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spi: spi-zyqnmp-gqspi: Add tap delay and Versal platform support
Merge series from Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>: A bunch of improvements to the driver: - Fix kernel-doc warnings in GQSPI driver. - Avoid setting CPOL, CPHA & baud rate multiple times. - Add Versal platform support in GQSPI driver. - Add tap delay support in GQSPI driver.
This commit is contained in:
Mark Brown
commit
f74d21829b
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@ -14,7 +14,9 @@ allOf:
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properties:
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compatible:
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const: xlnx,zynqmp-qspi-1.0
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enum:
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- xlnx,versal-qspi-1.0
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- xlnx,zynqmp-qspi-1.0
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reg:
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maxItems: 2
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@ -843,6 +843,13 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value)
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
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int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
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{
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return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_TAPDELAY_BYPASS,
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index, value, NULL);
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_set_tapdelay_bypass);
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/**
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* zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status
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* @value: Status value to be written
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@ -16,6 +16,7 @@
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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@ -34,6 +35,7 @@
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#define GQSPI_RXD_OFST 0x00000120
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#define GQSPI_TX_THRESHOLD_OFST 0x00000128
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#define GQSPI_RX_THRESHOLD_OFST 0x0000012C
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#define IOU_TAPDLY_BYPASS_OFST 0x0000003C
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#define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
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#define GQSPI_GEN_FIFO_OFST 0x00000140
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#define GQSPI_SEL_OFST 0x00000144
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@ -48,6 +50,7 @@
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#define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
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#define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
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#define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
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#define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8
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/* GQSPI register bit masks */
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#define GQSPI_SEL_MASK 0x00000001
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@ -136,11 +139,37 @@
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#define GQSPI_MAX_NUM_CS 2 /* Maximum number of chip selects */
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#define GQSPI_USE_DATA_DLY 0x1
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#define GQSPI_USE_DATA_DLY_SHIFT 31
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#define GQSPI_DATA_DLY_ADJ_VALUE 0x2
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#define GQSPI_DATA_DLY_ADJ_SHIFT 28
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#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x1
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#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 0x3
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#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1
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#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 0x2
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/* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
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#define QSPI_QUIRK_HAS_TAPDELAY BIT(0)
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#define GQSPI_FREQ_37_5MHZ 37500000
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#define GQSPI_FREQ_40MHZ 40000000
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#define GQSPI_FREQ_100MHZ 100000000
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#define GQSPI_FREQ_150MHZ 150000000
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#define SPI_AUTOSUSPEND_TIMEOUT 3000
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enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
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/**
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* struct qspi_platform_data - zynqmp qspi platform data structure
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* @quirks: Flags is used to identify the platform
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*/
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struct qspi_platform_data {
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u32 quirks;
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};
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/**
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* struct zynqmp_qspi - Defines qspi driver instance
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* @ctlr: Pointer to the spi controller information
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* @regs: Virtual address of the QSPI controller registers
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* @refclk: Pointer to the peripheral clock
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* @pclk: Pointer to the APB clock
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@ -157,6 +186,9 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
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* @genfifoentry: Used for storing the genfifoentry instruction.
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* @mode: Defines the mode in which QSPI is operating
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* @data_completion: completion structure
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* @op_lock: Operational lock
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* @speed_hz: Current SPI bus clock speed in hz
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* @has_tapdelay: Used for tapdelay register available in qspi
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*/
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struct zynqmp_qspi {
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struct spi_controller *ctlr;
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@ -177,6 +209,8 @@ struct zynqmp_qspi {
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enum mode_type mode;
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struct completion data_completion;
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struct mutex op_lock;
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u32 speed_hz;
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bool has_tapdelay;
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};
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/**
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@ -249,6 +283,56 @@ static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
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}
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}
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/**
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* zynqmp_qspi_set_tapdelay: To configure qspi tap delays
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* @xqspi: Pointer to the zynqmp_qspi structure
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* @baudrateval: Buadrate to configure
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*/
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static void zynqmp_qspi_set_tapdelay(struct zynqmp_qspi *xqspi, u32 baudrateval)
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{
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u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
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u32 reqhz = 0;
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clk_rate = clk_get_rate(xqspi->refclk);
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reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
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if (!xqspi->has_tapdelay) {
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if (reqhz <= GQSPI_FREQ_40MHZ) {
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zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,
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PM_TAPDELAY_BYPASS_ENABLE);
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} else if (reqhz <= GQSPI_FREQ_100MHZ) {
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zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,
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PM_TAPDELAY_BYPASS_ENABLE);
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lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
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datadlyadj |= ((GQSPI_USE_DATA_DLY <<
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GQSPI_USE_DATA_DLY_SHIFT)
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| (GQSPI_DATA_DLY_ADJ_VALUE <<
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GQSPI_DATA_DLY_ADJ_SHIFT));
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} else if (reqhz <= GQSPI_FREQ_150MHZ) {
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lpbkdlyadj |= GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK;
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}
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} else {
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if (reqhz <= GQSPI_FREQ_37_5MHZ) {
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tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
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TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
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} else if (reqhz <= GQSPI_FREQ_100MHZ) {
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tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
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TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
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lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
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datadlyadj |= (GQSPI_USE_DATA_DLY <<
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GQSPI_USE_DATA_DLY_SHIFT);
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} else if (reqhz <= GQSPI_FREQ_150MHZ) {
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lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK
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| (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
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GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT));
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}
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zynqmp_gqspi_write(xqspi,
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IOU_TAPDLY_BYPASS_OFST, tapdlybypass);
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}
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zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, lpbkdlyadj);
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zynqmp_gqspi_write(xqspi, GQSPI_DATA_DLY_ADJ_OFST, datadlyadj);
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}
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/**
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* zynqmp_qspi_init_hw - Initialize the hardware
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* @xqspi: Pointer to the zynqmp_qspi structure
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@ -264,12 +348,15 @@ static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
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* - Enable manual slave select
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* - Enable manual start
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* - Deselect all the chip select lines
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* - Set the little endian mode of TX FIFO and
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* - Set the little endian mode of TX FIFO
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* - Set clock phase
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* - Set clock polarity and
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* - Enable the QSPI controller
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*/
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static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
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{
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u32 config_reg;
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u32 config_reg, baud_rate_val = 0;
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ulong clk_rate;
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/* Select the GQSPI mode */
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zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
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@ -303,21 +390,37 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
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config_reg |= GQSPI_CFG_WP_HOLD_MASK;
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/* Clear pre-scalar by default */
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config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
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/* CPHA 0 */
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config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
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/* CPOL 0 */
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config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
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/* Set CPHA */
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if (xqspi->ctlr->mode_bits & SPI_CPHA)
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config_reg |= GQSPI_CFG_CLK_PHA_MASK;
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else
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config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
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/* Set CPOL */
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if (xqspi->ctlr->mode_bits & SPI_CPOL)
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config_reg |= GQSPI_CFG_CLK_POL_MASK;
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else
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config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
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/* Set the clock frequency */
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clk_rate = clk_get_rate(xqspi->refclk);
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while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
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(clk_rate /
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(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > xqspi->speed_hz)
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baud_rate_val++;
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config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
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config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
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zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
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/* Set the tapdelay for clock frequency */
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zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
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/* Clear the TX and RX FIFO */
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zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
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GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
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GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
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GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
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/* Set by default to allow for high frequencies */
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zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
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zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
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GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
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/* Reset thresholds */
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zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
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GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
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@ -455,30 +558,30 @@ static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
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struct spi_device *qspi)
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{
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ulong clk_rate;
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u32 config_reg, baud_rate_val = 0;
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u32 config_reg, req_speed_hz, baud_rate_val = 0;
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/* Set the clock frequency */
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/* If req_hz == 0, default to lowest speed */
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clk_rate = clk_get_rate(xqspi->refclk);
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req_speed_hz = qspi->max_speed_hz;
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while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
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(clk_rate /
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(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)
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baud_rate_val++;
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if (xqspi->speed_hz != req_speed_hz) {
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xqspi->speed_hz = req_speed_hz;
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config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
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/* Set the clock frequency */
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/* If req_speed_hz == 0, default to lowest speed */
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clk_rate = clk_get_rate(xqspi->refclk);
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/* Set the QSPI clock phase and clock polarity */
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config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
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while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
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(clk_rate /
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(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) >
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req_speed_hz)
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baud_rate_val++;
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if (qspi->mode & SPI_CPHA)
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config_reg |= GQSPI_CFG_CLK_PHA_MASK;
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if (qspi->mode & SPI_CPOL)
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config_reg |= GQSPI_CFG_CLK_POL_MASK;
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config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
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config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
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config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
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zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
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config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
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config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
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zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
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zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
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}
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return 0;
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}
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@ -739,6 +842,8 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
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/**
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* zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
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* @xqspi: xqspi is a pointer to the GQSPI instance.
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*
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* Return: 0 on success; error value otherwise.
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*/
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static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
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{
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@ -823,6 +928,8 @@ static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
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* @rx_nbits: Receive buswidth.
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* @genfifoentry: genfifoentry is pointer to the variable in which
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* GENFIFO mask is returned to calling function
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*
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* Return: 0 on success; error value otherwise.
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*/
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static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
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u32 genfifoentry)
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@ -1087,6 +1194,16 @@ static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
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};
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static const struct qspi_platform_data versal_qspi_def = {
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.quirks = QSPI_QUIRK_HAS_TAPDELAY,
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};
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static const struct of_device_id zynqmp_qspi_of_match[] = {
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{ .compatible = "xlnx,zynqmp-qspi-1.0"},
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{ .compatible = "xlnx,versal-qspi-1.0", .data = &versal_qspi_def },
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{ /* End of table */ }
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};
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static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
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.exec_op = zynqmp_qspi_exec_op,
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};
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@ -1107,6 +1224,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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u32 num_cs;
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const struct qspi_platform_data *p_data;
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ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
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if (!ctlr)
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@ -1117,6 +1235,10 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
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xqspi->ctlr = ctlr;
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platform_set_drvdata(pdev, xqspi);
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p_data = of_device_get_match_data(&pdev->dev);
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if (p_data && (p_data->quirks & QSPI_QUIRK_HAS_TAPDELAY))
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xqspi->has_tapdelay = true;
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xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(xqspi->regs)) {
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ret = PTR_ERR(xqspi->regs);
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@ -1164,6 +1286,11 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
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goto clk_dis_all;
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}
|
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|
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ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
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SPI_TX_DUAL | SPI_TX_QUAD;
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ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
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xqspi->speed_hz = ctlr->max_speed_hz;
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/* QSPI controller initializations */
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zynqmp_qspi_init_hw(xqspi);
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@ -1199,10 +1326,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
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ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
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ctlr->mem_ops = &zynqmp_qspi_mem_ops;
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ctlr->setup = zynqmp_qspi_setup_op;
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ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
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ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
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ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
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SPI_TX_DUAL | SPI_TX_QUAD;
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ctlr->dev.of_node = np;
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ctlr->auto_runtime_pm = true;
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|
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@ -1253,11 +1377,6 @@ static int zynqmp_qspi_remove(struct platform_device *pdev)
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return 0;
|
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}
|
||||
|
||||
static const struct of_device_id zynqmp_qspi_of_match[] = {
|
||||
{ .compatible = "xlnx,zynqmp-qspi-1.0", },
|
||||
{ /* End of table */ }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
|
||||
|
||||
static struct platform_driver zynqmp_qspi_driver = {
|
||||
|
|
|
|||
|
|
@ -135,6 +135,7 @@ enum pm_ret_status {
|
|||
};
|
||||
|
||||
enum pm_ioctl_id {
|
||||
IOCTL_SET_TAPDELAY_BYPASS = 4,
|
||||
IOCTL_SD_DLL_RESET = 6,
|
||||
IOCTL_SET_SD_TAPDELAY = 7,
|
||||
IOCTL_SET_PLL_FRAC_MODE = 8,
|
||||
|
|
@ -389,6 +390,18 @@ enum zynqmp_pm_shutdown_subtype {
|
|||
ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
|
||||
};
|
||||
|
||||
enum tap_delay_signal_type {
|
||||
PM_TAPDELAY_NAND_DQS_IN = 0,
|
||||
PM_TAPDELAY_NAND_DQS_OUT = 1,
|
||||
PM_TAPDELAY_QSPI = 2,
|
||||
PM_TAPDELAY_MAX = 3,
|
||||
};
|
||||
|
||||
enum tap_delay_bypass_ctrl {
|
||||
PM_TAPDELAY_BYPASS_DISABLE = 0,
|
||||
PM_TAPDELAY_BYPASS_ENABLE = 1,
|
||||
};
|
||||
|
||||
enum ospi_mux_select_type {
|
||||
PM_OSPI_MUX_SEL_DMA = 0,
|
||||
PM_OSPI_MUX_SEL_LINEAR = 1,
|
||||
|
|
@ -484,6 +497,7 @@ int zynqmp_pm_write_ggs(u32 index, u32 value);
|
|||
int zynqmp_pm_read_ggs(u32 index, u32 *value);
|
||||
int zynqmp_pm_write_pggs(u32 index, u32 value);
|
||||
int zynqmp_pm_read_pggs(u32 index, u32 *value);
|
||||
int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
|
||||
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
|
||||
int zynqmp_pm_set_boot_health_status(u32 value);
|
||||
int zynqmp_pm_pinctrl_request(const u32 pin);
|
||||
|
|
@ -696,6 +710,11 @@ static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
|
||||
{
|
||||
return -ENODEV;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user