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Revert "isp10: rockchip: v0.1.6"

Browse Source 
This reverts commit 8bffe04905.

rk-isp10 is unused.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Iefade8a612b8cb88f3632e4ddea9410d5ece19b9
This commit is contained in:
Tao Huang 2021-08-06 19:52:35 +08:00
parent 369abda7d1
commit f6d261b111
23 changed files with 0 additions and 22176 deletions
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13
drivers/media/platform/rk-isp10/Kconfig
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# SPDX-License-Identifier: GPL-2.0
config VIDEO_RK_CIF_ISP10
tristate "Rockchip cif isp10 camera sensors"
depends on VIDEO_V4L2 && I2C
select VIDEOBUF2_CORE
select VIDEOBUF_GEN
select VIDEOBUF2_DMA_SG
select VIDEOBUF2_VMALLOC
default n
help
Say Y here to enable selecting the
rockchip cif isp10 camera sensors

4
drivers/media/platform/rk-isp10/Makefile
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# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_VIDEO_RK_CIF_ISP10) += video_cif_isp10.o
video_cif_isp10-objs += cif_isp10.o cif_isp10_img_src.o cif_isp10_img_src_v4l2-subdev.o cif_isp10_isp.o cif_isp10_pltfrm.o cif_isp10_rk3288.o cif_isp10_rk3399.o cif_isp10_v4l2.o

7228
drivers/media/platform/rk-isp10/cif_isp10.c
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817
drivers/media/platform/rk-isp10/cif_isp10.h
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/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#ifndef _CIF_ISP10_H
#define _CIF_ISP10_H
#include <linux/platform_device.h>
#include "cif_isp10_pltfrm.h"
#include "cif_isp10_img_src.h"
#include "cif_isp10_isp.h"
#include <linux/platform_data/rk_isp10_platform.h>
#include <media/v4l2-device.h>
#include <media/v4l2-controls_rockchip.h>
#include <media/videobuf2-v4l2.h>
#include <linux/dma-iommu.h>
#include <drm/rockchip_drm.h>
#include <linux/dma-mapping.h>
#include <linux/dma-buf.h>
/*****************************************************************************/
#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG)
#define CIF_ISP10_MODE_DMA_CONTIG 1
#endif
#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG)
#define CIF_ISP10_MODE_DMA_SG 1
#endif
#if !defined(CIF_ISP10_MODE_DMA_CONTIG) && \
!defined(CIF_ISP10_MODE_DMA_SG)
#error One of the videobuf buffer modes(COTING/SG) \
must be selected in the config
#endif
/* Definitions */
#define CONFIG_CIF_ISP_AUTO_UPD_CFG_BUG
#define CIF_ISP10_NUM_INPUTS 10
/* FORMAT */
#define MAX_NB_FORMATS 30
#define CONTRAST_DEF 0x80
#define BRIGHTNESS_DEF 0x0
#define HUE_DEF 0x0
/*
* MIPI CSI2.0
*/
#define CSI2_DT_YUV420_8b (0x18)
#define CSI2_DT_YUV420_10b (0x19)
#define CSI2_DT_YUV422_8b (0x1E)
#define CSI2_DT_YUV422_10b (0x1F)
#define CSI2_DT_RGB565 (0x22)
#define CSI2_DT_RGB666 (0x23)
#define CSI2_DT_RGB888 (0x24)
#define CSI2_DT_RAW8 (0x2A)
#define CSI2_DT_RAW10 (0x2B)
#define CSI2_DT_RAW12 (0x2C)
enum cif_isp10_img_src_state {
CIF_ISP10_IMG_SRC_STATE_OFF = 0,
CIF_ISP10_IMG_SRC_STATE_SW_STNDBY = 1,
CIF_ISP10_IMG_SRC_STATE_STREAMING = 2
};
enum cif_isp10_state {
/* path not yet opened: */
CIF_ISP10_STATE_DISABLED = 0,
/* path opened but not yet configured: */
CIF_ISP10_STATE_INACTIVE = 1,
/* path opened and configured, ready for streaming: */
CIF_ISP10_STATE_READY = 2,
/* path is streaming: */
CIF_ISP10_STATE_STREAMING = 3
};
enum cif_isp10_pm_state {
CIF_ISP10_PM_STATE_OFF,
CIF_ISP10_PM_STATE_SUSPENDED,
CIF_ISP10_PM_STATE_SW_STNDBY,
CIF_ISP10_PM_STATE_STREAMING
};
enum cif_isp10_ispstate {
CIF_ISP10_STATE_IDLE = 0,
CIF_ISP10_STATE_RUNNING = 1,
CIF_ISP10_STATE_STOPPING = 2
};
enum cif_isp10_inp {
CIF_ISP10_INP_CSI = 0x10000000,
CIF_ISP10_INP_CPI = 0x20000000,
CIF_ISP10_INP_DMA = 0x30000000, /* DMA -> ISP */
CIF_ISP10_INP_DMA_IE = 0x31000000, /* DMA -> IE */
CIF_ISP10_INP_DMA_SP = 0x32000000, /* DMA -> SP */
CIF_ISP10_INP_DMA_MAX = 0x33000000,
CIF_ISP10_INP_MAX = 0x7fffffff
};
#define CIF_ISP10_INP_IS_DMA(inp) \
(((inp) & 0xf0000000) == CIF_ISP10_INP_DMA)
#define CIF_ISP10_INP_IS_MIPI(inp) \
(((inp) & 0xf0000000) == CIF_ISP10_INP_CSI)
#define CIF_ISP10_INP_IS_DVP(inp) \
(((inp) & 0xf0000000) == CIF_ISP10_INP_CPI)
#define CIF_ISP10_INP_NEED_ISP(inp) \
((inp) < CIF_ISP10_INP_DMA_IE)
#define CIF_ISP10_INP_DMA_CNT() \
((CIF_ISP10_INP_DMA_MAX -\
CIF_ISP10_INP_DMA) >> 24)
enum cif_isp10_pinctrl_state {
CIF_ISP10_PINCTRL_STATE_SLEEP,
CIF_ISP10_PINCTRL_STATE_INACTIVE,
CIF_ISP10_PINCTRL_STATE_DEFAULT,
CIF_ISP10_PINCTRL_STATE_ACTIVE
};
enum cif_isp10_flash_mode {
CIF_ISP10_FLASH_MODE_OFF,
CIF_ISP10_FLASH_MODE_FLASH,
CIF_ISP10_FLASH_MODE_TORCH,
};
enum cif_isp10_cid {
CIF_ISP10_CID_FLASH_MODE = 0,
CIF_ISP10_CID_EXPOSURE_TIME = 1,
CIF_ISP10_CID_ANALOG_GAIN = 2,
CIF_ISP10_CID_WB_TEMPERATURE = 3,
CIF_ISP10_CID_BLACK_LEVEL = 4,
CIF_ISP10_CID_AUTO_GAIN = 5,
CIF_ISP10_CID_AUTO_EXPOSURE = 6,
CIF_ISP10_CID_AUTO_WHITE_BALANCE = 7,
CIF_ISP10_CID_FOCUS_ABSOLUTE = 8,
CIF_ISP10_CID_AUTO_N_PRESET_WHITE_BALANCE = 9,
CIF_ISP10_CID_SCENE_MODE = 10,
CIF_ISP10_CID_SUPER_IMPOSE = 11,
CIF_ISP10_CID_JPEG_QUALITY = 12,
CIF_ISP10_CID_IMAGE_EFFECT = 13,
CIF_ISP10_CID_HFLIP = 14,
CIF_ISP10_CID_VFLIP = 15,
CIF_ISP10_CID_AUTO_FPS = 16,
CIF_ISP10_CID_VBLANKING = 17,
CIF_ISP10_CID_ISO_SENSITIVITY = 18,
CIF_ISP10_CID_MIN_BUFFER_FOR_CAPTURE = 19,
CIF_ISP10_CID_TEST_PATTERN = 20,
};
/* correspond to bit field values */
enum cif_isp10_image_effect {
CIF_ISP10_IE_BW = 0,
CIF_ISP10_IE_NEGATIVE = 1,
CIF_ISP10_IE_SEPIA = 2,
CIF_ISP10_IE_C_SEL = 3,
CIF_ISP10_IE_EMBOSS = 4,
CIF_ISP10_IE_SKETCH = 5,
CIF_ISP10_IE_NONE /* not a bit field value */
};
#define CIF_ISP10_PIX_FMT_MASK 0xf0000000
#define CIF_ISP10_PIX_FMT_MASK_BPP 0x0003f000
#define CIF_ISP10_PIX_FMT_YUV_MASK_CPLANES 0x00000003
#define CIF_ISP10_PIX_FMT_YUV_MASK_UVSWAP 0x00000004
#define CIF_ISP10_PIX_FMT_YUV_MASK_YCSWAP 0x00000008
#define CIF_ISP10_PIX_FMT_YUV_MASK_X 0x00000f00
#define CIF_ISP10_PIX_FMT_YUV_MASK_Y 0x000000f0
#define CIF_ISP10_PIX_FMT_RGB_MASK_PAT 0x000000f0
#define CIF_ISP10_PIX_FMT_BAYER_MASK_PAT 0x000000f0
#define CIF_ISP10_PIX_FMT_GET_BPP(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_MASK_BPP) >> 12)
#define cif_isp10_pix_fmt_set_bpp(pix_fmt, bpp) \
{ \
pix_fmt = (((pix_fmt) & ~CIF_ISP10_PIX_FMT_MASK_BPP) | \
(((bpp) << 12) & CIF_ISP10_PIX_FMT_MASK_BPP)); \
}
#define CIF_ISP10_PIX_FMT_YUV_GET_NUM_CPLANES(pix_fmt) \
((pix_fmt) & CIF_ISP10_PIX_FMT_YUV_MASK_CPLANES)
#define CIF_ISP10_PIX_FMT_YUV_IS_YC_SWAPPED(pix_fmt) \
((pix_fmt) & CIF_ISP10_PIX_FMT_YUV_MASK_YCSWAP)
#define CIF_ISP10_PIX_FMT_YUV_IS_UV_SWAPPED(pix_fmt) \
((pix_fmt) & CIF_ISP10_PIX_FMT_YUV_MASK_UVSWAP)
#define CIF_ISP10_PIX_FMT_YUV_GET_X_SUBS(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_YUV_MASK_X) >> 8)
#define CIF_ISP10_PIX_FMT_YUV_GET_Y_SUBS(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_YUV_MASK_Y) >> 4)
#define cif_isp10_pix_fmt_set_y_subs(pix_fmt, y_subs) \
{ \
pix_fmt = (((pix_fmt) & ~CIF_ISP10_PIX_FMT_YUV_MASK_Y) | \
((y_subs << 4) & CIF_ISP10_PIX_FMT_YUV_MASK_Y)); \
}
#define cif_isp10_pix_fmt_set_x_subs(pix_fmt, x_subs) \
{ \
pix_fmt = (((pix_fmt) & ~CIF_ISP10_PIX_FMT_YUV_MASK_X) | \
(((x_subs) << 8) & CIF_ISP10_PIX_FMT_YUV_MASK_X)); \
}
#define cif_isp10_pix_fmt_set_yc_swapped(pix_fmt, yc_swapped) \
{ \
pix_fmt = (((pix_fmt) & ~CIF_ISP10_PIX_FMT_YUV_MASK_YCSWAP) | \
(((yc_swapped) << 3) & \
CIF_ISP10_PIX_FMT_YUV_MASK_YCSWAP)); \
}
#define CIF_ISP10_PIX_FMT_BAYER_PAT_IS_BGGR(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_BAYER_MASK_PAT) == 0x0)
#define CIF_ISP10_PIX_FMT_BAYER_PAT_IS_GBRG(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_BAYER_MASK_PAT) == 0x10)
#define CIF_ISP10_PIX_FMT_BAYER_PAT_IS_GRBG(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_BAYER_MASK_PAT) == 0x20)
#define CIF_ISP10_PIX_FMT_BAYER_PAT_IS_RGGB(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_BAYER_MASK_PAT) == 0x30)
#define CIF_ISP10_PIX_FMT_IS_YUV(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_MASK) == 0x10000000)
#define CIF_ISP10_PIX_FMT_IS_RGB(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_MASK) == 0x20000000)
#define CIF_ISP10_PIX_FMT_IS_RAW_BAYER(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_MASK) == 0x30000000)
#define CIF_ISP10_PIX_FMT_IS_JPEG(pix_fmt) \
(((pix_fmt) & CIF_ISP10_PIX_FMT_MASK) == 0x40000000)
#define CIF_ISP10_PIX_FMT_IS_INTERLEAVED(pix_fmt) \
(!CIF_ISP10_PIX_FMT_IS_YUV(pix_fmt) ||\
!CIF_ISP10_PIX_FMT_YUV_GET_NUM_CPLANES(pix_fmt))
#define CIF_ISP10_PIX_FMT_IS_Y_ONLY(pix_fmt) \
((CIF_ISP10_PIX_FMT_IS_YUV(pix_fmt) == 1) && \
(CIF_ISP10_PIX_FMT_YUV_GET_X_SUBS(pix_fmt) == 0) && \
(CIF_ISP10_PIX_FMT_YUV_GET_Y_SUBS(pix_fmt) == 0) && \
(CIF_ISP10_PIX_FMT_YUV_IS_YC_SWAPPED(pix_fmt) == 0))
#define CIF_ISP10_IMG_SRC_DATA_NUM 6
enum cif_isp10_pix_fmt {
/* YUV */
CIF_YUV400 = 0x10008000,
CIF_YVU400 = 0x10008004,
CIF_Y10 = 0x1000a000,
CIF_Y12 = 0x10010000,
CIF_YUV420I = 0x1000c220,
CIF_YUV420SP = 0x1000c221, /* NV12 */
CIF_YUV420P = 0x1000c222,
CIF_YVU420I = 0x1000c224,
CIF_YVU420SP = 0x1000c225, /* NV21 */
CIF_YVU420P = 0x1000c226, /* YV12 */
CIF_YUV422I = 0x10010240,
CIF_YUV422SP = 0x10010241,
CIF_YUV422P = 0x10010242,
CIF_YVU422I = 0x10010244,
CIF_YVU422SP = 0x10010245,
CIF_YVU422P = 0x10010246,
CIF_YUV444I = 0x10018440,
CIF_YUV444SP = 0x10018441,
CIF_YUV444P = 0x10018442,
CIF_YVU444I = 0x10018444,
CIF_YVU444SP = 0x10018445,
CIF_YVU444P = 0x10018446,
CIF_UYV400 = 0x10008008,
CIF_UYV420I = 0x1000c228,
CIF_UYV420SP = 0x1000c229,
CIF_UYV420P = 0x1000c22a,
CIF_VYU420I = 0x1000c22c,
CIF_VYU420SP = 0x1000c22d,
CIF_VYU420P = 0x1000c22e,
CIF_UYV422I = 0x10010248,
CIF_UYV422SP = 0x10010249,
CIF_UYV422P = 0x1001024a,
CIF_VYU422I = 0x1001024c,
CIF_VYU422SP = 0x1001024d,
CIF_VYU422P = 0x1001024e,
CIF_UYV444I = 0x10018448,
CIF_UYV444SP = 0x10018449,
CIF_UYV444P = 0x1001844a,
CIF_VYU444I = 0x1001844c,
CIF_VYU444SP = 0x1001844d,
CIF_VYU444P = 0x1001844e,
/* RGB */
CIF_RGB565 = 0x20010000,
CIF_RGB666 = 0x20012000,
CIF_RGB888 = 0x20020000,
/* RAW Bayer */
CIF_BAYER_SBGGR8 = 0x30008000,
CIF_BAYER_SGBRG8 = 0x30008010,
CIF_BAYER_SGRBG8 = 0x30008020,
CIF_BAYER_SRGGB8 = 0x30008030,
CIF_BAYER_SBGGR10 = 0x3000a000,
CIF_BAYER_SGBRG10 = 0x3000a010,
CIF_BAYER_SGRBG10 = 0x3000a020,
CIF_BAYER_SRGGB10 = 0x3000a030,
CIF_BAYER_SBGGR12 = 0x3000c000,
CIF_BAYER_SGBRG12 = 0x3000c010,
CIF_BAYER_SGRBG12 = 0x3000c020,
CIF_BAYER_SRGGB12 = 0x3000c030,
/* JPEG */
CIF_JPEG = 0x40008000,
/* Data */
CIF_DATA = 0x70000000,
CIF_UNKNOWN_FORMAT = 0x80000000
};
enum cif_isp10_stream_id {
CIF_ISP10_STREAM_SP = 0x1,
CIF_ISP10_STREAM_MP = 0x2,
CIF_ISP10_STREAM_DMA = 0x4,
CIF_ISP10_STREAM_ISP = 0x8
};
#define CIF_ISP10_ALL_STREAMS \
(CIF_ISP10_STREAM_SP | \
CIF_ISP10_STREAM_MP | \
CIF_ISP10_STREAM_DMA)
enum cif_isp10_buff_fmt {
/* values correspond to bitfield values */
CIF_ISP10_BUFF_FMT_PLANAR = 0,
CIF_ISP10_BUFF_FMT_SEMIPLANAR = 1,
CIF_ISP10_BUFF_FMT_INTERLEAVED = 2,
CIF_ISP10_BUFF_FMT_RAW8 = 0,
CIF_ISP10_BUFF_FMT_RAW12 = 2
};
enum cif_isp10_jpeg_header {
CIF_ISP10_JPEG_HEADER_JFIF,
CIF_ISP10_JPEG_HEADER_NONE
};
struct cif_isp10_csi_config {
u32 vc;
u32 nb_lanes;
u32 bit_rate;
/* really used csi */
u32 used_csi; /* xuhf@rock-chips.com: v1.0.4 */
};
struct cif_isp10_paraport_config {
u32 cif_vsync;
u32 cif_hsync;
u32 cif_pclk;
/* really used csi */
u32 used_csi; /* xuhf@rock-chips.com: v1.0.4 */
};
struct cif_isp10_frm_intrvl {
u32 numerator;
u32 denominator;
};
struct cif_isp10_frm_fmt {
u32 width;
u32 height;
u32 stride;
u32 std_id;
enum cif_isp10_pix_fmt pix_fmt;
enum cif_isp10_pix_fmt_quantization quantization;
struct v4l2_rect defrect;
};
struct cif_isp10_strm_fmt {
struct cif_isp10_frm_fmt frm_fmt;
struct cif_isp10_frm_intrvl frm_intrvl;
};
struct cif_isp10_strm_fmt_desc {
bool discrete_frmsize;
struct {
u32 width;
u32 height;
} min_frmsize;
struct {
u32 width;
u32 height;
} max_frmsize;
enum cif_isp10_pix_fmt pix_fmt;
bool discrete_intrvl;
struct cif_isp10_frm_intrvl min_intrvl;
struct cif_isp10_frm_intrvl max_intrvl;
struct v4l2_rect defrect;
u32 std_id;
};
struct cif_isp10_rsz_config {
struct cif_isp10_frm_fmt *input;
struct cif_isp10_frm_fmt output;
bool ycflt_adjust;
bool ism_adjust;
};
struct cif_isp10_dcrop_config {
unsigned int h_offs;
unsigned int v_offs;
unsigned int h_size;
unsigned int v_size;
};
struct cif_isp10_sp_config {
struct cif_isp10_rsz_config rsz_config;
struct cif_isp10_dcrop_config dcrop;
};
struct cif_isp10_mp_config {
struct cif_isp10_rsz_config rsz_config;
struct cif_isp10_dcrop_config dcrop;
};
struct cif_isp10_mi_path_config {
struct cif_isp10_frm_fmt *input;
struct cif_isp10_frm_fmt output;
u32 llength;
u32 curr_buff_addr;
u32 next_buff_addr;
u32 cb_offs;
u32 cr_offs;
u32 y_size;
u32 cb_size;
u32 cr_size;
u32 burst_len;
bool busy;
/* FOR BT655: 0 = ODD, 1 = EVEN */
bool field_flag;
/* for interlace offset */
u32 vir_len_offset;
};
struct cif_isp10_zoom_buffer_info {
u32 width;
u32 height;
unsigned long buff_addr;
u32 flags;
};
struct cif_isp10_mi_config {
bool raw_enable;
u32 async_updt;
struct cif_isp10_mi_path_config mp;
struct cif_isp10_mi_path_config sp;
struct cif_isp10_mi_path_config dma;
};
struct cif_isp10_buffer {
struct vb2_v4l2_buffer vb;
struct list_head queue;
unsigned long int size;
};
struct cif_isp10_metadata_s {
unsigned int cnt;
unsigned int vmas;
spinlock_t spinlock;
unsigned char *d;
};
struct cif_isp10_stream {
enum cif_isp10_stream_id id;
enum cif_isp10_state state;
enum cif_isp10_state saved_state;
struct list_head buf_queue;
struct cif_isp10_buffer *curr_buf;
struct cif_isp10_buffer *next_buf;
bool updt_cfg;
bool stall;
bool stop;
CIF_ISP10_PLTFRM_EVENT done;
struct cif_isp10_metadata_s metadata;
};
struct cif_isp10_jpeg_config {
bool enable;
bool busy;
u32 ratio;
struct cif_isp10_frm_fmt *input;
enum cif_isp10_jpeg_header header;
};
struct cif_isp10_ie_config {
enum cif_isp10_image_effect effect;
};
/* IS */
struct cif_isp10_ism_params {
unsigned int ctrl;
unsigned int recenter;
unsigned int h_offs;
unsigned int v_offs;
unsigned int h_size;
unsigned int v_size;
unsigned int max_dx;
unsigned int max_dy;
unsigned int displace;
};
struct cif_isp10_ism_config {
bool ism_en;
struct cif_isp10_ism_params ism_params;
bool ism_update_needed;
};
struct cif_isp10_isp_config {
bool si_enable;
struct cif_isp10_ie_config ie_config;
struct cif_isp10_ism_config ism_config;
struct cif_isp10_frm_fmt *input;
struct cif_isp10_frm_fmt output;
};
struct cif_isp10_config {
CIF_ISP10_PLTFRM_MEM_IO_ADDR base_addr;
enum cif_isp10_flash_mode flash_mode;
enum cif_isp10_inp input_sel;
struct cif_isp10_jpeg_config jpeg_config;
struct cif_isp10_mi_config mi_config;
struct cif_isp10_sp_config sp_config;
struct cif_isp10_mp_config mp_config;
struct cif_isp10_strm_fmt img_src_output;
struct cif_isp10_isp_config isp_config;
struct pltfrm_cam_itf cam_itf;
bool out_of_buffer_stall;
};
struct cif_isp10_mi_state {
unsigned long flags;
unsigned int isp_ctrl;
unsigned int y_base_ad;
unsigned int y_size;
unsigned int cb_base_ad;
unsigned int cb_size;
unsigned int cr_base_ad;
unsigned int cr_size;
};
struct cif_isp10_img_src_exp {
struct list_head list;
struct cif_isp10_img_src_ext_ctrl exp;
};
struct cif_isp10_img_src_data {
unsigned int v_frame_id;
struct isp_supplemental_sensor_mode_data data;
};
struct cif_isp10_img_src_exps {
spinlock_t lock; /* protect list */
struct list_head list;
struct mutex mutex; /* protect frm_exp */
struct cif_isp10_img_src_data data[CIF_ISP10_IMG_SRC_DATA_NUM];
unsigned char exp_idx;
unsigned char exp_valid_frms[2];
bool inited;
};
enum cif_isp10_isp_vs_cmd {
CIF_ISP10_VS_EXIT = 0,
CIF_ISP10_VS_EXP = 1
};
struct cif_isp10_isp_vs_work {
struct work_struct work;
struct cif_isp10_device *dev;
enum cif_isp10_isp_vs_cmd cmd;
void *param;
};
struct cif_isp10_fmt {
char *name;
u32 fourcc;
int flags;
int depth;
unsigned char rotation;
unsigned char overlay;
};
#ifdef CIF_ISP10_MODE_DMA_SG
struct cif_isp10_iommu {
int client_fd;
int map_fd;
unsigned long linear_addr;
unsigned long len;
};
struct cif_isp10_dma_buf {
struct dma_buf *dma_buffer;
struct dma_buf_attachment *attach;
struct sg_table *sgt;
dma_addr_t dma_addr;
int fd;
};
#endif
struct cif_isp10_device {
unsigned int dev_id;
CIF_ISP10_PLTFRM_DEVICE dev;
struct v4l2_device v4l2_dev;
enum cif_isp10_pm_state pm_state;
enum cif_isp10_img_src_state img_src_state;
enum cif_isp10_ispstate isp_state;
spinlock_t vbq_lock; /* spinlock for videobuf queues */
spinlock_t vbreq_lock; /* spinlock for videobuf requeues */
spinlock_t iowrite32_verify_lock;
spinlock_t isp_state_lock;
wait_queue_head_t isp_stop_wait; /* wait while isp stop */
unsigned int isp_stop_flags;
struct cif_isp10_img_src *img_src;
struct cif_isp10_img_src *img_src_array[CIF_ISP10_NUM_INPUTS];
unsigned int img_src_cnt;
struct vb2_alloc_ctx *alloc_ctx;
#ifdef CIF_ISP10_MODE_DMA_SG
struct iommu_domain *domain;
struct cif_isp10_dma_buf dma_buffer[VB2_MAX_FRAME];
int dma_buf_cnt;
#endif
struct cif_isp10_img_src_exps img_src_exps;
struct cif_isp10_config config;
struct cif_isp10_isp_dev isp_dev;
struct cif_isp10_stream sp_stream;
struct cif_isp10_stream mp_stream;
struct cif_isp10_stream dma_stream;
struct workqueue_struct *vs_wq;
void (*sof_event)(struct cif_isp10_device *dev, __u32 frame_sequence);
/*
* requeue_bufs() is used to clean and rebuild the local buffer
* lists xx_stream.buf_queue. This is used e.g. in the CAPTURE use
* case where we start MP and SP separately and needs to shortly
* stop and start SP when start MP
*/
void (*requeue_bufs)(struct cif_isp10_device *dev,
enum cif_isp10_stream_id stream_id);
bool b_isp_frame_in;
bool b_mi_frame_end;
int otf_zsl_mode;
struct flash_timeinfo_s flash_t;
struct pltfrm_soc_cfg soc_cfg;
void *nodes;
struct mutex api_mutex; /* user api mutex */
};
struct cif_isp10_fmt *get_cif_isp10_output_format(int index);
int get_cif_isp10_output_format_size(void);
struct v4l2_fmtdesc *get_cif_isp10_output_format_desc(int index);
int get_cif_isp10_output_format_desc_size(void);
/* Clean code starts from here */
static inline
struct cif_isp10_stream *to_stream_by_id(struct cif_isp10_device *dev,
enum cif_isp10_stream_id id)
{
if (WARN_ON(id != CIF_ISP10_STREAM_MP &&
id != CIF_ISP10_STREAM_SP &&
id != CIF_ISP10_STREAM_DMA &&
id != CIF_ISP10_STREAM_ISP))
return &dev->sp_stream;
switch (id) {
case CIF_ISP10_STREAM_MP:
return &dev->mp_stream;
case CIF_ISP10_STREAM_SP:
return &dev->sp_stream;
case CIF_ISP10_STREAM_DMA:
return &dev->dma_stream;
case CIF_ISP10_STREAM_ISP:
return NULL;
}
return NULL;
}
struct cif_isp10_device *cif_isp10_create(
CIF_ISP10_PLTFRM_DEVICE pdev,
void (*sof_event)(struct cif_isp10_device *dev, __u32 frame_sequence),
void (*requeue_bufs)(struct cif_isp10_device *dev,
enum cif_isp10_stream_id stream_id),
struct pltfrm_soc_cfg *soc_cfg);
void cif_isp10_destroy(
struct cif_isp10_device *dev);
int cif_isp10_init(
struct cif_isp10_device *dev,
u32 stream_ids);
int cif_isp10_release(
struct cif_isp10_device *dev,
int stream_ids);
int cif_isp10_streamon(
struct cif_isp10_device *dev,
u32 stream_ids);
int cif_isp10_streamoff(
struct cif_isp10_device *dev,
u32 stream_ids);
int cif_isp10_g_input(
struct cif_isp10_device *dev,
enum cif_isp10_inp *inp);
int cif_isp10_s_input(
struct cif_isp10_device *dev,
enum cif_isp10_inp inp);
int cif_isp10_s_fmt(
struct cif_isp10_device *dev,
enum cif_isp10_stream_id stream_id,
struct cif_isp10_strm_fmt *strm_fmt,
u32 stride);
int cif_isp10_resume(
struct cif_isp10_device *dev);
int cif_isp10_suspend(
struct cif_isp10_device *dev);
int cif_isp10_qbuf(
struct cif_isp10_device *dev,
enum cif_isp10_stream_id stream,
struct cif_isp10_buffer *buf);
int cif_isp10_reqbufs(
struct cif_isp10_device *dev,
enum cif_isp10_stream_id strm,
struct v4l2_requestbuffers *req);
int cif_isp10_mmap(
struct cif_isp10_device *dev,
enum cif_isp10_stream_id stream_id,
struct vm_area_struct *vma);
int cif_isp10_get_target_frm_size(
struct cif_isp10_device *dev,
u32 *target_width,
u32 *target_height);
int cif_isp10_calc_isp_cropping(
struct cif_isp10_device *dev,
u32 *width,
u32 *height,
u32 *h_offs,
u32 *v_offs);
const char *cif_isp10_g_input_name(
struct cif_isp10_device *dev,
enum cif_isp10_inp inp);
int cif_isp10_calc_min_out_buff_size(
struct cif_isp10_device *dev,
enum cif_isp10_stream_id stream_id,
u32 *size,
bool payload);
int cif_isp10_s_ctrl(
struct cif_isp10_device *dev,
const enum cif_isp10_cid id,
int val);
int cif_isp10_s_vb_metadata(
struct cif_isp10_device *dev,
struct cif_isp10_isp_readout_work *readout_work);
int cif_isp10_s_exp(
struct cif_isp10_device *dev,
struct cif_isp10_img_src_ext_ctrl *exp_ctrl,
bool cls_exp);
int cif_isp10_s_vcm(
struct cif_isp10_device *dev,
unsigned int id,
int val);
void cif_isp10_sensor_mode_data_sync(
struct cif_isp10_device *dev,
unsigned int frame_id,
struct isp_supplemental_sensor_mode_data *data);
#endif

218
drivers/media/platform/rk-isp10/cif_isp10_img_src.c
View File

@ -1,218 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#include <linux/kernel.h>
#include <linux/platform_data/rk_isp10_platform.h>
#include "cif_isp10.h"
#include "cif_isp10_img_src_ops.h"
struct cif_isp10_img_src {
void *img_src;
const struct cif_isp10_img_src_ops *ops;
};
struct cif_isp10_img_src *cif_isp10_img_src_to_img_src(
CIF_ISP10_PLTFRM_DEVICE dev,
struct pltfrm_soc_cfg *soc_cfg)
{
int ret = 0;
int i;
const char *device_type;
struct cif_isp10_img_src *img_src;
img_src = devm_kzalloc(dev, sizeof(*img_src), GFP_KERNEL);
if (!img_src) {
ret = -ENOMEM;
goto err;
}
device_type = cif_isp10_pltfrm_get_device_type(dev);
img_src->ops = NULL;
for (i = 0; i < ARRAY_SIZE(cif_isp10_img_src_ops); i++) {
if (!strcmp(device_type, cif_isp10_img_src_ops->device_type)) {
img_src->ops = &cif_isp10_img_src_ops[i].ops;
break;
}
}
if (!img_src->ops) {
cif_isp10_pltfrm_pr_err(NULL,
"unsupported device type %s\n",
device_type);
ret = -EINVAL;
goto err;
}
WARN_ON(!img_src->ops->to_img_src);
WARN_ON(!img_src->ops->s_streaming);
WARN_ON(!img_src->ops->s_power);
WARN_ON(!img_src->ops->enum_strm_fmts);
WARN_ON(!img_src->ops->s_strm_fmt);
WARN_ON(!img_src->ops->g_ctrl);
WARN_ON(!img_src->ops->s_ctrl);
img_src->img_src = img_src->ops->to_img_src(dev, soc_cfg);
if (IS_ERR_OR_NULL(img_src->img_src)) {
cif_isp10_pltfrm_pr_err(NULL,
"to_img_src failed!\n");
ret = -EFAULT;
goto err;
}
return img_src;
err:
cif_isp10_pltfrm_pr_err(NULL, "failed with error %d\n",
ret);
if (!IS_ERR_OR_NULL(img_src))
devm_kfree(dev, img_src);
return ERR_PTR(ret);
}
int cif_isp10_img_src_s_streaming(
struct cif_isp10_img_src *img_src,
bool enable)
{
return img_src->ops->s_streaming(img_src->img_src, enable);
}
int cif_isp10_img_src_s_power(
struct cif_isp10_img_src *img_src,
bool on)
{
return img_src->ops->s_power(img_src->img_src, on);
}
int cif_isp10_img_src_enum_strm_fmts(
struct cif_isp10_img_src *img_src,
u32 index,
struct cif_isp10_strm_fmt_desc *strm_fmt_desc)
{
return img_src->ops->enum_strm_fmts(img_src->img_src,
index, strm_fmt_desc);
}
int cif_isp10_img_src_s_strm_fmt(
struct cif_isp10_img_src *img_src,
struct cif_isp10_strm_fmt *strm_fmt)
{
if (!img_src) {
cif_isp10_pltfrm_pr_err(NULL, "img_src is NULL\n");
return -EINVAL;
}
return img_src->ops->s_strm_fmt(img_src->img_src, strm_fmt);
}
int cif_isp10_img_src_g_ctrl(
struct cif_isp10_img_src *img_src,
int id,
int *val)
{
if (!img_src) {
cif_isp10_pltfrm_pr_err(NULL, "img_src is NULL\n");
return -EINVAL;
}
return img_src->ops->g_ctrl(img_src->img_src, id, val);
}
int cif_isp10_img_src_s_ctrl(
struct cif_isp10_img_src *img_src,
int id,
int val)
{
if (!img_src) {
cif_isp10_pltfrm_pr_err(NULL, "img_src is NULL\n");
return -EINVAL;
}
return img_src->ops->s_ctrl(img_src->img_src, id, val);
}
int cif_isp10_img_src_s_ext_ctrls(
struct cif_isp10_img_src *img_src,
struct cif_isp10_img_src_ext_ctrl *ctrl)
{
if (!img_src) {
cif_isp10_pltfrm_pr_err(NULL, "img_src is NULL\n");
return -EINVAL;
}
return img_src->ops->s_ext_ctrls(img_src->img_src, ctrl);
}
long cif_isp10_img_src_ioctl(
struct cif_isp10_img_src *img_src,
unsigned int cmd,
void *arg)
{
if (!img_src) {
cif_isp10_pltfrm_pr_err(NULL, "img_src is NULL\n");
return -EINVAL;
}
return img_src->ops->ioctl(img_src->img_src, cmd, arg);
}
const char *cif_isp10_img_src_g_name(
struct cif_isp10_img_src *img_src)
{
if (!img_src) {
cif_isp10_pltfrm_pr_err(NULL, "img_src is NULL\n");
return ERR_PTR(-EINVAL);
}
return img_src->ops->g_name(img_src->img_src);
}
void *cif_isp10_img_src_g_img_src(
struct cif_isp10_img_src *img_src)
{
if (img_src) {
return img_src->img_src;
}
return NULL;
}
int cif_isp10_img_src_s_frame_interval(
struct cif_isp10_img_src *img_src,
struct cif_isp10_frm_intrvl *frm_intrvl)
{
if (img_src)
return img_src->ops->s_frame_interval(
img_src->img_src,
frm_intrvl);
return -EINVAL;
}
int cif_isp10_img_src_g_frame_interval(
struct cif_isp10_img_src *img_src,
struct cif_isp10_frm_intrvl *frm_intrvl)
{
if (img_src)
return img_src->ops->g_frame_interval(
img_src->img_src,
frm_intrvl);
return -EINVAL;
}
int cif_isp10_img_src_enum_frame_size(
struct cif_isp10_img_src *img_src,
void *fse)
{
if (img_src)
return img_src->ops->enum_frame_size(
img_src->img_src,
fse);
return -EINVAL;
}

99
drivers/media/platform/rk-isp10/cif_isp10_img_src.h
View File

@ -1,99 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#ifndef _CIF_ISP10_IMG_SRC_H
#define _CIF_ISP10_IMG_SRC_H
struct cif_isp10_img_src;
struct cif_isp10_strm_fmt_desc;
struct cif_isp10_strm_fmt;
struct cif_isp10_csi_config;
enum cif_isp10_pix_fmt;
struct cif_isp10_frm_intrvl;
struct cif_isp10_img_src;
struct pltfrm_soc_cfg;
struct cif_isp10_img_src_ctrl {
unsigned int id;
int val;
};
struct cif_isp10_img_src_ext_ctrl {
int cnt;
unsigned int class;
struct cif_isp10_img_src_ctrl *ctrls;
};
struct cif_isp10_img_src *cif_isp10_img_src_to_img_src(
CIF_ISP10_PLTFRM_DEVICE dev,
struct pltfrm_soc_cfg *soc_cfg);
int cif_isp10_img_src_s_streaming(
struct cif_isp10_img_src *img_src,
bool enable);
int cif_isp10_img_src_s_power(
struct cif_isp10_img_src *img_src,
bool on);
int cif_isp10_img_src_enum_strm_fmts(
struct cif_isp10_img_src *img_src,
u32 index,
struct cif_isp10_strm_fmt_desc *strm_fmt_desc);
int cif_isp10_img_src_s_strm_fmt(
struct cif_isp10_img_src *img_src,
struct cif_isp10_strm_fmt *strm_fmt);
int cif_isp10_img_src_g_ctrl(
struct cif_isp10_img_src *img_src,
int id,
int *val);
int cif_isp10_img_src_s_ctrl(
struct cif_isp10_img_src *img_src,
int id,
int val);
const char *cif_isp10_img_src_g_name(
struct cif_isp10_img_src *img_src);
int cif_isp10_img_src_s_ext_ctrls(
struct cif_isp10_img_src *img_src,
struct cif_isp10_img_src_ext_ctrl *ctrls);
long cif_isp10_img_src_ioctl(
struct cif_isp10_img_src *img_src,
unsigned int cmd,
void *arg);
void *cif_isp10_img_src_g_img_src(
struct cif_isp10_img_src *img_src);
int cif_isp10_img_src_s_frame_interval(
struct cif_isp10_img_src *img_src,
struct cif_isp10_frm_intrvl *frm_intrvl);
int cif_isp10_img_src_g_frame_interval(
struct cif_isp10_img_src *img_src,
struct cif_isp10_frm_intrvl *frm_intrvl);
int cif_isp10_img_src_enum_frame_size(
struct cif_isp10_img_src *img_src,
void *fse);
#endif

104
drivers/media/platform/rk-isp10/cif_isp10_img_src_ops.h
View File

@ -1,104 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#ifndef _CIF_ISP10_IMG_SRC_OPS_H
#define _CIF_ISP10_IMG_SRC_OPS_H
#include <linux/platform_data/rk_isp10_platform.h>
#include "cif_isp10_img_src_v4l2-subdev.h"
struct cif_isp10_img_src_ops {
void * (*to_img_src)(
CIF_ISP10_PLTFRM_DEVICE dev,
struct pltfrm_soc_cfg *soc_cfg);
int (*s_streaming)(
void *img_src,
bool enable);
int (*s_power)(
void *img_src,
bool on);
int (*enum_strm_fmts)(
void *img_src,
u32 index,
struct cif_isp10_strm_fmt_desc *strm_fmt_desc);
int (*s_strm_fmt)(
void *img_src,
struct cif_isp10_strm_fmt *strm_fmt);
int (*g_ctrl)(
void *img_src,
int id,
int *val);
const char * (*g_name)(
void *img_src);
int (*s_ctrl)(
void *img_src,
int id,
int val);
int (*s_ext_ctrls)(
void *img_src,
struct cif_isp10_img_src_ext_ctrl *ctrl);
long (*ioctl)(
void *img_src,
unsigned int cmd,
void *arg);
int (*s_frame_interval)(
void *img_src,
struct cif_isp10_frm_intrvl *frm_intrvl);
int (*g_frame_interval)(
void *img_src,
struct cif_isp10_frm_intrvl *frm_intrvl);
int (*enum_frame_size)(
void *img_src,
void *fse);
};
const struct {
const char *device_type;
struct cif_isp10_img_src_ops ops;
} cif_isp10_img_src_ops[] = {
{
.device_type = CIF_ISP10_IMG_SRC_V4L2_I2C_SUBDEV,
.ops = {
.to_img_src =
cif_isp10_img_src_v4l2_i2c_subdev_to_img_src,
.s_streaming =
cif_isp10_img_src_v4l2_subdev_s_streaming,
.s_power =
cif_isp10_img_src_v4l2_subdev_s_power,
.enum_strm_fmts =
cif_isp10_img_src_v4l2_subdev_enum_strm_fmts,
.s_strm_fmt =
cif_isp10_img_src_v4l2_subdev_s_strm_fmt,
.g_ctrl =
cif_isp10_img_src_v4l2_subdev_g_ctrl,
.g_name =
cif_isp10_img_src_v4l2_subdev_g_name,
.s_ctrl =
cif_isp10_img_src_v4l2_subdev_s_ctrl,
.s_ext_ctrls =
cif_isp10_img_src_v4l2_subdev_s_ext_ctrls,
.ioctl =
cif_isp10_img_src_v4l2_subdev_ioctl,
.s_frame_interval =
cif_isp10_img_src_v4l2_subdev_s_frame_interval,
.g_frame_interval =
cif_isp10_img_src_v4l2_subdev_g_frame_interval,
.enum_frame_size =
cif_isp10_img_src_v4l2_subdev_enum_frame_size,
}
},
};
#endif

558
drivers/media/platform/rk-isp10/cif_isp10_img_src_v4l2-subdev.c
View File

@ -1,558 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include "cif_isp10.h"
#include <linux/platform_data/rk_isp10_platform.h>
#include <media/v4l2-controls_rockchip.h>
#include <linux/slab.h>
/* ===================== */
/* Image Source */
/* ===================== */
void *cif_isp10_img_src_v4l2_i2c_subdev_to_img_src(
struct device *dev,
struct pltfrm_soc_cfg *soc_cfg)
{
int ret = 0;
struct i2c_client *client;
struct v4l2_subdev *subdev;
client = i2c_verify_client(dev);
if (IS_ERR_OR_NULL(client)) {
cif_isp10_pltfrm_pr_err(dev,
"not an I2C device\n");
ret = -EINVAL;
goto err;
}
subdev = i2c_get_clientdata(client);
if (IS_ERR_OR_NULL(subdev))
return subdev;
ret = v4l2_subdev_call(subdev,
core,
ioctl,
PLTFRM_CIFCAM_ATTACH,
(void *)soc_cfg);
if (ret != 0)
goto err;
return (void *)subdev;
err:
cif_isp10_pltfrm_pr_err(NULL, "failed with error %d\n", ret);
return ERR_PTR(ret);
}
static enum cif_isp10_pix_fmt img_src_v4l2_subdev_pix_fmt2cif_isp10_pix_fmt(
int img_src_pix_fmt)
{
switch (img_src_pix_fmt) {
case MEDIA_BUS_FMT_Y8_1X8:
return CIF_YUV400;
case MEDIA_BUS_FMT_Y10_1X10:
return CIF_Y10;
case MEDIA_BUS_FMT_Y12_1X12:
return CIF_Y12;
case MEDIA_BUS_FMT_YUYV8_1_5X8:
case MEDIA_BUS_FMT_YUYV8_2X8:
case MEDIA_BUS_FMT_YUYV10_2X10:
case MEDIA_BUS_FMT_YUYV8_1X16:
case MEDIA_BUS_FMT_YUYV10_1X20:
return CIF_YUV422I;
case MEDIA_BUS_FMT_YVYU8_1_5X8:
case MEDIA_BUS_FMT_YVYU8_2X8:
case MEDIA_BUS_FMT_YVYU10_2X10:
case MEDIA_BUS_FMT_YVYU8_1X16:
case MEDIA_BUS_FMT_YVYU10_1X20:
return CIF_YVU422I;
case MEDIA_BUS_FMT_UYVY8_1_5X8:
case MEDIA_BUS_FMT_UYVY8_2X8:
case MEDIA_BUS_FMT_UYVY8_1X16:
return CIF_UYV422I;
case MEDIA_BUS_FMT_RGB565_2X8_BE:
case MEDIA_BUS_FMT_RGB565_2X8_LE:
return CIF_RGB565;
case MEDIA_BUS_FMT_RGB666_1X18:
return CIF_RGB666;
case MEDIA_BUS_FMT_RGB888_1X24:
case MEDIA_BUS_FMT_RGB888_2X12_BE:
case MEDIA_BUS_FMT_RGB888_2X12_LE:
return CIF_RGB888;
case MEDIA_BUS_FMT_SBGGR8_1X8:
return CIF_BAYER_SBGGR8;
case MEDIA_BUS_FMT_SGBRG8_1X8:
return CIF_BAYER_SGBRG8;
case MEDIA_BUS_FMT_SGRBG8_1X8:
return CIF_BAYER_SGRBG8;
case MEDIA_BUS_FMT_SRGGB8_1X8:
return CIF_BAYER_SRGGB8;
case MEDIA_BUS_FMT_SBGGR10_ALAW8_1X8:
case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
case MEDIA_BUS_FMT_SBGGR10_1X10:
return CIF_BAYER_SBGGR10;
case MEDIA_BUS_FMT_SGBRG10_ALAW8_1X8:
case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
case MEDIA_BUS_FMT_SGBRG10_1X10:
return CIF_BAYER_SGBRG10;
case MEDIA_BUS_FMT_SGRBG10_ALAW8_1X8:
case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
case MEDIA_BUS_FMT_SGRBG10_1X10:
return CIF_BAYER_SGRBG10;
case MEDIA_BUS_FMT_SRGGB10_ALAW8_1X8:
case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
case MEDIA_BUS_FMT_SRGGB10_1X10:
return CIF_BAYER_SRGGB10;
case MEDIA_BUS_FMT_SBGGR12_1X12:
return CIF_BAYER_SBGGR12;
case MEDIA_BUS_FMT_SGBRG12_1X12:
return CIF_BAYER_SGBRG12;
case MEDIA_BUS_FMT_SGRBG12_1X12:
return CIF_BAYER_SGRBG12;
case MEDIA_BUS_FMT_SRGGB12_1X12:
return CIF_BAYER_SRGGB12;
case MEDIA_BUS_FMT_JPEG_1X8:
return CIF_JPEG;
default:
return CIF_UNKNOWN_FORMAT;
}
}
static int cif_isp10_pix_fmt2img_src_v4l2_subdev_pix_fmt(
enum cif_isp10_pix_fmt cif_isp10_pix_fmt)
{
switch (cif_isp10_pix_fmt) {
case CIF_Y10:
return MEDIA_BUS_FMT_Y10_1X10;
case CIF_Y12:
return MEDIA_BUS_FMT_Y12_1X12;
case CIF_YUV400:
return MEDIA_BUS_FMT_Y8_1X8;
case CIF_YUV422I:
return MEDIA_BUS_FMT_YUYV8_2X8;
case CIF_YVU422I:
return MEDIA_BUS_FMT_YVYU8_2X8;
case CIF_UYV422I:
return MEDIA_BUS_FMT_UYVY8_2X8;
case CIF_RGB565:
return MEDIA_BUS_FMT_RGB565_2X8_LE;
case CIF_RGB666:
return MEDIA_BUS_FMT_RGB666_1X18;
case CIF_RGB888:
return MEDIA_BUS_FMT_RGB888_1X24;
case CIF_BAYER_SBGGR8:
return MEDIA_BUS_FMT_SBGGR8_1X8;
case CIF_BAYER_SGBRG8:
return MEDIA_BUS_FMT_SGBRG8_1X8;
case CIF_BAYER_SGRBG8:
return MEDIA_BUS_FMT_SGRBG8_1X8;
case CIF_BAYER_SRGGB8:
return MEDIA_BUS_FMT_SRGGB8_1X8;
case CIF_BAYER_SBGGR10:
return MEDIA_BUS_FMT_SBGGR10_1X10;
case CIF_BAYER_SGBRG10:
return MEDIA_BUS_FMT_SGBRG10_1X10;
case CIF_BAYER_SGRBG10:
return MEDIA_BUS_FMT_SGRBG10_1X10;
case CIF_BAYER_SRGGB10:
return MEDIA_BUS_FMT_SRGGB10_1X10;
case CIF_BAYER_SBGGR12:
return MEDIA_BUS_FMT_SBGGR12_1X12;
case CIF_BAYER_SGBRG12:
return MEDIA_BUS_FMT_SGBRG12_1X12;
case CIF_BAYER_SGRBG12:
return MEDIA_BUS_FMT_SGRBG12_1X12;
case CIF_BAYER_SRGGB12:
return MEDIA_BUS_FMT_SRGGB12_1X12;
case CIF_JPEG:
return MEDIA_BUS_FMT_JPEG_1X8;
default:
return -EINVAL;
}
}
static int cif_isp10_v4l2_cid2v4l2_cid(u32 cif_isp10_cid)
{
switch (cif_isp10_cid) {
case CIF_ISP10_CID_FLASH_MODE:
return V4L2_CID_FLASH_LED_MODE;
case CIF_ISP10_CID_AUTO_GAIN:
return V4L2_CID_AUTOGAIN;
case CIF_ISP10_CID_AUTO_EXPOSURE:
return V4L2_EXPOSURE_AUTO;
case CIF_ISP10_CID_AUTO_WHITE_BALANCE:
return V4L2_CID_AUTO_WHITE_BALANCE;
case CIF_ISP10_CID_BLACK_LEVEL:
return V4L2_CID_BLACK_LEVEL;
case CIF_ISP10_CID_WB_TEMPERATURE:
return V4L2_CID_WHITE_BALANCE_TEMPERATURE;
case CIF_ISP10_CID_EXPOSURE_TIME:
return V4L2_CID_EXPOSURE;
case CIF_ISP10_CID_ANALOG_GAIN:
return V4L2_CID_GAIN;
case CIF_ISP10_CID_FOCUS_ABSOLUTE:
return V4L2_CID_FOCUS_ABSOLUTE;
case CIF_ISP10_CID_AUTO_N_PRESET_WHITE_BALANCE:
return V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE;
case CIF_ISP10_CID_SCENE_MODE:
return V4L2_CID_SCENE_MODE;
case CIF_ISP10_CID_ISO_SENSITIVITY:
return V4L2_CID_ISO_SENSITIVITY;
case CIF_ISP10_CID_AUTO_FPS:
return RK_V4L2_CID_AUTO_FPS;
case CIF_ISP10_CID_VBLANKING:
return RK_V4L2_CID_VBLANKING;
case CIF_ISP10_CID_HFLIP:
return V4L2_CID_HFLIP;
case CIF_ISP10_CID_VFLIP:
return V4L2_CID_VFLIP;
case CIF_ISP10_CID_MIN_BUFFER_FOR_CAPTURE:
return V4L2_CID_MIN_BUFFERS_FOR_CAPTURE;
case CIF_ISP10_CID_TEST_PATTERN:
return V4L2_CID_TEST_PATTERN;
default:
cif_isp10_pltfrm_pr_err(NULL,
"unknown/unsupported CIF ISP20 ID %d\n",
cif_isp10_cid);
break;
}
return -EINVAL;
}
int cif_isp10_img_src_v4l2_subdev_s_streaming(
void *img_src,
bool enable)
{
struct v4l2_subdev *subdev = img_src;
if (enable)
return v4l2_subdev_call(subdev, video, s_stream, 1);
else
return v4l2_subdev_call(subdev, video, s_stream, 0);
}
int cif_isp10_img_src_v4l2_subdev_s_power(
void *img_src,
bool on)
{
struct v4l2_subdev *subdev = img_src;
if (on)
return v4l2_subdev_call(subdev, core, s_power, 1);
else
return v4l2_subdev_call(subdev, core, s_power, 0);
}
int cif_isp10_img_src_v4l2_subdev_enum_strm_fmts(
void *img_src,
u32 index,
struct cif_isp10_strm_fmt_desc *strm_fmt_desc)
{
int ret;
struct v4l2_subdev *subdev = img_src;
struct v4l2_subdev_frame_interval_enum fie = {.index = index};
struct pltfrm_cam_defrect defrect;
v4l2_std_id std;
ret = v4l2_subdev_call(subdev, video, querystd, &std);
if (!IS_ERR_VALUE(ret))
strm_fmt_desc->std_id = std;
else
strm_fmt_desc->std_id = 0;
ret = v4l2_subdev_call(subdev, pad,
enum_frame_interval, NULL, &fie);
if (!IS_ERR_VALUE(ret)) {
strm_fmt_desc->discrete_intrvl = true;
strm_fmt_desc->min_intrvl.numerator =
fie.interval.numerator;
strm_fmt_desc->min_intrvl.denominator =
fie.interval.denominator;
strm_fmt_desc->discrete_frmsize = true;
strm_fmt_desc->min_frmsize.width = fie.width;
strm_fmt_desc->min_frmsize.height = fie.height;
strm_fmt_desc->pix_fmt =
img_src_v4l2_subdev_pix_fmt2cif_isp10_pix_fmt(
fie.code);
defrect.width = fie.width;
defrect.height = fie.height;
memset(&defrect.defrect, 0x00, sizeof(defrect.defrect));
v4l2_subdev_call(subdev,
core,
ioctl,
PLTFRM_CIFCAM_G_DEFRECT,
(void *)&defrect);
if ((defrect.defrect.width == 0) ||
(defrect.defrect.height == 0)) {
strm_fmt_desc->defrect.left = 0;
strm_fmt_desc->defrect.top = 0;
strm_fmt_desc->defrect.width = fie.width;
strm_fmt_desc->defrect.height = fie.height;
} else {
strm_fmt_desc->defrect = defrect.defrect;
}
}
return ret;
}
int cif_isp10_img_src_v4l2_subdev_s_strm_fmt(
void *img_src,
struct cif_isp10_strm_fmt *strm_fmt)
{
int ret = 0;
struct v4l2_subdev *subdev = img_src;
struct v4l2_subdev_format format;
struct v4l2_subdev_frame_interval intrvl;
format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
format.format.code = cif_isp10_pix_fmt2img_src_v4l2_subdev_pix_fmt(
strm_fmt->frm_fmt.pix_fmt);
format.format.width = strm_fmt->frm_fmt.width;
format.format.height = strm_fmt->frm_fmt.height;
ret = v4l2_subdev_call(subdev, pad, set_fmt, NULL, &format);
if (IS_ERR_VALUE(ret))
goto err;
intrvl.interval.numerator = strm_fmt->frm_intrvl.numerator;
intrvl.interval.denominator = strm_fmt->frm_intrvl.denominator;
ret = v4l2_subdev_call(subdev, video, s_frame_interval, &intrvl);
if (IS_ERR_VALUE(ret))
goto err;
return 0;
err:
pr_err("img_src.%s ERR: failed with error %d\n", __func__, ret);
return ret;
}
int cif_isp10_img_src_v4l2_subdev_g_ctrl(
void *img_src,
int id,
int *val)
{
struct v4l2_control ctrl;
int ret;
struct v4l2_subdev *subdev = img_src;
ctrl.id = cif_isp10_v4l2_cid2v4l2_cid(id);
if (IS_ERR_VALUE(ctrl.id))
return (int)ctrl.id;
ret = v4l2_subdev_call(subdev, core, g_ctrl, &ctrl);
if (!IS_ERR_VALUE(ret)) {
if (id == CIF_ISP10_CID_FLASH_MODE) {
if (ctrl.value == V4L2_FLASH_LED_MODE_NONE) {
ctrl.value = CIF_ISP10_FLASH_MODE_OFF;
} else if (ctrl.value == V4L2_FLASH_LED_MODE_FLASH) {
ctrl.value = CIF_ISP10_FLASH_MODE_FLASH;
} else if (ctrl.value == V4L2_FLASH_LED_MODE_TORCH) {
ctrl.value = CIF_ISP10_FLASH_MODE_TORCH;
} else {
cif_isp10_pltfrm_pr_err(NULL,
"unknown/unsupported value %d for control ID 0x%x\n",
ctrl.value, id);
return -EINVAL;
}
}
*val = ctrl.value;
} else {
cif_isp10_pltfrm_pr_err(NULL,
"subdevcall got err: %d\n", ret);
}
return ret;
}
int cif_isp10_img_src_v4l2_subdev_s_ctrl(
void *img_src,
int id,
int val)
{
struct v4l2_control ctrl;
struct v4l2_subdev *subdev = img_src;
ctrl.value = val;
ctrl.id = cif_isp10_v4l2_cid2v4l2_cid(id);
if (IS_ERR_VALUE(ctrl.id)) {
return (int)ctrl.id;
} else if (id == CIF_ISP10_CID_FLASH_MODE) {
if (val == CIF_ISP10_FLASH_MODE_OFF) {
ctrl.value = V4L2_FLASH_LED_MODE_NONE;
} else if (val == CIF_ISP10_FLASH_MODE_FLASH) {
ctrl.value = V4L2_FLASH_LED_MODE_FLASH;
} else if (val == CIF_ISP10_FLASH_MODE_TORCH) {
ctrl.value = V4L2_FLASH_LED_MODE_TORCH;
} else {
cif_isp10_pltfrm_pr_err(NULL,
"unknown/unsupported value %d for control ID %d\n",
val, id);
return -EINVAL;
}
}
return v4l2_subdev_call(subdev, core, s_ctrl, &ctrl);
}
const char *cif_isp10_img_src_v4l2_subdev_g_name(
void *img_src)
{
struct v4l2_subdev *subdev = img_src;
return dev_driver_string(subdev->dev);
}
int cif_isp10_img_src_v4l2_subdev_s_ext_ctrls(
void *img_src,
struct cif_isp10_img_src_ext_ctrl *ctrl)
{
struct v4l2_ext_controls ctrls;
struct v4l2_ext_control *controls;
int i;
int ret;
struct v4l2_subdev *subdev = img_src;
if (ctrl->cnt == 0)
return -EINVAL;
controls = kmalloc_array(ctrl->cnt, sizeof(struct v4l2_ext_control),
GFP_KERNEL);
if (!controls)
return -ENOMEM;
for (i = 0; i < ctrl->cnt; i++) {
controls[i].id = ctrl->ctrls[i].id;
controls[i].value = ctrl->ctrls[i].val;
}
ctrls.count = ctrl->cnt;
ctrls.controls = controls;
/*
* current kernel version don't define
* this member for struct v4l2_ext_control.
*/
/* ctrls.ctrl_class = ctrl->class; */
ctrls.reserved[0] = 0;
ctrls.reserved[1] = 0;
ret = v4l2_subdev_call(subdev,
core, s_ext_ctrls, &ctrls);
kfree(controls);
return ret;
}
long cif_isp10_img_src_v4l2_subdev_ioctl(
void *img_src,
unsigned int cmd,
void *arg)
{
struct v4l2_subdev *subdev = img_src;
long ret = -EINVAL;
switch (cmd) {
case RK_VIDIOC_SENSOR_MODE_DATA:
case RK_VIDIOC_CAMERA_MODULEINFO:
case RK_VIDIOC_SENSOR_CONFIGINFO:
case RK_VIDIOC_SENSOR_REG_ACCESS:
case PLTFRM_CIFCAM_G_ITF_CFG:
case PLTFRM_CIFCAM_G_DEFRECT:
case PLTFRM_CIFCAM_ATTACH:
case PLTFRM_CIFCAM_SET_VCM_POS:
case PLTFRM_CIFCAM_GET_VCM_POS:
case PLTFRM_CIFCAM_GET_VCM_MOVE_RES:
ret = v4l2_subdev_call(subdev,
core,
ioctl,
cmd,
arg);
break;
default:
break;
}
if (IS_ERR_VALUE(ret) && cmd != PLTFRM_CIFCAM_GET_VCM_MOVE_RES)
pr_err("img_src.%s subdev call(cmd: 0x%x) failed with error %ld\n",
__func__, cmd, ret);
return ret;
}
int cif_isp10_img_src_v4l2_subdev_s_frame_interval(
void *img_src,
struct cif_isp10_frm_intrvl *frm_intrvl)
{
int ret = 0;
struct v4l2_subdev *subdev = img_src;
struct v4l2_subdev_frame_interval interval;
interval.interval.numerator = frm_intrvl->numerator;
interval.interval.denominator = frm_intrvl->denominator;
ret = v4l2_subdev_call(subdev, video, s_frame_interval, &interval);
if (IS_ERR_VALUE(ret))
goto err;
return 0;
err:
pr_err("img_src.%s ERR: failed with error %d\n", __func__, ret);
return ret;
}
int cif_isp10_img_src_v4l2_subdev_g_frame_interval(
void *img_src,
struct cif_isp10_frm_intrvl *frm_intrvl)
{
int ret = 0;
struct v4l2_subdev *subdev = img_src;
struct v4l2_subdev_frame_interval interval;
interval.interval.numerator = 0;
interval.interval.denominator = 0;
ret = v4l2_subdev_call(subdev, video, g_frame_interval, &interval);
if (IS_ERR_VALUE(ret))
goto err;
frm_intrvl->denominator = interval.interval.denominator;
frm_intrvl->numerator = interval.interval.numerator;
return 0;
err:
pr_err("img_src.%s ERR: failed with error %d\n", __func__, ret);
return ret;
}
int cif_isp10_img_src_v4l2_subdev_enum_frame_size(
void *img_src,
struct v4l2_subdev_frame_size_enum *fse)
{
struct v4l2_subdev *subdev = img_src;
return v4l2_subdev_call(subdev, pad,
enum_frame_size, NULL, fse);
}

77
drivers/media/platform/rk-isp10/cif_isp10_img_src_v4l2-subdev.h
View File

@ -1,77 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#ifndef _CIF_ISP10_IMG_SRC_V4L2_SUBDEV_H
#define _CIF_ISP10_IMG_SRC_V4L2_SUBDEV_H
#define CIF_ISP10_IMG_SRC_V4L2_I2C_SUBDEV "v4l2-i2c-subdev"
void *cif_isp10_img_src_v4l2_i2c_subdev_to_img_src(
struct device *dev,
struct pltfrm_soc_cfg *soc_cfg);
int cif_isp10_img_src_v4l2_subdev_s_streaming(
void *img_src,
bool enable);
int cif_isp10_img_src_v4l2_subdev_s_power(
void *img_src,
bool on);
int cif_isp10_img_src_v4l2_subdev_enum_strm_fmts(
void *img_src,
u32 index,
struct cif_isp10_strm_fmt_desc *strm_fmt_desc);
int cif_isp10_img_src_v4l2_subdev_s_strm_fmt(
void *img_src,
struct cif_isp10_strm_fmt *strm_fmt);
int cif_isp10_img_src_v4l2_subdev_g_ctrl(
void *img_src,
int id,
int *val);
int cif_isp10_img_src_v4l2_subdev_s_ctrl(
void *img_src,
int id,
int val);
const char *cif_isp10_img_src_v4l2_subdev_g_name(
void *img_src);
int cif_isp10_img_src_v4l2_subdev_s_ext_ctrls(
void *img_src,
struct cif_isp10_img_src_ext_ctrl *ctrl);
long cif_isp10_img_src_v4l2_subdev_ioctl(
void *img_src,
unsigned int cmd,
void *arg);
int cif_isp10_img_src_v4l2_subdev_s_frame_interval(
void *img_src,
struct cif_isp10_frm_intrvl *frm_intrvl);
int cif_isp10_img_src_v4l2_subdev_g_frame_interval(
void *img_src,
struct cif_isp10_frm_intrvl *frm_intrvl);
int cif_isp10_img_src_v4l2_subdev_enum_frame_size(
void *img_src,
void *fse);
#endif

5252
drivers/media/platform/rk-isp10/cif_isp10_isp.c
View File

File diff suppressed because it is too large Load Diff

166
drivers/media/platform/rk-isp10/cif_isp10_isp.h
View File

@ -1,166 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#ifndef _CIF_ISP10_ISP_H
#define _CIF_ISP10_ISP_H
#include <media/v4l2-common.h>
#include <media/videobuf2-core.h>
#include <media/rk-isp10-ioctl.h>
#include <media/v4l2-controls_rockchip.h>
/*
* ISP device struct
*/
#define CIF_ISP10_META_INFO_NUM 2
enum cif_isp10_pix_fmt;
enum cif_isp10_pix_fmt_quantization {
CIF_ISP10_QUANTIZATION_DEFAULT = 0,
CIF_ISP10_QUANTIZATION_FULL_RANGE = 1,
CIF_ISP10_QUANTIZATION_LIM_RANGE = 2
};
struct cif_isp10_isp_meta_info {
unsigned int write_id;
unsigned int read_id;
unsigned int read_cnt;
unsigned int read_max;
unsigned int frame_id[CIF_ISP10_META_INFO_NUM];
struct timeval vs_t[CIF_ISP10_META_INFO_NUM];
struct timeval fi_t[CIF_ISP10_META_INFO_NUM];
};
struct cif_isp10_isp_cfgs_log {
unsigned int s_frame_id[3];
unsigned int new_id;
unsigned int curr_id;
};
struct cif_isp10_isp_other_cfgs {
struct cif_isp10_isp_cfgs_log log[CIFISP_MODULE_MAX];
struct cifisp_isp_other_cfg cfgs[3];
unsigned int module_updates;
unsigned int module_actives;
};
struct cif_isp10_isp_meas_cfgs {
struct cif_isp10_isp_cfgs_log log[CIFISP_MODULE_MAX];
struct cifisp_isp_meas_cfg cfgs[3];
unsigned int module_updates;
unsigned int module_actives;
};
struct cif_isp10_isp_meas_stats {
unsigned int g_frame_id;
struct cifisp_stat_buffer stat;
};
struct cif_isp10_isp_dev {
/*
* Purpose of mutex is to protect and serialize use
* of isp data structure and CIF API calls.
*/
struct mutex mutex;
/* Current ISP parameters */
spinlock_t config_lock;
struct cif_isp10_isp_other_cfgs other_cfgs;
struct cif_isp10_isp_meas_cfgs meas_cfgs;
struct cif_isp10_isp_meas_stats meas_stats;
bool cif_ism_cropping;
enum cif_isp10_pix_fmt_quantization quantization;
/* input resolution needed for LSC param check */
unsigned int input_width;
unsigned int input_height;
unsigned int active_lsc_width;
unsigned int active_lsc_height;
/* ISP statistics related */
spinlock_t irq_lock;
/* ISP statistics related */
spinlock_t req_lock;
struct list_head stat;
void __iomem *base_addr; /* registers base address */
bool streamon;
unsigned int v_blanking_us;
unsigned int frame_id;
unsigned int frame_id_setexp;
unsigned int active_meas;
unsigned int meas_send_alone;
bool awb_meas_ready;
bool afm_meas_ready;
bool aec_meas_ready;
bool hst_meas_ready;
struct timeval vs_t; /* updated each frame */
struct timeval fi_t; /* updated each frame */
struct workqueue_struct *readout_wq;
struct cif_isp10_isp_meta_info meta_info;
unsigned int *dev_id;
struct vb2_queue vb2_vidq;
};
enum cif_isp10_isp_readout_cmd {
CIF_ISP10_ISP_READOUT_MEAS = 0,
CIF_ISP10_ISP_READOUT_META = 1,
};
struct cif_isp10_isp_readout_work {
struct work_struct work;
struct cif_isp10_isp_dev *isp_dev;
unsigned int frame_id;
unsigned int active_meas;
struct timeval vs_t;
struct timeval fi_t;
enum cif_isp10_isp_readout_cmd readout;
struct vb2_buffer *vb;
unsigned int stream_id;
struct cifisp_isp_metadata *isp_metadata;
};
int register_cifisp_device(
struct cif_isp10_isp_dev *isp_dev,
struct video_device *vdev_cifisp,
struct v4l2_device *v4l2_dev,
void __iomem *cif_reg_baseaddress);
void unregister_cifisp_device(struct video_device *vdev_cifisp);
void cifisp_configure_isp(
struct cif_isp10_isp_dev *isp_dev,
enum cif_isp10_pix_fmt in_pix_fmt,
enum cif_isp10_pix_fmt_quantization quantization);
void cifisp_disable_isp(struct cif_isp10_isp_dev *isp_dev);
int cifisp_isp_isr(struct cif_isp10_isp_dev *isp_dev, u32 isp_mis);
void cifisp_clr_readout_wq(struct cif_isp10_isp_dev *isp_dev);
void cifisp_v_start(struct cif_isp10_isp_dev *isp_dev,
const struct timeval *timestamp);
void cifisp_frame_in(
struct cif_isp10_isp_dev *isp_dev,
const struct timeval *fi_t);
void cifisp_frame_id_reset(
struct cif_isp10_isp_dev *isp_dev);
void cifisp_isp_readout_work(struct work_struct *work);
#endif

1382
drivers/media/platform/rk-isp10/cif_isp10_pltfrm.c
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drivers/media/platform/rk-isp10/cif_isp10_pltfrm.h
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@ -1,207 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#ifndef _CIF_ISP10_PLTFRM_H
#define _CIF_ISP10_PLTFRM_H
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/wait.h>
#include <linux/string.h>
#include <linux/platform_data/rk_isp10_platform.h>
struct cif_isp10_strm_fmt;
struct cif_isp10_csi_config;
struct cif_isp10_device;
struct cif_isp10_img_src;
struct pltfrm_cam_itf;
enum cif_isp10_pinctrl_state;
enum cif_isp10_inp;
enum cif_isp10_pm_state;
#define CIF_ISP10_PLTFRM_DEVICE struct device *
#define CIF_ISP10_PLTFRM_MEM_IO_ADDR void __iomem *
#define CIF_ISP10_PLTFRM_EVENT wait_queue_head_t
#ifdef CONFIG_CIF_ISP10_REG_TRACE
int
cif_isp10_pltfrm_rtrace_printf(
struct device *dev,
const char *fmt,
...);
int
cif_isp10_pltfrm_ftrace_printf(
struct device *dev,
const char *fmt,
...);
#else
#define cif_isp10_pltfrm_rtrace_printf(dev, str, ...)
#define cif_isp10_pltfrm_ftrace_printf(dev, str, ...)
#endif
#define cif_isp10_pltfrm_pr_dbg(dev, fmt, arg...) \
do { \
pr_debug("%s: " fmt, \
__func__, ## arg); \
cif_isp10_pltfrm_ftrace_printf(dev, "%s: " fmt, \
__func__, ## arg); \
} while (0)
#define cif_isp10_pltfrm_pr_info(dev, fmt, arg...) \
do { \
pr_info("%s: " fmt, \
__func__, ## arg); \
cif_isp10_pltfrm_ftrace_printf(dev, "%s: " fmt, \
__func__, ## arg); \
} while (0)
#define cif_isp10_pltfrm_pr_warn(dev, fmt, arg...) \
do { \
pr_warn("%s WARN: " fmt, \
__func__, ## arg); \
cif_isp10_pltfrm_ftrace_printf(dev, "%s WARN: " fmt, \
__func__, ## arg); \
} while (0)
#define cif_isp10_pltfrm_pr_err(dev, fmt, arg...) \
do { \
pr_err("%s(%d) ERR: " fmt, \
__func__, __LINE__, ## arg); \
cif_isp10_pltfrm_ftrace_printf(dev, "%s(%d) ERR: " fmt, \
__func__, __LINE__, ## arg); \
} while (0)
void cif_isp10_pltfrm_write_reg(
struct device *dev,
u32 data,
CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
void cif_isp10_pltfrm_write_reg_OR(
struct device *dev,
u32 data,
CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
void cif_isp10_pltfrm_write_reg_AND(
struct device *dev,
u32 data,
CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
u32 cif_isp10_pltfrm_read_reg(
struct device *dev,
CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
#define cif_iowrite32(d, a) \
cif_isp10_pltfrm_write_reg(NULL, (u32)(d), a)
#define cif_ioread32(a) \
cif_isp10_pltfrm_read_reg(NULL, a)
#define cif_iowrite32OR(d, a) \
cif_isp10_pltfrm_write_reg_OR(NULL, (u32)(d), a)
#define cif_iowrite32AND(d, a) \
cif_isp10_pltfrm_write_reg_AND(NULL, (u32)(d), a)
/* BUG: Register write seems to fail sometimes w/o read before write. */
#define cif_iowrite32_verify(d, a, mask) \
{ \
unsigned int i = 0; \
unsigned long flags = 0; \
spin_lock_irqsave(&dev->iowrite32_verify_lock, flags); \
do { \
cif_iowrite32(d, a); \
udelay(1); \
if (i++ == 50) { \
pr_err("Error in writing %x@0x%p, read %x\n", \
(d) & (mask), a, ioread32(a)); \
WARN_ON(1); \
} \
} while ((ioread32(a) & mask) != ((d) & mask)); \
spin_unlock_irqrestore(&dev->iowrite32_verify_lock, flags);\
}
#define cif_iowrite32OR_verify(d, a, mask) \
cif_iowrite32_verify((u32)(d) | cif_ioread32(a), a, mask)
#define cif_iowrite32AND_verify(d, a, mask) \
cif_iowrite32_verify((u32)(d) & cif_ioread32(a), a, mask)
#define cif_isp10_pltfrm_event_init(_dev, _event) \
init_waitqueue_head(_event)
#define cif_isp10_pltfrm_event_clear(_dev, _event)
#define cif_isp10_pltfrm_event_signal(_dev, _event) \
wake_up_interruptible(_event)
#define cif_isp10_pltfrm_event_wait_timeout( \
_dev, _event, _condition, _timeout_us) \
wait_event_interruptible_timeout( \
*(_event), _condition, ((_timeout_us) * HZ) / 1000000)
void
cif_isp10_pltfrm_debug_register_print_cb(
struct device *dev,
void (*print)(void *cntxt, const char *block_name),
void *cntxt);
int cif_isp10_pltfrm_dev_init(
struct cif_isp10_device *cif_isp_dev,
struct device **dev,
void __iomem **reg_base_addr);
void cif_isp10_pltfrm_dev_release(
struct device *dev,
struct cif_isp10_device *cif_isp10_dev);
int cif_isp10_pltfrm_pm_set_state(
struct device *dev,
enum cif_isp10_pm_state state);
int cif_isp10_pltfrm_write_cif_ana_bandgap_bias(
struct device *dev,
u32 val);
int cif_isp10_pltfrm_pinctrl_set_state(
struct device *dev,
enum cif_isp10_pinctrl_state pinctrl_state);
int cif_isp10_pltfrm_get_img_src_device(
struct device *dev,
struct cif_isp10_img_src **img_src_array,
unsigned int array_len);
int cif_isp10_pltfrm_g_interface_config(
struct cif_isp10_img_src *img_src,
struct pltfrm_cam_itf *cam_itf);
int cif_isp10_pltfrm_irq_register_isr(
struct device *dev,
unsigned int mis,
int (*isr)(unsigned int mis, void *cntxt),
void *cntxt);
const char *cif_isp10_pltfrm_get_device_type(
struct device *dev);
const char *cif_isp10_pltfrm_dev_string(
struct device *dev);
int cif_isp10_pltfrm_soc_init(
struct cif_isp10_device *cif_isp10_dev,
struct pltfrm_soc_cfg *soc_cfg);
int cif_isp10_pltfrm_mipi_dphy_config(
struct cif_isp10_device *cif_isp10_dev);
int cif_isp10_pltfrm_reset(
struct cif_isp10_device *cif_isp10_dev);
#endif

1208
drivers/media/platform/rk-isp10/cif_isp10_regs.h
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drivers/media/platform/rk-isp10/cif_isp10_rk3288.c
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/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/platform_data/rk_isp10_platform.h>
#define ONE_LANE_ENABLE_BIT 0x1
#define TWO_LANE_ENABLE_BIT 0x2
#define FOUR_LANE_ENABLE_BIT 0x4
#define MRV_MIPI_BASE 0x1C00
#define MRV_MIPI_CTRL 0x00
/*
* GRF_SOC_CON14
* bit 0 dphy_rx0_testclr
* bit 1 dphy_rx0_testclk
* bit 2 dphy_rx0_testen
* bit 3:10 dphy_rx0_testdin
*/
#define GRF_SOC_CON14_OFFSET (0x027c)
#define DPHY_RX0_TESTCLR_MASK (0x1 << 16)
#define DPHY_RX0_TESTCLK_MASK (0x1 << 17)
#define DPHY_RX0_TESTEN_MASK (0x1 << 18)
#define DPHY_RX0_TESTDIN_MASK (0xff << 19)
#define DPHY_RX0_TESTCLR BIT(0)
#define DPHY_RX0_TESTCLK BIT(1)
#define DPHY_RX0_TESTEN BIT(2)
#define DPHY_RX0_TESTDIN_OFFSET (3)
#define DPHY_TX1RX1_ENABLECLK_MASK (0x1 << 28)
#define DPHY_RX1_SRC_SEL_MASK (0x1 << 29)
#define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1 << 30)
#define DPHY_TX1RX1_BASEDIR_OFFSET (0x1 << 31)
#define DPHY_TX1RX1_ENABLECLK (0x1 << 12)
#define DPHY_TX1RX1_DISABLECLK (0x0 << 12)
#define DPHY_RX1_SRC_SEL_ISP (0x1 << 13)
#define DPHY_TX1RX1_SLAVEZ (0x0 << 14)
#define DPHY_TX1RX1_BASEDIR_REC (0x1 << 15)
/*
* GRF_SOC_CON6
* bit 0 grf_con_disable_isp
* bit 1 grf_con_isp_dphy_sel 1'b0 mipi phy rx0
*/
#define GRF_SOC_CON6_OFFSET (0x025c)
#define MIPI_PHY_DISABLE_ISP_MASK (0x1 << 16)
#define MIPI_PHY_DISABLE_ISP (0x0 << 0)
#define DSI_CSI_TESTBUS_SEL_MASK (0x1 << 30)
#define DSI_CSI_TESTBUS_SEL_OFFSET_BIT (14)
#define MIPI_PHY_DPHYSEL_OFFSET_MASK (0x1 << 17)
#define MIPI_PHY_DPHYSEL_OFFSET_BIT (0x1)
/*
* GRF_SOC_CON10
* bit12:15 grf_dphy_rx0_enable
* bit 0:3 turn disable
*/
#define GRF_SOC_CON10_OFFSET (0x026c)
#define DPHY_RX0_TURN_DISABLE_MASK (0xf << 16)
#define DPHY_RX0_TURN_DISABLE_OFFSET_BITS (0x0)
#define DPHY_RX0_ENABLE_MASK (0xf << 28)
#define DPHY_RX0_ENABLE_OFFSET_BITS (12)
/*
* GRF_SOC_CON9
* bit12:15 grf_dphy_rx0_enable
* bit 0:3 turn disable
*/
#define GRF_SOC_CON9_OFFSET (0x0268)
#define DPHY_TX1RX1_TURN_DISABLE_MASK (0xf << 16)
#define DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS (0x0)
#define DPHY_TX1RX1_ENABLE_MASK (0xf << 28)
#define DPHY_TX1RX1_ENABLE_OFFSET_BITS (12)
/*
* GRF_SOC_CON15
* bit 0:3 turn request
*/
#define GRF_SOC_CON15_OFFSET (0x03a4)
#define DPHY_RX0_TURN_REQUEST_MASK (0xf << 16)
#define DPHY_RX0_TURN_REQUEST_OFFSET_BITS (0x0)
#define DPHY_TX1RX1_TURN_REQUEST_MASK (0xf << 20)
#define DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS (0x0)
/*
* GRF_SOC_STATUS21
* bit0:7 dphy_rx0_testdout
*/
#define GRF_SOC_STATUS21_OFFSET (0x2D4)
#define DPHY_RX0_TESTDOUT(a) ((a) & 0xff)
/*
* GRF_IO_VSEL
*/
#define GRF_IO_VSEL_OFFSET (0x0380)
#define DVP_V18SEL ((1 << 1) | (1 << 17))
#define DVP_V33SEL ((0 << 1) | (1 << 17))
/*
* GRF_IO_VSEL
*/
#define GRF_GPIO2B_E_OFFSET (0x0380)
#define CIF_CLKOUT_STRENGTH(a) ((((a) & 0x03) << 3) | (0x03 << 19))
/*
* CSI HOST
*/
#define CSIHOST_PHY_TEST_CTRL0 (0x30)
#define CSIHOST_PHY_TEST_CTRL1 (0x34)
#define CSIHOST_PHY_SHUTDOWNZ (0x08)
#define CSIHOST_DPHY_RSTZ (0x0c)
#define CSIHOST_N_LANES (0x04)
#define CSIHOST_CSI2_RESETN (0x10)
#define CSIHOST_PHY_STATE (0x14)
#define CSIHOST_DATA_IDS1 (0x18)
#define CSIHOST_DATA_IDS2 (0x1C)
#define CSIHOST_ERR1 (0x20)
#define CSIHOST_ERR2 (0x24)
#define write_cifisp_reg(addr, val) \
__raw_writel(val, (addr) + rk3288->isp_base)
#define read_cifisp_reg(addr) \
__raw_readl((addr) + rk3288->isp_base)
#define write_grf_reg(addr, val) \
regmap_write(rk3288->regmap_grf, addr, val)
#define read_grf_reg(addr, val) regmap_read(rk3288->regmap_grf, addr, val)
#define write_csihost_reg(addr, val) \
__raw_writel(val, (addr) + rk3288->csihost_base)
#define read_csihost_reg(addr) __raw_readl((addr) + rk3288->csihost_base)
struct cif_isp10_clk_rst_rk3288 {
struct clk *aclk_isp;
struct clk *hclk_isp;
struct clk *sclk_isp;
struct clk *sclk_isp_jpe;
struct clk *sclk_mipidsi_24m;
struct clk *pclk_mipi_csi;
struct clk *pclk_isp_in;
struct reset_control *isp_rst;
};
struct cif_isp10_rk3288 {
struct regmap *regmap_grf;
void __iomem *csihost_base;
void __iomem *isp_base;
struct cif_isp10_clk_rst_rk3288 clk_rst;
struct cif_isp10_device *cif_isp10;
};
struct mipi_dphy_hsfreqrange {
unsigned int range_l;
unsigned int range_h;
unsigned char cfg_bit;
};
static struct mipi_dphy_hsfreqrange mipi_dphy_hsfreq_range[] = {
{80, 90, 0x00},
{90, 100, 0x10},
{100, 110, 0x20},
{110, 130, 0x01},
{130, 140, 0x11},
{140, 150, 0x21},
{150, 170, 0x02},
{170, 180, 0x12},
{180, 200, 0x22},
{200, 220, 0x03},
{220, 240, 0x13},
{240, 250, 0x23},
{250, 270, 0x4},
{270, 300, 0x14},
{300, 330, 0x5},
{330, 360, 0x15},
{360, 400, 0x25},
{400, 450, 0x06},
{450, 500, 0x16},
{500, 550, 0x07},
{550, 600, 0x17},
{600, 650, 0x08},
{650, 700, 0x18},
{700, 750, 0x09},
{750, 800, 0x19},
{800, 850, 0x29},
{850, 900, 0x39},
{900, 950, 0x0a},
{950, 1000, 0x1a}
};
static struct cif_isp10_rk3288 *rk3288;
static int mipi_dphy0_wr_reg(unsigned char addr, unsigned char data)
{
/*
* TESTCLK=1
* TESTEN =1,TESTDIN=addr
* TESTCLK=0
*/
write_grf_reg(GRF_SOC_CON14_OFFSET,
DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
write_grf_reg(GRF_SOC_CON14_OFFSET,
((addr << DPHY_RX0_TESTDIN_OFFSET) | DPHY_RX0_TESTDIN_MASK
| DPHY_RX0_TESTEN | DPHY_RX0_TESTEN_MASK));
write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK);
/*
* write data:
* TESTEN =0,TESTDIN=data
* TESTCLK=1
*/
if (data != 0xff) {
write_grf_reg(GRF_SOC_CON14_OFFSET,
((data << DPHY_RX0_TESTDIN_OFFSET) |
DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN_MASK));
write_grf_reg(GRF_SOC_CON14_OFFSET,
DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
}
return 0;
}
static int mipi_dphy1_wr_reg(unsigned char addr, unsigned char data)
{
/*
* TESTEN =1,TESTDIN=addr
* TESTCLK=0
* TESTEN =0,TESTDIN=data
* TESTCLK=1
*/
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000000);
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
return 0;
}
static int mipi_dphy1_rd_reg(unsigned char addr)
{
return (read_csihost_reg(((CSIHOST_PHY_TEST_CTRL1) & 0xff00)) >> 8);
}
static int mipi_dphy_cfg(struct pltfrm_cam_mipi_config *para)
{
unsigned char hsfreqrange = 0xff, i;
struct mipi_dphy_hsfreqrange *hsfreqrange_p;
unsigned char datalane_en, input_sel;
hsfreqrange_p = mipi_dphy_hsfreq_range;
for (i = 0;
i < (sizeof(mipi_dphy_hsfreq_range) /
sizeof(struct mipi_dphy_hsfreqrange));
i++) {
if ((para->bit_rate > hsfreqrange_p->range_l) &&
(para->bit_rate <= hsfreqrange_p->range_h)) {
hsfreqrange = hsfreqrange_p->cfg_bit;
break;
}
hsfreqrange_p++;
}
if (hsfreqrange == 0xff)
hsfreqrange = 0x00;
hsfreqrange <<= 1;
input_sel = para->dphy_index;
datalane_en = 0;
for (i = 0; i < para->nb_lanes; i++)
datalane_en |= (1 << i);
if (input_sel == 0) {
write_grf_reg(GRF_SOC_CON6_OFFSET,
MIPI_PHY_DPHYSEL_OFFSET_MASK |
(input_sel << MIPI_PHY_DPHYSEL_OFFSET_BIT));
/* set lane num */
write_grf_reg(GRF_SOC_CON10_OFFSET,
DPHY_RX0_ENABLE_MASK |
(datalane_en << DPHY_RX0_ENABLE_OFFSET_BITS));
/* set lan turndisab as 1 */
write_grf_reg(GRF_SOC_CON10_OFFSET,
DPHY_RX0_TURN_DISABLE_MASK |
(0xf << DPHY_RX0_TURN_DISABLE_OFFSET_BITS));
write_grf_reg(GRF_SOC_CON10_OFFSET,
(0x0 << 4) | (0xf << 20));
/* set lan turnrequest as 0 */
write_grf_reg(GRF_SOC_CON15_OFFSET,
DPHY_RX0_TURN_REQUEST_MASK |
(0x0 << DPHY_RX0_TURN_REQUEST_OFFSET_BITS));
/* phy start */
/*
* TESTCLK=1
* TESTCLR=1
* delay 100us
* TESTCLR=0
*/
write_grf_reg(GRF_SOC_CON14_OFFSET,
DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
write_grf_reg(GRF_SOC_CON14_OFFSET,
DPHY_RX0_TESTCLR_MASK | DPHY_RX0_TESTCLR);
usleep_range(100, 150);
write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK);
usleep_range(100, 150);
/* set clock lane */
mipi_dphy0_wr_reg(0x34, 0x15);
if (datalane_en == ONE_LANE_ENABLE_BIT) {
mipi_dphy0_wr_reg(0x44, hsfreqrange);
} else if (datalane_en == TWO_LANE_ENABLE_BIT) {
mipi_dphy0_wr_reg(0x44, hsfreqrange);
mipi_dphy0_wr_reg(0x54, hsfreqrange);
} else if (datalane_en == FOUR_LANE_ENABLE_BIT) {
mipi_dphy0_wr_reg(0x44, hsfreqrange);
mipi_dphy0_wr_reg(0x54, hsfreqrange);
mipi_dphy0_wr_reg(0x84, hsfreqrange);
mipi_dphy0_wr_reg(0x94, hsfreqrange);
}
/* Normal operation */
/*
* TESTCLK=1
* TESTEN =0
*/
mipi_dphy0_wr_reg(0x0, -1);
write_grf_reg(GRF_SOC_CON14_OFFSET,
DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
write_grf_reg(GRF_SOC_CON14_OFFSET,
(DPHY_RX0_TESTEN_MASK));
write_cifisp_reg((MRV_MIPI_BASE + MRV_MIPI_CTRL),
read_cifisp_reg(MRV_MIPI_BASE + MRV_MIPI_CTRL) |
(0x0f << 8));
} else if (input_sel == 1) {
write_grf_reg(GRF_SOC_CON6_OFFSET,
MIPI_PHY_DPHYSEL_OFFSET_MASK |
(input_sel << MIPI_PHY_DPHYSEL_OFFSET_BIT));
write_grf_reg(GRF_SOC_CON6_OFFSET,
DSI_CSI_TESTBUS_SEL_MASK |
(1 << DSI_CSI_TESTBUS_SEL_OFFSET_BIT));
write_grf_reg(GRF_SOC_CON14_OFFSET,
DPHY_RX1_SRC_SEL_ISP | DPHY_RX1_SRC_SEL_MASK);
write_grf_reg(GRF_SOC_CON14_OFFSET,
DPHY_TX1RX1_SLAVEZ | DPHY_TX1RX1_MASTERSLAVEZ_MASK);
write_grf_reg(GRF_SOC_CON14_OFFSET,
DPHY_TX1RX1_BASEDIR_REC | DPHY_TX1RX1_BASEDIR_OFFSET);
/* set lane num */
write_grf_reg(GRF_SOC_CON9_OFFSET,
DPHY_TX1RX1_ENABLE_MASK |
(datalane_en << DPHY_TX1RX1_ENABLE_OFFSET_BITS));
/* set lan turndisab as 1 */
write_grf_reg(GRF_SOC_CON9_OFFSET,
DPHY_TX1RX1_TURN_DISABLE_MASK |
(0xf << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS));
/* set lan turnrequest as 0 */
write_grf_reg(GRF_SOC_CON15_OFFSET,
DPHY_TX1RX1_TURN_REQUEST_MASK |
(0x0 << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS));
/* phy1 start */
/*
* SHUTDOWNZ=0
* RSTZ=0
* TESTCLK=1
* TESTCLR=1 TESTCLK=1
* TESTCLR=0 TESTCLK=1
*/
write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000000);
write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000);
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000003);
usleep_range(100, 150);
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
usleep_range(100, 150);
/* set clock lane */
mipi_dphy1_wr_reg(0x34, 0x15);
if (datalane_en == ONE_LANE_ENABLE_BIT) {
mipi_dphy1_wr_reg(0x44, hsfreqrange);
} else if (datalane_en == TWO_LANE_ENABLE_BIT) {
mipi_dphy1_wr_reg(0x44, hsfreqrange);
mipi_dphy1_wr_reg(0x54, hsfreqrange);
} else if (datalane_en == FOUR_LANE_ENABLE_BIT) {
mipi_dphy1_wr_reg(0x44, hsfreqrange);
mipi_dphy1_wr_reg(0x54, hsfreqrange);
mipi_dphy1_wr_reg(0x84, hsfreqrange);
mipi_dphy1_wr_reg(0x94, hsfreqrange);
}
mipi_dphy1_rd_reg(0x0);
/*
* TESTCLK=1
* TESTEN =0
* SHUTDOWNZ=1
* RSTZ=1
*/
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, 0x00000000);
write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000001);
write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000001);
} else {
goto fail;
}
return 0;
fail:
return -1;
}
static int soc_clk_enable(void)
{
struct cif_isp10_clk_rst_rk3288 *clk_rst = &rk3288->clk_rst;
clk_prepare_enable(clk_rst->hclk_isp);
clk_prepare_enable(clk_rst->aclk_isp);
clk_prepare_enable(clk_rst->sclk_isp);
clk_prepare_enable(clk_rst->sclk_isp_jpe);
clk_prepare_enable(clk_rst->sclk_mipidsi_24m);
clk_prepare_enable(clk_rst->pclk_isp_in);
clk_prepare_enable(clk_rst->pclk_mipi_csi);
return 0;
}
static int soc_clk_disable(void)
{
struct cif_isp10_clk_rst_rk3288 *clk_rst = &rk3288->clk_rst;
clk_disable_unprepare(clk_rst->hclk_isp);
clk_disable_unprepare(clk_rst->aclk_isp);
clk_disable_unprepare(clk_rst->sclk_isp);
clk_disable_unprepare(clk_rst->sclk_isp_jpe);
clk_disable_unprepare(clk_rst->sclk_mipidsi_24m);
clk_disable_unprepare(clk_rst->pclk_isp_in);
clk_disable_unprepare(clk_rst->pclk_mipi_csi);
return 0;
}
static int soc_init(struct pltfrm_soc_init_para *init)
{
struct cif_isp10_clk_rst_rk3288 *clk_rst;
struct platform_device *pdev = init->pdev;
struct device_node *np = pdev->dev.of_node, *node;
struct resource *res;
int err;
rk3288 = (struct cif_isp10_rk3288 *)devm_kzalloc(
&pdev->dev,
sizeof(struct cif_isp10_rk3288),
GFP_KERNEL);
if (!rk3288) {
dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3288\n");
err = -ENOMEM;
goto alloc_failed;
}
node = of_parse_phandle(np, "rockchip,grf", 0);
if (node) {
rk3288->regmap_grf = syscon_node_to_regmap(node);
if (IS_ERR(rk3288->regmap_grf)) {
dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3288\n");
err = -ENODEV;
goto regmap_failed;
}
}
res = platform_get_resource_byname(pdev,
IORESOURCE_MEM, "csihost-register");
if (!res) {
dev_err(&pdev->dev,
"platform_get_resource_byname csihost-register failed\n");
err = -ENODEV;
goto regmap_failed;
}
rk3288->csihost_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR_OR_NULL(rk3288->csihost_base)) {
dev_err(&pdev->dev, "devm_ioremap_resource failed\n");
if (IS_ERR(rk3288->csihost_base))
err = PTR_ERR(rk3288->csihost_base);
else
err = -ENODEV;
goto regmap_failed;
}
clk_rst = &rk3288->clk_rst;
clk_rst->aclk_isp = devm_clk_get(&pdev->dev, "aclk_isp");
clk_rst->hclk_isp = devm_clk_get(&pdev->dev, "hclk_isp");
clk_rst->sclk_isp = devm_clk_get(&pdev->dev, "sclk_isp");
clk_rst->sclk_isp_jpe = devm_clk_get(&pdev->dev, "sclk_isp_jpe");
clk_rst->sclk_mipidsi_24m =
devm_clk_get(&pdev->dev, "sclk_mipidsi_24m");
clk_rst->pclk_mipi_csi = devm_clk_get(&pdev->dev, "pclk_mipi_csi");
clk_rst->isp_rst = devm_reset_control_get(&pdev->dev, "rst_isp");
clk_rst->pclk_isp_in = devm_clk_get(&pdev->dev, "pclk_isp_in");
if (IS_ERR_OR_NULL(clk_rst->aclk_isp) ||
IS_ERR_OR_NULL(clk_rst->hclk_isp) ||
IS_ERR_OR_NULL(clk_rst->sclk_isp) ||
IS_ERR_OR_NULL(clk_rst->sclk_isp_jpe) ||
IS_ERR_OR_NULL(clk_rst->pclk_mipi_csi) ||
IS_ERR_OR_NULL(clk_rst->isp_rst) ||
IS_ERR_OR_NULL(clk_rst->pclk_isp_in) ||
IS_ERR_OR_NULL(clk_rst->sclk_mipidsi_24m)) {
dev_err(&pdev->dev, "Get rk3288 cif isp10 clock resouce failed !\n");
err = -EINVAL;
goto clk_failed;
}
clk_set_rate(clk_rst->sclk_isp, 400000000);
clk_set_rate(clk_rst->sclk_isp_jpe, 400000000);
reset_control_deassert(clk_rst->isp_rst);
rk3288->isp_base = init->isp_base;
return 0;
clk_failed:
if (!IS_ERR_OR_NULL(clk_rst->aclk_isp))
devm_clk_put(&pdev->dev, clk_rst->aclk_isp);
if (!IS_ERR_OR_NULL(clk_rst->hclk_isp))
devm_clk_put(&pdev->dev, clk_rst->hclk_isp);
if (!IS_ERR_OR_NULL(clk_rst->sclk_isp))
devm_clk_put(&pdev->dev, clk_rst->sclk_isp);
if (!IS_ERR_OR_NULL(clk_rst->sclk_isp_jpe))
devm_clk_put(&pdev->dev, clk_rst->sclk_isp_jpe);
if (!IS_ERR_OR_NULL(clk_rst->pclk_mipi_csi))
devm_clk_put(&pdev->dev, clk_rst->pclk_mipi_csi);
if (!IS_ERR_OR_NULL(clk_rst->pclk_isp_in))
devm_clk_put(&pdev->dev, clk_rst->pclk_isp_in);
if (!IS_ERR_OR_NULL(clk_rst->sclk_mipidsi_24m))
devm_clk_put(&pdev->dev, clk_rst->sclk_mipidsi_24m);
if (!IS_ERR_OR_NULL(clk_rst->isp_rst))
reset_control_put(clk_rst->isp_rst);
regmap_failed:
alloc_failed:
return err;
}
int pltfrm_rk3288_cfg(struct pltfrm_soc_cfg_para *cfg)
{
switch (cfg->cmd) {
case PLTFRM_MCLK_CFG: {
struct pltfrm_soc_mclk_para *mclk_para;
mclk_para = (struct pltfrm_soc_mclk_para *)cfg->cfg_para;
if (mclk_para->io_voltage == PLTFRM_IO_1V8)
write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V18SEL);
else
write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V33SEL);
write_grf_reg(GRF_GPIO2B_E_OFFSET,
CIF_CLKOUT_STRENGTH(mclk_para->drv_strength));
break;
}
case PLTFRM_MIPI_DPHY_CFG:
mipi_dphy_cfg((struct pltfrm_cam_mipi_config *)cfg->cfg_para);
break;
case PLTFRM_CLKEN:
soc_clk_enable();
break;
case PLTFRM_CLKDIS:
soc_clk_disable();
break;
case PLTFRM_CLKRST:
reset_control_assert(rk3288->clk_rst.isp_rst);
usleep_range(10, 15);
reset_control_deassert(rk3288->clk_rst.isp_rst);
break;
case PLTFRM_SOC_INIT:
soc_init((struct pltfrm_soc_init_para *)cfg->cfg_para);
break;
default:
break;
}
return 0;
}

770
drivers/media/platform/rk-isp10/cif_isp10_rk3399.c
View File

@ -1,770 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/platform_data/rk_isp10_platform.h>
#define VI_IRCL 0x0014
#define MRV_MIPI_BASE 0x1C00
#define MRV_MIPI_CTRL 0x00
/*
* GRF_IO_VSEL
*/
#define GRF_IO_VSEL_OFFSET (0x0900)
#define DVP_V18SEL ((1 << 1) | (1 << 17))
#define DVP_V33SEL ((0 << 1) | (1 << 17))
/*
* GRF_IO_VSEL
*/
#define GRF_GPIO2B_E_OFFSET (0x0204)
#define CIF_CLKOUT_STRENGTH(a) \
((((a) & 0x03) << 3) | (0x03 << 19))
#define GRF_SOC_STATUS1 (0x0e2a4)
#define GRF_SOC_CON9_OFFSET (0x6224)
#define DPHY_RX0_TURNREQUEST_MASK (0xF << 16)
#define DPHY_RX0_TURNREQUEST_BIT (0)
#define GRF_SOC_CON21_OFFSET (0x6254)
#define DPHY_RX0_FORCERXMODE_MASK (0xF << 20)
#define DPHY_RX0_FORCERXMODE_BIT (4)
#define DPHY_RX0_FORCETXSTOPMODE_MASK (0xF << 24)
#define DPHY_RX0_FORCETXSTOPMODE_BIT (8)
#define DPHY_RX0_TURNDISABLE_MASK (0xF << 28)
#define DPHY_RX0_TURNDISABLE_BIT (12)
#define DPHY_RX0_ENABLE_MASK (0xF << 16)
#define DPHY_RX0_ENABLE_BIT (0)
#define GRF_SOC_CON23_OFFSET (0x625c)
#define DPHY_TX1RX1_TURNDISABLE_MASK (0xF << 28)
#define DPHY_TX1RX1_TURNDISABLE_BIT (12)
#define DPHY_TX1RX1_FORCERXMODE_MASK (0xF << 20)
#define DPHY_TX1RX1_FORCERXMODE_BIT (4)
#define DPHY_TX1RX1_FORCETXSTOPMODE_MASK (0xF << 24)
#define DPHY_TX1RX1_FORCETXSTOPMODE_BIT (8)
#define DPHY_TX1RX1_ENABLE_MASK (0xF << 16)
#define DPHY_TX1RX1_ENABLE_BIT (0)
#define GRF_SOC_CON24_OFFSET (0x6260)
#define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1 << 23)
#define DPHY_TX1RX1_MASTERSLAVEZ_BIT (7)
#define DPHY_TX1RX1_BASEDIR_MASK (0x1 << 21)
#define DPHY_TX1RX1_BASEDIR_BIT (5)
#define DPHY_RX1_MASK (0x1 << 20)
#define DPHY_RX1_SEL_BIT (4)
#define GRF_SOC_CON25_OFFSET (0x6264)
#define DPHY_RX0_TESTCLK_MASK (0x1 << 25)
#define DPHY_RX0_TESTCLK_BIT (9)
#define DPHY_RX0_TESTCLR_MASK (0x1 << 26)
#define DPHY_RX0_TESTCLR_BIT (10)
#define DPHY_RX0_TESTDIN_MASK (0xFF << 16)
#define DPHY_RX0_TESTDIN_BIT (0)
#define DPHY_RX0_TESTEN_MASK (0x1 << 24)
#define DPHY_RX0_TESTEN_BIT (8)
#define DPHY_TX1RX1_TURNREQUEST_MASK (0xF << 16)
#define DPHY_TX1RX1_TURNREQUEST_BIT (0)
#define DSIHOST_PHY_SHUTDOWNZ (0x00a0)
#define DSIHOST_DPHY_RSTZ (0x00a0)
#define DSIHOST_PHY_TEST_CTRL0 (0x00b4)
#define DSIHOST_PHY_TEST_CTRL1 (0x00b8)
#define write_cifisp_reg(addr, val) \
__raw_writel(val, (addr) + isp_cfg->isp_base)
#define read_cifisp_reg(addr) \
__raw_readl((addr) + isp_cfg->isp_base)
#define write_grf_reg(addr, val) \
regmap_write(isp_cfg->regmap_grf, addr, val)
#define read_grf_reg(addr, val) \
regmap_read(isp_cfg->regmap_grf, addr, val)
#define write_dsihost_reg(addr, val) \
__raw_writel(val, (addr) + isp_cfg->dsihost_base)
#define read_dsihost_reg(addr) \
__raw_readl((addr) + isp_cfg->dsihost_base)
enum cif_isp10_isp_idx {
CIF_ISP10_ISP0 = 0,
CIF_ISP10_ISP1 = 1
};
struct cif_isp10_clk_rst_rk3399 {
struct clk *hclk_isp0_noc;
struct clk *hclk_isp0_wrapper;
struct clk *hclk_isp1_noc;
struct clk *hclk_isp1_wrapper;
struct clk *aclk_isp0_noc;
struct clk *aclk_isp0_wrapper;
struct clk *aclk_isp1_noc;
struct clk *aclk_isp1_wrapper;
struct clk *clk_isp0;
struct clk *clk_isp1;
struct clk *pclkin_isp1;
struct clk *pclk_dphy_ref;
struct clk *pclk_dphytxrx;
struct clk *pclk_dphyrx;
struct clk *cif_clk_out;
struct clk *cif_clk_pll;
struct clk *cif_clk_mipi_dsi;
struct clk *cif_clk_mipi_dphy_cfg;
};
struct cif_isp10_rk3399 {
struct regmap *regmap_grf;
void __iomem *dsihost_base;
void __iomem *isp_base;
struct cif_isp10_clk_rst_rk3399 clk_rst;
struct cif_isp10_device *cif_isp10;
enum cif_isp10_isp_idx isp_idx;
};
struct mipi_dphy_hsfreqrange {
unsigned int range_l;
unsigned int range_h;
unsigned char cfg_bit;
};
static struct mipi_dphy_hsfreqrange mipi_dphy_hsfreq_range[] = {
{80, 90, 0x00},
{90, 100, 0x10},
{100, 110, 0x20},
{110, 130, 0x01},
{130, 140, 0x11},
{140, 150, 0x21},
{150, 170, 0x02},
{170, 180, 0x12},
{180, 200, 0x22},
{200, 220, 0x03},
{220, 240, 0x13},
{240, 250, 0x23},
{250, 270, 0x4},
{270, 300, 0x14},
{300, 330, 0x5},
{330, 360, 0x15},
{360, 400, 0x25},
{400, 450, 0x06},
{450, 500, 0x16},
{500, 550, 0x07},
{550, 600, 0x17},
{600, 650, 0x08},
{650, 700, 0x18},
{700, 750, 0x09},
{750, 800, 0x19},
{800, 850, 0x29},
{850, 900, 0x39},
{900, 950, 0x0a},
{950, 1000, 0x1a},
{1000, 1050, 0x2a},
{1100, 1150, 0x3a},
{1150, 1200, 0x0b},
{1200, 1250, 0x1b},
{1250, 1300, 0x2b},
{1300, 1350, 0x0c},
{1350, 1400, 0x1c},
{1400, 1450, 0x2c},
{1450, 1500, 0x3c}
};
static int mipi_dphy0_wr_reg(struct cif_isp10_rk3399 *isp_cfg, unsigned char addr, unsigned char data)
{
/*
* TESTCLK=1
* TESTEN =1,TESTDIN=addr
* TESTCLK=0
*/
write_grf_reg(GRF_SOC_CON25_OFFSET,
DPHY_RX0_TESTCLK_MASK | (1 << DPHY_RX0_TESTCLK_BIT));
write_grf_reg(GRF_SOC_CON25_OFFSET,
((addr << DPHY_RX0_TESTDIN_BIT) | DPHY_RX0_TESTDIN_MASK
| (1 << DPHY_RX0_TESTEN_BIT) | DPHY_RX0_TESTEN_MASK));
write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
/*
* write data:
* TESTEN =0,TESTDIN=data
* TESTCLK=1
*/
if (data != 0xff) {
write_grf_reg(GRF_SOC_CON25_OFFSET,
((data << DPHY_RX0_TESTDIN_BIT) |
DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN_MASK));
write_grf_reg(GRF_SOC_CON25_OFFSET,
DPHY_RX0_TESTCLK_MASK | (1 << DPHY_RX0_TESTCLK_BIT));
}
return 0;
}
static int mipi_dphy0_rd_reg(struct cif_isp10_rk3399 *isp_cfg, unsigned char addr)
{
int val = 0;
/*TESTCLK=1*/
write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK |
(1 << DPHY_RX0_TESTCLK_BIT));
/*TESTEN =1,TESTDIN=addr*/
write_grf_reg(GRF_SOC_CON25_OFFSET,
((addr << DPHY_RX0_TESTDIN_BIT) |
DPHY_RX0_TESTDIN_MASK |
(1 << DPHY_RX0_TESTEN_BIT) |
DPHY_RX0_TESTEN_MASK));
/*TESTCLK=0*/
write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
read_grf_reg(GRF_SOC_STATUS1, &val);
return val & 0xff;
}
static int mipi_dphy1_wr_reg(struct cif_isp10_rk3399 *isp_cfg, unsigned char addr, unsigned char data)
{
/*
* TESTEN =1,TESTDIN=addr
* TESTCLK=0
* TESTEN =0,TESTDIN=data
* TESTCLK=1
*/
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
return 0;
}
static int mipi_dphy1_rd_reg(struct cif_isp10_rk3399 *isp_cfg, unsigned char addr)
{
/* TESTEN =1,TESTDIN=addr */
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
/* TESTCLK=0 */
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
return ((read_dsihost_reg(DSIHOST_PHY_TEST_CTRL1) & 0xff00) >> 8);
}
static int mipi_dphy_cfg(struct cif_isp10_rk3399 *isp_cfg, struct pltfrm_cam_mipi_config *para)
{
unsigned char hsfreqrange = 0xff, i;
struct mipi_dphy_hsfreqrange *hsfreqrange_p;
unsigned char datalane_en, input_sel;
hsfreqrange_p = mipi_dphy_hsfreq_range;
for (i = 0;
i < (sizeof(mipi_dphy_hsfreq_range) /
sizeof(struct mipi_dphy_hsfreqrange));
i++) {
if ((para->bit_rate > hsfreqrange_p->range_l) &&
(para->bit_rate <= hsfreqrange_p->range_h)) {
hsfreqrange = hsfreqrange_p->cfg_bit;
break;
}
hsfreqrange_p++;
}
if (hsfreqrange == 0xff)
hsfreqrange = 0x00;
hsfreqrange <<= 1;
input_sel = para->dphy_index;
datalane_en = 0;
for (i = 0; i < para->nb_lanes; i++)
datalane_en |= (1 << i);
if (input_sel == 0) {
/*
* According to the sequence of RK3399_TXRX_DPHY, the setting of isp0 mipi
* will affect txrx dphy in default state of grf_soc_con24.
*/
write_grf_reg(GRF_SOC_CON24_OFFSET,
DPHY_TX1RX1_MASTERSLAVEZ_MASK |
(0x0 << DPHY_TX1RX1_MASTERSLAVEZ_BIT) |
DPHY_TX1RX1_BASEDIR_MASK |
(0x1 << DPHY_TX1RX1_BASEDIR_BIT) |
DPHY_RX1_MASK | 0x0 << DPHY_RX1_SEL_BIT);
write_grf_reg(GRF_SOC_CON21_OFFSET,
DPHY_RX0_FORCERXMODE_MASK |
(0x0 << DPHY_RX0_FORCERXMODE_BIT) |
DPHY_RX0_FORCETXSTOPMODE_MASK |
(0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
/* set lane num */
write_grf_reg(GRF_SOC_CON21_OFFSET,
DPHY_RX0_ENABLE_MASK |
(datalane_en << DPHY_RX0_ENABLE_BIT));
/* set lan turndisab as 1 */
write_grf_reg(GRF_SOC_CON21_OFFSET,
DPHY_RX0_TURNDISABLE_MASK |
(0xf << DPHY_RX0_TURNDISABLE_BIT));
write_grf_reg(GRF_SOC_CON21_OFFSET, (0x0 << 4) | (0xf << 20));
/* set lan turnrequest as 0 */
write_grf_reg(GRF_SOC_CON9_OFFSET,
DPHY_RX0_TURNREQUEST_MASK |
(0x0 << DPHY_RX0_TURNREQUEST_BIT));
/* phy start */
/*
* TESTCLK=1
* TESTCLR=1
* delay 100us
* TESTCLR=0
*/
write_grf_reg(GRF_SOC_CON25_OFFSET,
DPHY_RX0_TESTCLK_MASK |
(0x1 << DPHY_RX0_TESTCLK_BIT)); /* TESTCLK=1 */
write_grf_reg(GRF_SOC_CON25_OFFSET,
DPHY_RX0_TESTCLR_MASK |
(0x1 << DPHY_RX0_TESTCLR_BIT)); /* TESTCLR=1 */
usleep_range(100, 150);
/* TESTCLR=0 zyc */
write_grf_reg(GRF_SOC_CON25_OFFSET,
DPHY_RX0_TESTCLR_MASK);
usleep_range(100, 150);
/* set clock lane */
mipi_dphy0_wr_reg
(isp_cfg, 0x34, 0);
/* HS hsfreqrange & lane 0 settle bypass */
mipi_dphy0_wr_reg(isp_cfg, 0x44, hsfreqrange);
mipi_dphy0_wr_reg(isp_cfg, 0x54, 0);
mipi_dphy0_wr_reg(isp_cfg, 0x84, 0);
mipi_dphy0_wr_reg(isp_cfg, 0x94, 0);
mipi_dphy0_wr_reg(isp_cfg, 0x75, 0x04);
mipi_dphy0_rd_reg(isp_cfg, 0x75);
/* Normal operation */
/*
* TESTCLK=1
* TESTEN =0
*/
mipi_dphy0_wr_reg(isp_cfg, 0x0, -1);
write_grf_reg(GRF_SOC_CON25_OFFSET,
DPHY_RX0_TESTCLK_MASK | (1 << DPHY_RX0_TESTCLK_BIT));
write_grf_reg(GRF_SOC_CON25_OFFSET,
(DPHY_RX0_TESTEN_MASK));
write_cifisp_reg((MRV_MIPI_BASE + MRV_MIPI_CTRL),
read_cifisp_reg(MRV_MIPI_BASE + MRV_MIPI_CTRL)
| (0x0f << 8));
} else if (input_sel == 1) {
write_grf_reg(GRF_SOC_CON23_OFFSET,
DPHY_RX0_FORCERXMODE_MASK |
(0x0 << DPHY_RX0_FORCERXMODE_BIT) |
DPHY_RX0_FORCETXSTOPMODE_MASK |
(0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
write_grf_reg(GRF_SOC_CON24_OFFSET,
DPHY_TX1RX1_MASTERSLAVEZ_MASK |
(0x0 << DPHY_TX1RX1_MASTERSLAVEZ_BIT) |
DPHY_TX1RX1_BASEDIR_MASK |
(0x1 << DPHY_TX1RX1_BASEDIR_BIT) |
DPHY_RX1_MASK | 0x0 << DPHY_RX1_SEL_BIT);
/* set lane num */
write_grf_reg(GRF_SOC_CON23_OFFSET,
DPHY_TX1RX1_ENABLE_MASK |
(datalane_en << DPHY_TX1RX1_ENABLE_BIT));
/* set lan turndisab as 1 */
write_grf_reg(GRF_SOC_CON23_OFFSET,
DPHY_TX1RX1_TURNDISABLE_MASK |
(0xf << DPHY_TX1RX1_TURNDISABLE_BIT));
write_grf_reg(GRF_SOC_CON23_OFFSET, (0x0 << 4) | (0xf << 20));
/* set lan turnrequest as 0 */
write_grf_reg(GRF_SOC_CON24_OFFSET,
DPHY_TX1RX1_TURNREQUEST_MASK |
(0x0 << DPHY_TX1RX1_TURNREQUEST_BIT));
/* phy1 start */
/*
* SHUTDOWNZ=0
* RSTZ=0
* TESTCLK=1
* TESTCLR=1 TESTCLK=1
* TESTCLR=0 TESTCLK=1
*/
write_dsihost_reg(DSIHOST_PHY_SHUTDOWNZ, 0x00000000);
write_dsihost_reg(DSIHOST_DPHY_RSTZ, 0x00000000);
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, 0x00000003);
usleep_range(100, 150);
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
usleep_range(100, 150);
/* set clock lane */
mipi_dphy1_wr_reg(isp_cfg, 0x34, 0x00);
mipi_dphy1_wr_reg(isp_cfg, 0x44, hsfreqrange);
mipi_dphy1_wr_reg(isp_cfg, 0x54, 0);
mipi_dphy1_wr_reg(isp_cfg, 0x84, 0);
mipi_dphy1_wr_reg(isp_cfg, 0x94, 0);
mipi_dphy1_wr_reg(isp_cfg, 0x75, 0x04);
mipi_dphy1_rd_reg(isp_cfg, 0x0);
/*
* TESTCLK=1
* TESTEN =0
* SHUTDOWNZ=1
* RSTZ=1
*/
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, 0x00000000);
/*SHUTDOWNZ=1, RSTZ=1*/
write_dsihost_reg(DSIHOST_DPHY_RSTZ, 0x00000003);
write_cifisp_reg((MRV_MIPI_BASE + MRV_MIPI_CTRL),
read_cifisp_reg(MRV_MIPI_BASE + MRV_MIPI_CTRL)
| (0x0f << 8));
} else {
goto fail;
}
return 0;
fail:
return -1;
}
static int soc_clk_enable(struct cif_isp10_rk3399 *isp_cfg)
{
struct cif_isp10_clk_rst_rk3399 *clk_rst = &isp_cfg->clk_rst;
if (isp_cfg->isp_idx == CIF_ISP10_ISP0) {
clk_prepare_enable(clk_rst->hclk_isp0_noc);
clk_prepare_enable(clk_rst->hclk_isp0_wrapper);
clk_prepare_enable(clk_rst->aclk_isp0_noc);
clk_prepare_enable(clk_rst->aclk_isp0_wrapper);
clk_prepare_enable(clk_rst->clk_isp0);
clk_prepare_enable(clk_rst->pclk_dphyrx);
clk_prepare_enable(clk_rst->cif_clk_out);
clk_prepare_enable(clk_rst->pclk_dphy_ref);
} else {
clk_prepare_enable(clk_rst->hclk_isp1_noc);
clk_prepare_enable(clk_rst->hclk_isp1_wrapper);
clk_prepare_enable(clk_rst->aclk_isp1_noc);
clk_prepare_enable(clk_rst->aclk_isp1_wrapper);
clk_prepare_enable(clk_rst->clk_isp1);
clk_prepare_enable(clk_rst->pclkin_isp1);
clk_prepare_enable(clk_rst->pclk_dphytxrx);
clk_prepare_enable(clk_rst->cif_clk_mipi_dsi);
clk_prepare_enable(clk_rst->cif_clk_mipi_dphy_cfg);
clk_prepare_enable(clk_rst->cif_clk_out);
clk_prepare_enable(clk_rst->pclk_dphy_ref);
}
return 0;
}
static int soc_clk_disable(struct cif_isp10_rk3399 *isp_cfg)
{
struct cif_isp10_clk_rst_rk3399 *clk_rst = &isp_cfg->clk_rst;
if (isp_cfg->isp_idx == CIF_ISP10_ISP0) {
clk_disable_unprepare(clk_rst->hclk_isp0_noc);
clk_disable_unprepare(clk_rst->hclk_isp0_wrapper);
clk_disable_unprepare(clk_rst->aclk_isp0_noc);
clk_disable_unprepare(clk_rst->aclk_isp0_wrapper);
clk_disable_unprepare(clk_rst->clk_isp0);
clk_disable_unprepare(clk_rst->pclk_dphyrx);
if (!IS_ERR_OR_NULL(clk_rst->cif_clk_pll))
clk_set_parent(clk_rst->cif_clk_out,
clk_rst->cif_clk_pll);
clk_disable_unprepare(clk_rst->cif_clk_out);
clk_disable_unprepare(clk_rst->pclk_dphy_ref);
} else {
clk_disable_unprepare(clk_rst->hclk_isp1_noc);
clk_disable_unprepare(clk_rst->hclk_isp1_wrapper);
clk_disable_unprepare(clk_rst->aclk_isp1_noc);
clk_disable_unprepare(clk_rst->aclk_isp1_wrapper);
clk_disable_unprepare(clk_rst->clk_isp1);
clk_disable_unprepare(clk_rst->pclkin_isp1);
clk_disable_unprepare(clk_rst->pclk_dphytxrx);
clk_disable_unprepare(clk_rst->cif_clk_mipi_dsi);
clk_disable_unprepare(clk_rst->cif_clk_mipi_dphy_cfg);
if (!IS_ERR_OR_NULL(clk_rst->cif_clk_pll))
clk_set_parent(clk_rst->cif_clk_out,
clk_rst->cif_clk_pll);
clk_disable_unprepare(clk_rst->cif_clk_out);
clk_disable_unprepare(clk_rst->pclk_dphy_ref);
}
return 0;
}
static int soc_init(struct cif_isp10_rk3399 **isp_cfg, struct pltfrm_soc_init_para *init)
{
struct cif_isp10_clk_rst_rk3399 *clk_rst;
struct platform_device *pdev = init->pdev;
struct device_node *np = pdev->dev.of_node, *node;
struct resource *res;
struct cif_isp10_rk3399 *isp_cfg_tmp;
int err;
*isp_cfg = NULL;
isp_cfg_tmp = (struct cif_isp10_rk3399 *)devm_kzalloc(
&pdev->dev,
sizeof(struct cif_isp10_rk3399),
GFP_KERNEL);
if (!isp_cfg_tmp) {
dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3399\n");
err = -ENOMEM;
goto alloc_failed;
}
node = of_parse_phandle(np, "rockchip,grf", 0);
if (node) {
isp_cfg_tmp->regmap_grf = syscon_node_to_regmap(node);
if (IS_ERR(isp_cfg_tmp->regmap_grf)) {
dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3399\n");
err = -ENODEV;
goto regmap_failed;
}
}
clk_rst = &isp_cfg_tmp->clk_rst;
if (strcmp(pdev->name, "ff910000.cif_isp") == 0) {
clk_rst->hclk_isp0_noc =
devm_clk_get(&pdev->dev, "hclk_isp0_noc");
clk_rst->hclk_isp0_wrapper =
devm_clk_get(&pdev->dev, "hclk_isp0_wrapper");
clk_rst->aclk_isp0_noc =
devm_clk_get(&pdev->dev, "aclk_isp0_noc");
clk_rst->aclk_isp0_wrapper =
devm_clk_get(&pdev->dev, "aclk_isp0_wrapper");
clk_rst->clk_isp0 =
devm_clk_get(&pdev->dev, "clk_isp0");
clk_rst->pclk_dphyrx =
devm_clk_get(&pdev->dev, "pclk_dphyrx");
clk_rst->cif_clk_out =
devm_clk_get(&pdev->dev, "clk_cif_out");
clk_rst->cif_clk_pll =
devm_clk_get(&pdev->dev, "clk_cif_pll");
clk_rst->pclk_dphy_ref =
devm_clk_get(&pdev->dev, "pclk_dphy_ref");
if (IS_ERR_OR_NULL(clk_rst->hclk_isp0_noc) ||
IS_ERR_OR_NULL(clk_rst->hclk_isp0_wrapper) ||
IS_ERR_OR_NULL(clk_rst->aclk_isp0_noc) ||
IS_ERR_OR_NULL(clk_rst->aclk_isp0_wrapper) ||
IS_ERR_OR_NULL(clk_rst->clk_isp0) ||
IS_ERR_OR_NULL(clk_rst->pclk_dphyrx) ||
IS_ERR_OR_NULL(clk_rst->cif_clk_out) ||
IS_ERR_OR_NULL(clk_rst->pclk_dphy_ref)) {
dev_err(&pdev->dev, "Get rk3399 cif isp10 clock resouce failed !\n");
err = -EINVAL;
goto clk_failed;
}
clk_set_rate(clk_rst->clk_isp0, 420000000);
isp_cfg_tmp->isp_idx = CIF_ISP10_ISP0;
} else {
res = platform_get_resource_byname(pdev,
IORESOURCE_MEM, "dsihost-register");
if (!res) {
dev_err(&pdev->dev,
"platform_get_resource_byname dsihost-register failed\n");
err = -ENODEV;
goto regmap_failed;
}
isp_cfg_tmp->dsihost_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR_OR_NULL(isp_cfg_tmp->dsihost_base)) {
dev_err(&pdev->dev, "devm_ioremap_resource failed\n");
if (IS_ERR(isp_cfg_tmp->dsihost_base))
err = PTR_ERR(isp_cfg_tmp->dsihost_base);
else
err = -ENODEV;
goto regmap_failed;
}
clk_rst->hclk_isp1_noc =
devm_clk_get(&pdev->dev, "hclk_isp1_noc");
clk_rst->hclk_isp1_wrapper =
devm_clk_get(&pdev->dev, "hclk_isp1_wrapper");
clk_rst->aclk_isp1_noc =
devm_clk_get(&pdev->dev, "aclk_isp1_noc");
clk_rst->aclk_isp1_wrapper =
devm_clk_get(&pdev->dev, "aclk_isp1_wrapper");
clk_rst->clk_isp1 =
devm_clk_get(&pdev->dev, "clk_isp1");
clk_rst->pclkin_isp1 =
devm_clk_get(&pdev->dev, "pclkin_isp1");
clk_rst->pclk_dphytxrx =
devm_clk_get(&pdev->dev, "pclk_dphytxrx");
clk_rst->cif_clk_mipi_dsi =
devm_clk_get(&pdev->dev, "pclk_mipi_dsi");
clk_rst->cif_clk_mipi_dphy_cfg =
devm_clk_get(&pdev->dev, "mipi_dphy_cfg");
clk_rst->cif_clk_out =
devm_clk_get(&pdev->dev, "clk_cif_out");
clk_rst->cif_clk_pll =
devm_clk_get(&pdev->dev, "clk_cif_pll");
clk_rst->pclk_dphy_ref =
devm_clk_get(&pdev->dev, "pclk_dphy_ref");
if (IS_ERR_OR_NULL(clk_rst->hclk_isp1_noc) ||
IS_ERR_OR_NULL(clk_rst->hclk_isp1_wrapper) ||
IS_ERR_OR_NULL(clk_rst->aclk_isp1_noc) ||
IS_ERR_OR_NULL(clk_rst->aclk_isp1_wrapper) ||
IS_ERR_OR_NULL(clk_rst->clk_isp1) ||
IS_ERR_OR_NULL(clk_rst->pclkin_isp1) ||
IS_ERR_OR_NULL(clk_rst->pclk_dphytxrx) ||
IS_ERR_OR_NULL(clk_rst->cif_clk_mipi_dsi) ||
IS_ERR_OR_NULL(clk_rst->cif_clk_mipi_dphy_cfg) ||
IS_ERR_OR_NULL(clk_rst->cif_clk_out) ||
IS_ERR_OR_NULL(clk_rst->pclk_dphy_ref)) {
dev_err(&pdev->dev, "Get rk3399 cif isp10 clock resouce failed !\n");
err = -EINVAL;
goto clk_failed;
}
clk_set_rate(clk_rst->clk_isp1, 420000000);
isp_cfg_tmp->isp_idx = CIF_ISP10_ISP1;
}
isp_cfg_tmp->isp_base = init->isp_base;
*isp_cfg = isp_cfg_tmp;
return 0;
clk_failed:
if (!IS_ERR_OR_NULL(clk_rst->hclk_isp0_noc))
devm_clk_put(&pdev->dev, clk_rst->hclk_isp0_noc);
if (!IS_ERR_OR_NULL(clk_rst->hclk_isp0_wrapper))
devm_clk_put(&pdev->dev, clk_rst->hclk_isp0_wrapper);
if (!IS_ERR_OR_NULL(clk_rst->aclk_isp0_noc))
devm_clk_put(&pdev->dev, clk_rst->aclk_isp0_noc);
if (!IS_ERR_OR_NULL(clk_rst->aclk_isp0_wrapper))
devm_clk_put(&pdev->dev, clk_rst->aclk_isp0_wrapper);
if (!IS_ERR_OR_NULL(clk_rst->clk_isp0))
devm_clk_put(&pdev->dev, clk_rst->clk_isp0);
if (!IS_ERR_OR_NULL(clk_rst->pclk_dphyrx))
devm_clk_put(&pdev->dev, clk_rst->pclk_dphyrx);
if (!IS_ERR_OR_NULL(clk_rst->hclk_isp1_noc))
devm_clk_put(&pdev->dev, clk_rst->hclk_isp1_noc);
if (!IS_ERR_OR_NULL(clk_rst->hclk_isp1_wrapper))
devm_clk_put(&pdev->dev, clk_rst->hclk_isp1_wrapper);
if (!IS_ERR_OR_NULL(clk_rst->aclk_isp1_noc))
devm_clk_put(&pdev->dev, clk_rst->aclk_isp1_noc);
if (!IS_ERR_OR_NULL(clk_rst->aclk_isp1_wrapper))
devm_clk_put(&pdev->dev, clk_rst->aclk_isp1_wrapper);
if (!IS_ERR_OR_NULL(clk_rst->clk_isp1))
devm_clk_put(&pdev->dev, clk_rst->clk_isp1);
if (!IS_ERR_OR_NULL(clk_rst->pclkin_isp1))
devm_clk_put(&pdev->dev, clk_rst->pclkin_isp1);
if (!IS_ERR_OR_NULL(clk_rst->pclk_dphytxrx))
devm_clk_put(&pdev->dev, clk_rst->pclk_dphytxrx);
if (!IS_ERR_OR_NULL(clk_rst->cif_clk_mipi_dsi))
devm_clk_put(&pdev->dev, clk_rst->cif_clk_mipi_dsi);
if (!IS_ERR_OR_NULL(clk_rst->cif_clk_mipi_dphy_cfg))
devm_clk_put(&pdev->dev, clk_rst->cif_clk_mipi_dphy_cfg);
if (!IS_ERR_OR_NULL(clk_rst->cif_clk_out))
devm_clk_put(&pdev->dev, clk_rst->cif_clk_out);
if (!IS_ERR_OR_NULL(clk_rst->pclk_dphy_ref))
devm_clk_put(&pdev->dev, clk_rst->pclk_dphy_ref);
regmap_failed:
alloc_failed:
return err;
}
int pltfrm_rk3399_cfg(struct pltfrm_soc_cfg_para *cfg)
{
int ret = -1;
struct cif_isp10_rk3399 *isp_cfg = NULL;
if (cfg->isp_config == NULL) {
return -1;
} else {
isp_cfg = (struct cif_isp10_rk3399 *)(*cfg->isp_config);
if (isp_cfg == NULL && cfg->cmd != PLTFRM_SOC_INIT)
return -1;
}
switch (cfg->cmd) {
case PLTFRM_MCLK_CFG: {
struct pltfrm_soc_mclk_para *mclk_para;
mclk_para = (struct pltfrm_soc_mclk_para *)cfg->cfg_para;
if (mclk_para->io_voltage == PLTFRM_IO_1V8)
write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V18SEL);
else
write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V33SEL);
write_grf_reg(GRF_GPIO2B_E_OFFSET,
CIF_CLKOUT_STRENGTH(mclk_para->drv_strength));
ret = 0;
break;
}
case PLTFRM_MIPI_DPHY_CFG:
ret = mipi_dphy_cfg(isp_cfg, (struct pltfrm_cam_mipi_config *)cfg->cfg_para);
break;
case PLTFRM_CLKEN:
ret = soc_clk_enable(isp_cfg);
break;
case PLTFRM_CLKDIS:
ret = soc_clk_disable(isp_cfg);
break;
case PLTFRM_CLKRST:
write_cifisp_reg(VI_IRCL, 0xf7f);
usleep_range(10, 15);
write_cifisp_reg(VI_IRCL, 0x00);
ret = 0;
break;
case PLTFRM_SOC_INIT:
ret = soc_init((struct cif_isp10_rk3399 **)cfg->isp_config, (struct pltfrm_soc_init_para *)cfg->cfg_para);
break;
default:
break;
}
return ret;
}

2255
drivers/media/platform/rk-isp10/cif_isp10_v4l2.c
View File

File diff suppressed because it is too large Load Diff

133
drivers/media/platform/rk-isp10/cif_isp10_version.h
View File

@ -1,133 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#ifndef _CIF_ISP10_RK_VERSION_H_
#define _CIF_ISP10_RK_VERSION_H_
#include <linux/version.h>
/*
* CIF DRIVER VERSION NOTE
*
*v0.1.0:
*1. New mi register update mode is invalidate in raw/jpeg for rk1108,
* All path used old mode for rk1108;
*v0.1.1:
*1. Modify CIF stop sequence for fix isp bus may dead when switch isp:
*Original stop sequence: Stop ISP(mipi) -> Stop ISP(isp) ->wait for ISP
*isp off -> Stop ISP(mi)
*Current stop sequence: ISP(mi) stop in mi frame end -> Stop ISP(mipi)
*-> Stop ISP(isp) ->wait for ISP isp off;
* Current stop sequence is only match sensor stream v-blanking >= 1.5ms;
*
*v0.1.2:
*1. Disable CIF_MIPI_ERR_DPHY interrupt here temporary for
*isp bus may be dead when switch isp;
*2. Cancel hw restart isp operation in mipi isr, only notice error log;
*
*v0.1.3:
*1. fix camerahal query exp info failed from cifisp_stat_buffer, because
*wake_up buffer before cif_isp11_sensor_mode_data_sync;
*
*v0.1.4:
*1. Disable DPHY errctrl interrupt, because this dphy erctrl signal
*is assert and until the next changes in line state. This time is may
*be too long and cpu is hold in this interrupt. Enable DPHY errctrl
*interrupt again, if mipi have receive the whole frame without any error.
*2. Modify mipi_dphy_cfg follow vendor recommended process in
*document.
*3. Select the limit dphy setting if sensor mipi datarate is overflow,
*and print warning information to user.
*
*v0.1.5:
*Exposure list must be queue operation, not stack. list_add switch to
*list_add_tail in cif_isp11_s_exp;
*
*v0.1.6:
*Add isp output size in struct isp_supplemental_sensor_mode_data.
*
*v0.1.7:
*Add support to isp1.
*The running of isp0 or isp1 is ok,
*but running of isp0 and isp1 at the same time has not been tested.
*
*v0.1.8:
*Fix oops error when soc_clk_disable is called in rk3399.
*
*v0.1.9:
*1. Support bt656 signal interlace: odd and even field interlace generating
*a frame image.
*2. fix cif_isp10_img_src_v4l2_subdev_enum_strm_fmts defrect info get error.
*3. fix cif_isp10_rk3399 cif_clk_pll info doesn't match with dts config.
*
*v0.1.0xa
*Based on version 0.1.9:
*1. To optimize the readability of the code.
*2. optimize CIF_MI_CTRL_BURST_LEN param.
*3. Add the check for cam_itf.type(PLTFRM_CAM_ITF_BT656_8I) on
* cif_isp10_s_fmt_mp.
*4. get field_flag value from cif_isp10_isp_isr.
*
*v0.1.0xb
*1. Initialize default format for current stream.
*2. Implement command VIDIOC_G_FMT.
*3. Set bytesused of each plane to its real size.
*4. Support io mode 'VB2_DMABUF'.
*
*v0.1.0xc
*1. support isp0 and isp1 run at the same time.
*2. support VIDIOC_G_INPUT command.
*3. support VIDIOC_G_PARM command.
*4. support VIDIOC_G_PARM command.
*5. add pix.bytesperline and pix.sizeimage in VIDIOC_G_FMT command.
*
*v0.1.0xd
*1. Support RGB24(xRGB8888) format of SP Path.
*
*v0.1.0xe
*1. fix owned_by_drv_count is not 0 when stop stream.
*2. fix write fmt is not correct when setting mi_ctrl.
*3. modify for dumpsys tool.
*4. remove "Measurement late" check.
*5. modify for af function.
*6. add module parameter for dumpsys.
*
*v0.1.0xf
*1. merge modification from rv1108 project.
*
*v0.2.0x0
*1. fix compile warning.
*2. add check of iommu status.
*3. support stream on/off/on/off...
*4. get correct isp out width/height.
*5. fix the issue that setting of isp0 mipi affect txrx dphy.
*6. fix the issue cannot set exposure by mp path device.
*
*v0.2.0x1
*1. add isp reset function.
*2. fix the issue that setting of isp0 mipi affect txrx dphy.
*
*v0.2.0x2
*1. fix fmt selection.
*2. MP/SP burst config with resolution.
*3. fix one vb is in queue.done_list twice.
*4. fix lose buffer in qduf ioctl.
*5. fix AE information is not correct when updating exposure by each frame.
*6. support Y8/Y12 grey sensor.
*
*/
#define CONFIG_CIFISP10_DRIVER_VERSION KERNEL_VERSION(0, 2, 0x2)
#endif

196
include/linux/platform_data/rk_isp10_platform.h
View File

@ -1,196 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#ifndef _CIF_ISP10_PLATFORM_H
#define _CIF_ISP10_PLATFORM_H
#include <linux/videodev2.h>
#define CIF_ISP10_SOC_RK3288 "rk3288"
#define CIF_ISP10_SOC_RK3368 "rk3368"
#define CIF_ISP10_SOC_RK3399 "rk3399"
#define DRIVER_NAME "rkisp10"
#define ISP_VDEV_NAME DRIVER_NAME "_ispdev"
#define SP_VDEV_NAME DRIVER_NAME "_selfpath"
#define MP_VDEV_NAME DRIVER_NAME "_mainpath"
#define DMA_VDEV_NAME DRIVER_NAME "_dmapath"
enum pltfrm_cam_signal_polarity {
PLTFRM_CAM_SIGNAL_HIGH_LEVEL = 0,
PLTFRM_CAM_SIGNAL_LOW_LEVEL = 1,
};
enum pltfrm_cam_sample_type {
PLTFRM_CAM_SDR_NEG_EDG = 0x10000001,
PLTFRM_CAM_SDR_POS_EDG = 0x10000002,
PLTFRM_CAM_DDR = 0x20000000
};
enum pltfrm_cam_itf_type {
PLTFRM_CAM_ITF_MIPI = 0x10000000,
PLTFRM_CAM_ITF_BT601_8 = 0x20000071,
PLTFRM_CAM_ITF_BT656_8 = 0x20000072,
PLTFRM_CAM_ITF_BT601_10 = 0x20000091,
PLTFRM_CAM_ITF_BT656_10 = 0x20000092,
PLTFRM_CAM_ITF_BT601_12 = 0x200000B1,
PLTFRM_CAM_ITF_BT656_12 = 0x200000B2,
PLTFRM_CAM_ITF_BT601_16 = 0x200000F1,
PLTFRM_CAM_ITF_BT656_16 = 0x200000F2,
PLTFRM_CAM_ITF_BT656_8I = 0x20000172
};
#define PLTFRM_CAM_ITF_MAIN_MASK 0xf0000000
#define PLTFRM_CAM_ITF_SUB_MASK 0x0000000f
#define PLTFRM_CAM_ITF_DVP_BW_MASK 0x000000f0
#define PLTFRM_CAM_ITF_INTERLACE_MASK 0x00000100
#define PLTFRM_CAM_ITF_IS_MIPI(a) \
(((a) & PLTFRM_CAM_ITF_MAIN_MASK) == 0x10000000)
#define PLTFRM_CAM_ITF_IS_DVP(a) \
(((a) & PLTFRM_CAM_ITF_MAIN_MASK) == 0x20000000)
#define PLTFRM_CAM_ITF_IS_BT656(a) (PLTFRM_CAM_ITF_IS_DVP(a) &&\
(((a) & PLTFRM_CAM_ITF_SUB_MASK) == 0x02))
#define PLTFRM_CAM_ITF_IS_BT601(a) (PLTFRM_CAM_ITF_IS_DVP(a) &&\
(((a) & PLTFRM_CAM_ITF_SUB_MASK) == 0x01))
#define PLTFRM_CAM_ITF_DVP_BW(a) \
((((a) & PLTFRM_CAM_ITF_DVP_BW_MASK) >> 4) + 1)
#define PLTFRM_CAM_ITF_INTERLACE(a) \
(((a) & PLTFRM_CAM_ITF_INTERLACE_MASK) == 0x00000100)
struct pltfrm_cam_mipi_config {
u32 dphy_index;
u32 vc;
u32 nb_lanes;
u32 bit_rate;
};
struct pltfrm_cam_dvp_config {
enum pltfrm_cam_signal_polarity vsync;
enum pltfrm_cam_signal_polarity hsync;
enum pltfrm_cam_sample_type pclk;
};
struct pltfrm_cam_itf {
enum pltfrm_cam_itf_type type;
union {
struct pltfrm_cam_mipi_config mipi;
struct pltfrm_cam_dvp_config dvp;
} cfg;
unsigned int mclk_hz;
};
#define PLTFRM_CAM_ITF_MIPI_CFG(v, nb, br, mk)\
.itf_cfg = {\
.type = PLTFRM_CAM_ITF_MIPI,\
.cfg = {\
.mipi = {\
.dphy_index = 0,\
.vc = v,\
.nb_lanes = nb,\
.bit_rate = br,\
} \
},\
.mclk_hz = mk\
}
#define PLTFRM_CAM_ITF_DVP_CFG(ty, vs, hs, ck, mk)\
.itf_cfg = {\
.type = ty,\
.cfg = {\
.dvp = {\
.vsync = vs,\
.hsync = hs,\
.pclk = ck,\
} \
},\
.mclk_hz = mk\
}
#define PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE 0x00
#define PLTFRM_CIFCAM_G_ITF_CFG \
(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 1)
#define PLTFRM_CIFCAM_G_DEFRECT \
(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 2)
#define PLTFRM_CIFCAM_ATTACH \
(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 3)
#define PLTFRM_CIFCAM_SET_VCM_POS \
(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 4)
#define PLTFRM_CIFCAM_GET_VCM_POS \
(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 5)
#define PLTFRM_CIFCAM_GET_VCM_MOVE_RES \
(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 6)
struct pltfrm_cam_vcm_tim {
struct timeval vcm_start_t;
struct timeval vcm_end_t;
};
struct pltfrm_cam_defrect {
unsigned int width;
unsigned int height;
struct v4l2_rect defrect;
};
enum pltfrm_soc_cfg_cmd {
PLTFRM_MCLK_CFG = 0,
PLTFRM_MIPI_DPHY_CFG,
PLTFRM_CLKEN,
PLTFRM_CLKDIS,
PLTFRM_CLKRST,
PLTFRM_SOC_INIT
};
enum pltfrm_soc_io_voltage {
PLTFRM_IO_1V8 = 0,
PLTFRM_IO_3V3 = 1
};
enum pltfrm_soc_drv_strength {
PLTFRM_DRV_STRENGTH_0 = 0,
PLTFRM_DRV_STRENGTH_1 = 1,
PLTFRM_DRV_STRENGTH_2 = 2,
PLTFRM_DRV_STRENGTH_3 = 3
};
struct pltfrm_soc_init_para {
struct platform_device *pdev;
void __iomem *isp_base;
};
struct pltfrm_soc_mclk_para {
enum pltfrm_soc_io_voltage io_voltage;
enum pltfrm_soc_drv_strength drv_strength;
};
struct pltfrm_soc_cfg_para {
enum pltfrm_soc_cfg_cmd cmd;
void **isp_config;
void *cfg_para;
};
struct pltfrm_soc_cfg {
char name[32];
void *isp_config;
int (*soc_cfg)(struct pltfrm_soc_cfg_para *cfg);
};
int pltfrm_rk3288_cfg(struct pltfrm_soc_cfg_para *cfg);
int pltfrm_rk3399_cfg(struct pltfrm_soc_cfg_para *cfg);
#endif

592
include/media/rk-isp10-config.h
View File

@ -1,592 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#ifndef _RK_ISP11_CONFIG_H
#define _RK_ISP11_CONFIG_H
#include <media/v4l2-config_rockchip.h>
#define CIFISP_MODULE_MAX 18
/* ISP Other module ID */
#define CIFISP_DPCC_ID 0
#define CIFISP_BLS_ID 1
#define CIFISP_SDG_ID 2
#define CIFISP_LSC_ID 3
#define CIFISP_AWB_GAIN_ID 4
#define CIFISP_FLT_ID 5
#define CIFISP_BDM_ID 6
#define CIFISP_CTK_ID 7
#define CIFISP_GOC_ID 8
#define CIFISP_CPROC_ID 9
#define CIFISP_IE_ID 10
#define CIFISP_WDR_ID 11
#define CIFISP_DPF_ID 12
#define CIFISP_DPF_STRENGTH_ID 13
/* ISP Meas module ID, It must be after other id */
#define CIFISP_MEAS_ID 14
#define CIFISP_AEC_ID (CIFISP_MEAS_ID + 0)
#define CIFISP_AFC_ID (CIFISP_MEAS_ID + 1)
#define CIFISP_AWB_ID (CIFISP_MEAS_ID + 2)
#define CIFISP_HST_ID (CIFISP_MEAS_ID + 3)
#define CIFISP_MODULE_DPCC (1 << CIFISP_DPCC_ID)
#define CIFISP_MODULE_BLS (1 << CIFISP_BLS_ID)
#define CIFISP_MODULE_SDG (1 << CIFISP_SDG_ID)
#define CIFISP_MODULE_HST (1 << CIFISP_HST_ID)
#define CIFISP_MODULE_LSC (1 << CIFISP_LSC_ID)
#define CIFISP_MODULE_AWB_GAIN (1 << CIFISP_AWB_GAIN_ID)
#define CIFISP_MODULE_FLT (1 << CIFISP_FLT_ID)
#define CIFISP_MODULE_BDM (1 << CIFISP_BDM_ID)
#define CIFISP_MODULE_CTK (1 << CIFISP_CTK_ID)
#define CIFISP_MODULE_GOC (1 << CIFISP_GOC_ID)
#define CIFISP_MODULE_CPROC (1 << CIFISP_CPROC_ID)
#define CIFISP_MODULE_AFC (1 << CIFISP_AFC_ID)
#define CIFISP_MODULE_AWB (1 << CIFISP_AWB_ID)
#define CIFISP_MODULE_IE (1 << CIFISP_IE_ID)
#define CIFISP_MODULE_AEC (1 << CIFISP_AEC_ID)
#define CIFISP_MODULE_WDR (1 << CIFISP_WDR_ID)
#define CIFISP_MODULE_DPF (1 << CIFISP_DPF_ID)
#define CIFISP_MODULE_DPF_STRENGTH (1 << CIFISP_DPF_STRENGTH_ID)
#define CIFISP_CTK_COEFF_MAX 0x100
#define CIFISP_CTK_OFFSET_MAX 0x800
#define CIFISP_AE_MEAN_MAX 25
#define CIFISP_HIST_BIN_N_MAX 16
#define CIFISP_AFM_MAX_WINDOWS 3
#define CIFISP_DEGAMMA_CURVE_SIZE 17
#define CIFISP_BDM_MAX_TH 0xFF
/* maximum value for horizontal start address */
#define CIFISP_BLS_START_H_MAX (0x00000FFF)
/* maximum value for horizontal stop address */
#define CIFISP_BLS_STOP_H_MAX (0x00000FFF)
/* maximum value for vertical start address */
#define CIFISP_BLS_START_V_MAX (0x00000FFF)
/* maximum value for vertical stop address */
#define CIFISP_BLS_STOP_V_MAX (0x00000FFF)
/* maximum is 2^18 = 262144*/
#define CIFISP_BLS_SAMPLES_MAX (0x00000012)
/* maximum value for fixed black level */
#define CIFISP_BLS_FIX_SUB_MAX (0x00000FFF)
/* minimum value for fixed black level */
#define CIFISP_BLS_FIX_SUB_MIN (0xFFFFF000)
/* 13 bit range (signed)*/
#define CIFISP_BLS_FIX_MASK (0x00001FFF)
/* AWB */
#define CIFISP_AWB_MAX_GRID 1
#define CIFISP_AWB_MAX_FRAMES 7
/* Gamma out*/
/* Maximum number of color samples supported */
#define CIFISP_GAMMA_OUT_MAX_SAMPLES 17
/* LSC */
#define CIFISP_LSC_GRAD_TBL_SIZE 8
#define CIFISP_LSC_SIZE_TBL_SIZE 8
/*
* The following matches the tuning process,
* not the max capabilities of the chip.
*/
#define CIFISP_LSC_DATA_TBL_SIZE 289
/* HIST */
#define CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 25
/* DPCC */
#define CIFISP_DPCC_METHODS_MAX (3)
/* DPF */
#define CIFISP_DPF_MAX_NLF_COEFFS 17
#define CIFISP_DPF_MAX_SPATIAL_COEFFS 6
#define CIFISP_STAT_AWB BIT(0)
#define CIFISP_STAT_AUTOEXP BIT(1)
#define CIFISP_STAT_AFM_FIN BIT(2)
#define CIFISP_STAT_HIST BIT(3)
enum cifisp_histogram_mode {
CIFISP_HISTOGRAM_MODE_DISABLE = 0,
CIFISP_HISTOGRAM_MODE_RGB_COMBINED = 1,
CIFISP_HISTOGRAM_MODE_R_HISTOGRAM = 2,
CIFISP_HISTOGRAM_MODE_G_HISTOGRAM = 3,
CIFISP_HISTOGRAM_MODE_B_HISTOGRAM = 4,
CIFISP_HISTOGRAM_MODE_Y_HISTOGRAM = 5
};
enum cifisp_exp_ctrl_autostop {
CIFISP_EXP_CTRL_AUTOSTOP_0 = 0,
CIFISP_EXP_CTRL_AUTOSTOP_1 = 1
};
enum cifisp_exp_meas_mode {
/* < Y = 16 + 0.25R + 0.5G + 0.1094B */
CIFISP_EXP_MEASURING_MODE_0 = 0,
/* < Y = (R + G + B) x (85/256) */
CIFISP_EXP_MEASURING_MODE_1 = 1,
};
struct cifisp_window {
unsigned short h_offs;
unsigned short v_offs;
unsigned short h_size;
unsigned short v_size;
};
enum cifisp_awb_mode_type {
CIFISP_AWB_MODE_MANUAL = 0,
CIFISP_AWB_MODE_RGB = 1,
CIFISP_AWB_MODE_YCBCR = 2
};
enum cifisp_bls_win_enable {
ISP_BLS_CTRL_WINDOW_ENABLE_0 = 0,
ISP_BLS_CTRL_WINDOW_ENABLE_1 = 1,
ISP_BLS_CTRL_WINDOW_ENABLE_2 = 2,
ISP_BLS_CTRL_WINDOW_ENABLE_3 = 3
};
enum cifisp_flt_mode {
CIFISP_FLT_STATIC_MODE,
CIFISP_FLT_DYNAMIC_MODE
};
struct cifisp_awb_meas {
unsigned int cnt;
unsigned char mean_y;
unsigned char mean_cb;
unsigned char mean_cr;
unsigned short mean_r;
unsigned short mean_b;
unsigned short mean_g;
};
struct cifisp_awb_stat {
struct cifisp_awb_meas awb_mean[CIFISP_AWB_MAX_GRID];
};
struct cifisp_hist_stat {
unsigned int hist_bins[CIFISP_HIST_BIN_N_MAX];
};
/*! BLS mean measured values */
struct cifisp_bls_meas_val {
/*! Mean measured value for Bayer pattern R.*/
unsigned short meas_r;
/*! Mean measured value for Bayer pattern Gr.*/
unsigned short meas_gr;
/*! Mean measured value for Bayer pattern Gb.*/
unsigned short meas_gb;
/*! Mean measured value for Bayer pattern B.*/
unsigned short meas_b;
};
/*
* BLS fixed subtraction values. The values will be subtracted from the sensor
* values. Therefore a negative value means addition instead of subtraction!
*/
struct cifisp_bls_fixed_val {
/*! Fixed (signed!) subtraction value for Bayer pattern R. */
signed short r;
/*! Fixed (signed!) subtraction value for Bayer pattern Gr. */
signed short gr;
/*! Fixed (signed!) subtraction value for Bayer pattern Gb. */
signed short gb;
/*! Fixed (signed!) subtraction value for Bayer pattern B. */
signed short b;
};
/* Configuration used by black level subtraction */
struct cifisp_bls_config {
/*
* Automatic mode activated means that the measured values
* are subtracted.Otherwise the fixed subtraction
* values will be subtracted.
*/
bool enable_auto;
unsigned char en_windows;
struct cifisp_window bls_window1; /* < Measurement window 1. */
struct cifisp_window bls_window2; /* !< Measurement window 2 */
/*
* Set amount of measured pixels for each Bayer position
* (A, B,C and D) to 2^bls_samples.
*/
unsigned char bls_samples;
/* !< Fixed subtraction values. */
struct cifisp_bls_fixed_val fixed_val;
};
struct cifisp_ae_stat {
unsigned char exp_mean[CIFISP_AE_MEAN_MAX];
struct cifisp_bls_meas_val bls_val; /* available wit exposure results */
};
struct cifisp_af_meas_val {
unsigned int sum;
unsigned int lum;
};
struct cifisp_af_stat {
struct cifisp_af_meas_val window[CIFISP_AFM_MAX_WINDOWS];
};
enum cifisp_vcm_val {
CIFISP_VCM_INVAL = -1,
CIFISP_VCM_MOVE_START = 0,
CIFISP_VCM_MOVE_RUNNING = 1,
CIFISP_VCM_MOVE_END = 2
};
struct cifisp_vcm_tim {
struct timeval vcm_start_t;
struct timeval vcm_end_t;
};
struct cifisp_subdev_stat {
struct cifisp_vcm_tim vcm;
};
struct cifisp_stat {
struct cifisp_awb_stat awb;
struct cifisp_ae_stat ae;
struct cifisp_af_stat af;
struct cifisp_hist_stat hist;
};
struct cifisp_stat_buffer {
unsigned int meas_type;
struct cifisp_stat params;
struct isp_supplemental_sensor_mode_data sensor_mode;
struct cifisp_subdev_stat subdev_stat;
struct timeval vs_t;
struct timeval fi_t;
};
struct cifisp_dpcc_methods_config {
unsigned int method;
unsigned int line_thresh;
unsigned int line_mad_fac;
unsigned int pg_fac;
unsigned int rnd_thresh;
unsigned int rg_fac;
};
struct cifisp_dpcc_config {
unsigned int mode;
unsigned int output_mode;
unsigned int set_use;
struct cifisp_dpcc_methods_config methods[CIFISP_DPCC_METHODS_MAX];
unsigned int ro_limits;
unsigned int rnd_offs;
};
struct cifisp_gamma_corr_curve {
unsigned short gamma_y[CIFISP_DEGAMMA_CURVE_SIZE];
};
struct cifisp_gamma_curve_x_axis_pnts {
unsigned int gamma_dx0;
unsigned int gamma_dx1;
};
/* Configuration used by sensor degamma */
struct cifisp_sdg_config {
struct cifisp_gamma_corr_curve curve_r;
struct cifisp_gamma_corr_curve curve_g;
struct cifisp_gamma_corr_curve curve_b;
struct cifisp_gamma_curve_x_axis_pnts xa_pnts;
};
/* Configuration used by Lens shading correction */
struct cifisp_lsc_config {
unsigned int r_data_tbl[CIFISP_LSC_DATA_TBL_SIZE];
unsigned int gr_data_tbl[CIFISP_LSC_DATA_TBL_SIZE];
unsigned int gb_data_tbl[CIFISP_LSC_DATA_TBL_SIZE];
unsigned int b_data_tbl[CIFISP_LSC_DATA_TBL_SIZE];
unsigned int x_grad_tbl[CIFISP_LSC_GRAD_TBL_SIZE];
unsigned int y_grad_tbl[CIFISP_LSC_GRAD_TBL_SIZE];
unsigned int x_size_tbl[CIFISP_LSC_SIZE_TBL_SIZE];
unsigned int y_size_tbl[CIFISP_LSC_SIZE_TBL_SIZE];
unsigned short config_width;
unsigned short config_height;
};
struct cifisp_ie_config {
enum v4l2_colorfx effect;
unsigned short color_sel;
/* 3x3 Matrix Coefficients for Emboss Effect 1 */
unsigned short eff_mat_1;
/* 3x3 Matrix Coefficients for Emboss Effect 2 */
unsigned short eff_mat_2;
/* 3x3 Matrix Coefficients for Emboss 3/Sketch 1 */
unsigned short eff_mat_3;
/* 3x3 Matrix Coefficients for Sketch Effect 2 */
unsigned short eff_mat_4;
/* 3x3 Matrix Coefficients for Sketch Effect 3 */
unsigned short eff_mat_5;
/* Chrominance increment values of tint (used for sepia effect) */
unsigned short eff_tint;
};
/* Configuration used by auto white balance */
struct cifisp_awb_meas_config {
/*
* white balance measurement window (in pixels)
* Note: currently the h and v offsets are mapped to grid offsets
*/
struct cifisp_window awb_wnd;
enum cifisp_awb_mode_type awb_mode;
/*
* only pixels values < max_y contribute to awb measurement
* (set to 0 to disable this feature)
*/
unsigned char max_y;
/* only pixels values > min_y contribute to awb measurement */
unsigned char min_y;
/*
* Chrominance sum maximum value, only consider pixels with Cb+Cr
* smaller than threshold for awb measurements
*/
unsigned char max_csum;
/*
* Chrominance minimum value, only consider pixels with Cb/Cr
* each greater than threshold value for awb measurements
*/
unsigned char min_c;
/*
* number of frames - 1 used for mean value calculation
* (ucFrames=0 means 1 Frame)
*/
unsigned char frames;
/* reference Cr value for AWB regulation, target for AWB */
unsigned char awb_ref_cr;
/* reference Cb value for AWB regulation, target for AWB */
unsigned char awb_ref_cb;
bool enable_ymax_cmp;
};
struct cifisp_awb_gain_config {
unsigned short gain_red;
unsigned short gain_green_r;
unsigned short gain_blue;
unsigned short gain_green_b;
};
/* Configuration used by ISP filtering */
struct cifisp_flt_config {
enum cifisp_flt_mode mode; /* ISP_FILT_MODE register fields */
unsigned char grn_stage1; /* ISP_FILT_MODE register fields */
unsigned char chr_h_mode; /* ISP_FILT_MODE register fields */
unsigned char chr_v_mode; /* ISP_FILT_MODE register fields */
unsigned int thresh_bl0;
unsigned int thresh_bl1;
unsigned int thresh_sh0;
unsigned int thresh_sh1;
unsigned int lum_weight;
unsigned int fac_sh1;
unsigned int fac_sh0;
unsigned int fac_mid;
unsigned int fac_bl0;
unsigned int fac_bl1;
};
/* Configuration used by Bayer DeMosaic */
struct cifisp_bdm_config {
unsigned char demosaic_th;
};
/* Configuration used by Cross Talk correction */
struct cifisp_ctk_config {
unsigned short coeff0;
unsigned short coeff1;
unsigned short coeff2;
unsigned short coeff3;
unsigned short coeff4;
unsigned short coeff5;
unsigned short coeff6;
unsigned short coeff7;
unsigned short coeff8;
/* offset for the crosstalk correction matrix */
unsigned short ct_offset_r;
unsigned short ct_offset_g;
unsigned short ct_offset_b;
};
enum cifisp_goc_mode {
CIFISP_GOC_MODE_LOGARITHMIC,
CIFISP_GOC_MODE_EQUIDISTANT
};
/* Configuration used by Gamma Out correction */
struct cifisp_goc_config {
enum cifisp_goc_mode mode;
unsigned short gamma_y[CIFISP_GAMMA_OUT_MAX_SAMPLES];
};
/* CCM (Color Correction) */
struct cifisp_cproc_config {
unsigned char c_out_range;
unsigned char y_in_range;
unsigned char y_out_range;
unsigned char contrast;
unsigned char brightness;
unsigned char sat;
unsigned char hue;
};
/* Configuration used by Histogram */
struct cifisp_hst_config {
enum cifisp_histogram_mode mode;
unsigned char histogram_predivider;
struct cifisp_window meas_window;
unsigned char hist_weight[CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE];
};
/* Configuration used by Auto Exposure Control */
struct cifisp_aec_config {
enum cifisp_exp_meas_mode mode;
enum cifisp_exp_ctrl_autostop autostop;
struct cifisp_window meas_window;
};
struct cifisp_afc_config {
unsigned char num_afm_win; /* max CIFISP_AFM_MAX_WINDOWS */
struct cifisp_window afm_win[CIFISP_AFM_MAX_WINDOWS];
unsigned int thres;
unsigned int var_shift;
};
enum cifisp_dpf_gain_usage {
/* don't use any gains in preprocessing stage */
CIFISP_DPF_GAIN_USAGE_DISABLED = 1,
/* use only the noise function gains from registers DPF_NF_GAIN_R, ... */
CIFISP_DPF_GAIN_USAGE_NF_GAINS = 2,
/* use only the gains from LSC module */
CIFISP_DPF_GAIN_USAGE_LSC_GAINS = 3,
/* use the moise function gains and the gains from LSC module */
CIFISP_DPF_GAIN_USAGE_NF_LSC_GAINS = 4,
/* use only the gains from AWB module */
CIFISP_DPF_GAIN_USAGE_AWB_GAINS = 5,
/* use the gains from AWB and LSC module */
CIFISP_DPF_GAIN_USAGE_AWB_LSC_GAINS = 6,
/* upper border (only for an internal evaluation) */
CIFISP_DPF_GAIN_USAGE_MAX
};
enum cifisp_dpf_rb_filtersize {
/* red and blue filter kernel size 13x9 (means 7x5 active pixel) */
CIFISP_DPF_RB_FILTERSIZE_13x9 = 0,
/* red and blue filter kernel size 9x9 (means 5x5 active pixel) */
CIFISP_DPF_RB_FILTERSIZE_9x9 = 1,
};
enum cifisp_dpf_nll_scale_mode {
/* use a linear scaling */
CIFISP_NLL_SCALE_LINEAR = 0,
/* use a logarithmic scaling */
CIFISP_NLL_SCALE_LOGARITHMIC = 1,
};
struct cifisp_dpf_nll {
unsigned short coeff[CIFISP_DPF_MAX_NLF_COEFFS];
enum cifisp_dpf_nll_scale_mode scale_mode;
};
struct cifisp_dpf_rb_flt {
enum cifisp_dpf_rb_filtersize fltsize;
unsigned char spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS];
bool r_enable;
bool b_enable;
};
struct cifisp_dpf_g_flt {
unsigned char spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS];
bool gr_enable;
bool gb_enable;
};
struct cifisp_dpf_gain {
enum cifisp_dpf_gain_usage mode;
unsigned short nf_r_gain;
unsigned short nf_b_gain;
unsigned short nf_gr_gain;
unsigned short nf_gb_gain;
};
struct cifisp_dpf_config {
struct cifisp_dpf_gain gain;
struct cifisp_dpf_g_flt g_flt;
struct cifisp_dpf_rb_flt rb_flt;
struct cifisp_dpf_nll nll;
};
struct cifisp_dpf_strength_config {
unsigned char r;
unsigned char g;
unsigned char b;
};
struct cifisp_last_capture_config {
struct cifisp_cproc_config cproc;
struct cifisp_goc_config goc;
struct cifisp_ctk_config ctk;
struct cifisp_bdm_config bdm;
struct cifisp_flt_config flt;
struct cifisp_awb_gain_config awb_gain;
struct cifisp_awb_meas_config awb_meas;
struct cifisp_lsc_config lsc;
struct cifisp_sdg_config sdg;
struct cifisp_bls_config bls;
};
struct cifisp_isp_other_cfg {
unsigned int s_frame_id;/* Set isp hardware frame id */
unsigned int module_ens;
struct cifisp_dpcc_config dpcc_config;
struct cifisp_bls_config bls_config;
struct cifisp_sdg_config sdg_config;
struct cifisp_lsc_config lsc_config;
struct cifisp_awb_gain_config awb_gain_config;
struct cifisp_flt_config flt_config;
struct cifisp_bdm_config bdm_config;
struct cifisp_ctk_config ctk_config;
struct cifisp_goc_config goc_config;
struct cifisp_cproc_config cproc_config;
struct cifisp_ie_config ie_config;
struct cifisp_dpf_config dpf_config;
struct cifisp_dpf_strength_config dpf_strength_config;
};
struct cifisp_isp_meas_cfg {
unsigned int s_frame_id; /* Set isp hardware frame id */
unsigned int module_ens;
struct cifisp_awb_meas_config awb_meas_config;
struct cifisp_hst_config hst_config;
struct cifisp_aec_config aec_config;
struct cifisp_afc_config afc_config;
};
struct cifisp_isp_metadata {
struct cifisp_isp_other_cfg other_cfg;
struct cifisp_isp_meas_cfg meas_cfg;
struct cifisp_stat_buffer meas_stat;
};
#endif

140
include/media/rk-isp10-ioctl.h
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@ -1,140 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#include <linux/v4l2-controls.h>
#include <media/rk-isp10-config.h>
#include <media/v4l2-controls_rockchip.h>
#ifndef _RK_ISP10_IOCTL_H
#define _RK_ISP10_IOCTL_H
/* Private IOCTLs */
/* DPCC */
#define CIFISP_IOC_G_DPCC \
_IOR('v', BASE_VIDIOC_PRIVATE + 0, struct cifisp_dpcc_config)
#define CIFISP_IOC_S_DPCC \
_IOW('v', BASE_VIDIOC_PRIVATE + 1, struct cifisp_dpcc_config)
/* Black Level Subtraction */
#define CIFISP_IOC_G_BLS \
_IOR('v', BASE_VIDIOC_PRIVATE + 2, struct cifisp_bls_config)
#define CIFISP_IOC_S_BLS \
_IOW('v', BASE_VIDIOC_PRIVATE + 3, struct cifisp_bls_config)
/* Sensor DeGamma */
#define CIFISP_IOC_G_SDG \
_IOR('v', BASE_VIDIOC_PRIVATE + 4, struct cifisp_sdg_config)
#define CIFISP_IOC_S_SDG \
_IOW('v', BASE_VIDIOC_PRIVATE + 5, struct cifisp_sdg_config)
/* Lens Shading Correction */
#define CIFISP_IOC_G_LSC \
_IOR('v', BASE_VIDIOC_PRIVATE + 6, struct cifisp_lsc_config)
#define CIFISP_IOC_S_LSC \
_IOW('v', BASE_VIDIOC_PRIVATE + 7, struct cifisp_lsc_config)
/* Auto White Balance */
#define CIFISP_IOC_G_AWB_MEAS \
_IOR('v', BASE_VIDIOC_PRIVATE + 8, struct cifisp_awb_meas_config)
#define CIFISP_IOC_S_AWB_MEAS \
_IOW('v', BASE_VIDIOC_PRIVATE + 9, struct cifisp_awb_meas_config)
/* ISP Filtering( Sharpening & Noise reduction */
#define CIFISP_IOC_G_FLT \
_IOR('v', BASE_VIDIOC_PRIVATE + 10, struct cifisp_flt_config)
#define CIFISP_IOC_S_FLT \
_IOW('v', BASE_VIDIOC_PRIVATE + 11, struct cifisp_flt_config)
/* Bayer Demosaic */
#define CIFISP_IOC_G_BDM \
_IOR('v', BASE_VIDIOC_PRIVATE + 12, struct cifisp_bdm_config)
#define CIFISP_IOC_S_BDM \
_IOW('v', BASE_VIDIOC_PRIVATE + 13, struct cifisp_bdm_config)
/* Cross Talk correction */
#define CIFISP_IOC_G_CTK \
_IOR('v', BASE_VIDIOC_PRIVATE + 14, struct cifisp_ctk_config)
#define CIFISP_IOC_S_CTK \
_IOW('v', BASE_VIDIOC_PRIVATE + 15, struct cifisp_ctk_config)
/* Gamma Out Correction */
#define CIFISP_IOC_G_GOC \
_IOR('v', BASE_VIDIOC_PRIVATE + 16, struct cifisp_goc_config)
#define CIFISP_IOC_S_GOC \
_IOW('v', BASE_VIDIOC_PRIVATE + 17, struct cifisp_goc_config)
/* Histogram Measurement */
#define CIFISP_IOC_G_HST \
_IOR('v', BASE_VIDIOC_PRIVATE + 18, struct cifisp_hst_config)
#define CIFISP_IOC_S_HST \
_IOW('v', BASE_VIDIOC_PRIVATE + 19, struct cifisp_hst_config)
/* Auto Exposure Measurements */
#define CIFISP_IOC_G_AEC \
_IOR('v', BASE_VIDIOC_PRIVATE + 20, struct cifisp_aec_config)
#define CIFISP_IOC_S_AEC \
_IOW('v', BASE_VIDIOC_PRIVATE + 21, struct cifisp_aec_config)
#define CIFISP_IOC_G_BPL \
_IOR('v', BASE_VIDIOC_PRIVATE + 22, struct cifisp_aec_config)
#define CIFISP_IOC_G_AWB_GAIN \
_IOR('v', BASE_VIDIOC_PRIVATE + 23, struct cifisp_awb_gain_config)
#define CIFISP_IOC_S_AWB_GAIN \
_IOW('v', BASE_VIDIOC_PRIVATE + 24, struct cifisp_awb_gain_config)
#define CIFISP_IOC_G_CPROC \
_IOR('v', BASE_VIDIOC_PRIVATE + 25, struct cifisp_cproc_config)
#define CIFISP_IOC_S_CPROC \
_IOW('v', BASE_VIDIOC_PRIVATE + 26, struct cifisp_cproc_config)
#define CIFISP_IOC_G_AFC \
_IOR('v', BASE_VIDIOC_PRIVATE + 27, struct cifisp_afc_config)
#define CIFISP_IOC_S_AFC \
_IOW('v', BASE_VIDIOC_PRIVATE + 28, struct cifisp_afc_config)
#define CIFISP_IOC_G_IE \
_IOR('v', BASE_VIDIOC_PRIVATE + 29, struct cifisp_ie_config)
#define CIFISP_IOC_S_IE \
_IOW('v', BASE_VIDIOC_PRIVATE + 30, struct cifisp_ie_config)
#define CIFISP_IOC_G_DPF \
_IOR('v', BASE_VIDIOC_PRIVATE + 31, struct cifisp_dpf_config)
#define CIFISP_IOC_S_DPF \
_IOW('v', BASE_VIDIOC_PRIVATE + 32, struct cifisp_dpf_config)
#define CIFISP_IOC_G_DPF_STRENGTH \
_IOR('v', BASE_VIDIOC_PRIVATE + 33, struct cifisp_dpf_strength_config)
#define CIFISP_IOC_S_DPF_STRENGTH \
_IOW('v', BASE_VIDIOC_PRIVATE + 34, struct cifisp_dpf_strength_config)
#define CIFISP_IOC_G_LAST_CONFIG \
_IOR('v', BASE_VIDIOC_PRIVATE + 35, struct cifisp_last_capture_config)
/* CIF-ISP Private control IDs */
#define V4L2_CID_CIFISP_DPCC (V4L2_CID_PRIVATE_BASE + CIFISP_DPCC_ID)
#define V4L2_CID_CIFISP_BLS (V4L2_CID_PRIVATE_BASE + CIFISP_BLS_ID)
#define V4L2_CID_CIFISP_SDG (V4L2_CID_PRIVATE_BASE + CIFISP_SDG_ID)
#define V4L2_CID_CIFISP_HST (V4L2_CID_PRIVATE_BASE + CIFISP_HST_ID)
#define V4L2_CID_CIFISP_LSC (V4L2_CID_PRIVATE_BASE + CIFISP_LSC_ID)
#define V4L2_CID_CIFISP_AWB_GAIN (V4L2_CID_PRIVATE_BASE + CIFISP_AWB_GAIN_ID)
#define V4L2_CID_CIFISP_FLT (V4L2_CID_PRIVATE_BASE + CIFISP_FLT_ID)
#define V4L2_CID_CIFISP_BDM (V4L2_CID_PRIVATE_BASE + CIFISP_BDM_ID)
#define V4L2_CID_CIFISP_CTK (V4L2_CID_PRIVATE_BASE + CIFISP_CTK_ID)
#define V4L2_CID_CIFISP_GOC (V4L2_CID_PRIVATE_BASE + CIFISP_GOC_ID)
#define V4L2_CID_CIFISP_CPROC (V4L2_CID_PRIVATE_BASE + CIFISP_CPROC_ID)
#define V4L2_CID_CIFISP_AFC (V4L2_CID_PRIVATE_BASE + CIFISP_AFC_ID)
#define V4L2_CID_CIFISP_AWB_MEAS (V4L2_CID_PRIVATE_BASE + CIFISP_AWB_ID)
#define V4L2_CID_CIFISP_IE (V4L2_CID_PRIVATE_BASE + CIFISP_IE_ID)
#define V4L2_CID_CIFISP_AEC (V4L2_CID_PRIVATE_BASE + CIFISP_AEC_ID)
#define V4L2_CID_CIFISP_DPF (V4L2_CID_PRIVATE_BASE + CIFISP_DPF_ID)
/* Camera Sensors' running modes */
#define CI_MODE_PREVIEW 0x8000
#define CI_MODE_VIDEO 0x4000
#define CI_MODE_STILL_CAPTURE 0x2000
#define CI_MODE_CONTINUOUS 0x1000
#define CI_MODE_NONE 0x0000
/* Kernel API */
void cif_isp11_v4l2_s_frame_interval(
unsigned int numerator,
unsigned int denominator);
int cif_isp11_v4l2_g_frame_interval(
unsigned int *numerator,
unsigned int *denominator);
#endif

127
include/media/v4l2-config_rockchip.h
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@ -1,127 +0,0 @@
/*
*************************************************************************
* Rockchip driver for CIF ISP 1.0
* (Based on Intel driver for sofiaxxx)
*
* Copyright (C) 2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*************************************************************************
*/
#ifndef _V4L2_CONFIG_ROCKCHIP_H
#define _V4L2_CONFIG_ROCKCHIP_H
#define CAMERA_STRLEN 32
#define CAMERA_METADATA_LEN (2 * PAGE_SIZE)
#define VALID_FR_EXP_T_INDEX 0
#define VALID_FR_EXP_G_INDEX 1
#define SENSOR_CONFIG_NUM 4
#define SENSOR_READ_MODE 0
#define SENSOR_WRITE_MODE 1
/* Sensor resolution specific data for AE calculation.*/
struct isp_supplemental_sensor_mode_data {
unsigned int coarse_integration_time_min;
unsigned int coarse_integration_time_max_margin;
unsigned int fine_integration_time_min;
unsigned int fine_integration_time_max_margin;
unsigned int frame_length_lines;
unsigned int line_length_pck;
unsigned int vt_pix_clk_freq_hz;
unsigned int crop_horizontal_start; /* Sensor crop start cord. (x0,y0)*/
unsigned int crop_vertical_start;
unsigned int crop_horizontal_end; /* Sensor crop end cord. (x1,y1)*/
unsigned int crop_vertical_end;
unsigned int sensor_output_width; /* input size to ISP */
unsigned int sensor_output_height;
unsigned int isp_input_horizontal_start; /* cif isp input */
unsigned int isp_input_vertical_start;
unsigned int isp_input_width;
unsigned int isp_input_height;
unsigned int isp_output_width; /* cif isp output */
unsigned int isp_output_height;
unsigned char binning_factor_x; /* horizontal binning factor used */
unsigned char binning_factor_y; /* vertical binning factor used */
/*
*0: Exposure time valid fileds;
*1: Exposure gain valid fileds;
*(2 fileds == 1 frames)
*/
unsigned char exposure_valid_frame[2];
int exp_time;
unsigned short gain;
unsigned char max_exp_gain_h;
unsigned char max_exp_gain_l;
};
struct camera_module_info_s {
char sensor_name[CAMERA_STRLEN];
char module_name[CAMERA_STRLEN];
char len_name[CAMERA_STRLEN];
char fov_h[CAMERA_STRLEN];
char fov_v[CAMERA_STRLEN];
char focal_length[CAMERA_STRLEN];
char focus_distance[CAMERA_STRLEN];
int facing;
int orientation;
bool iq_mirror;
bool iq_flip;
int flash_support;
int flash_exp_percent;
int af_support;
};
struct sensor_resolution_s {
unsigned short width;
unsigned short height;
};
struct sensor_config_info_s {
unsigned char config_num;
unsigned char sensor_fmt[SENSOR_CONFIG_NUM];
struct sensor_resolution_s reso[SENSOR_CONFIG_NUM];
};
struct sensor_reg_rw_s {
unsigned char reg_access_mode;
unsigned char reg_addr_len;
unsigned char reg_data_len;
unsigned short addr;
unsigned short data;
};
struct flash_timeinfo_s {
struct timeval preflash_start_t;
struct timeval preflash_end_t;
struct timeval mainflash_start_t;
struct timeval mainflash_end_t;
int flash_turn_on_time;
int flash_on_timeout;
};
struct frame_timeinfo_s {
struct timeval vs_t;
struct timeval fi_t;
};
struct sensor_metadata_s {
unsigned int exp_time;
unsigned int gain;
};
struct v4l2_buffer_metadata_s {
unsigned int frame_id;
struct frame_timeinfo_s frame_t;
struct flash_timeinfo_s flash_t;
struct sensor_metadata_s sensor;
unsigned char isp[CAMERA_METADATA_LEN - 512];
};
#endif

15
include/media/v4l2-controls_rockchip.h
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@ -18,23 +18,8 @@
#define _V4L2_CONTROLS_ROCKCHIP_H
#include <linux/videodev2.h>
#include <media/v4l2-config_rockchip.h>
#define RK_VIDIOC_CAMERA_MODULEINFO \
_IOWR('v', BASE_VIDIOC_PRIVATE + 10, struct camera_module_info_s)
#define RK_VIDIOC_SENSOR_MODE_DATA \
_IOR('v', BASE_VIDIOC_PRIVATE, struct isp_supplemental_sensor_mode_data)
#define RK_VIDIOC_SENSOR_CONFIGINFO \
_IOR('v', BASE_VIDIOC_PRIVATE + 1, struct sensor_config_info_s)
#define RK_VIDIOC_SENSOR_REG_ACCESS \
_IOWR('v', BASE_VIDIOC_PRIVATE + 2, struct sensor_reg_rw_s)
#define V4L2_CID_USER_RK_BASE (V4L2_CID_USER_BASE + 0x1080)
#define RK_V4L2_CID_VBLANKING (V4L2_CID_USER_RK_BASE + 1)
#define RK_V4L2_CID_GAIN_PERCENT (V4L2_CID_USER_RK_BASE + 2)
#define RK_V4L2_CID_AUTO_FPS (V4L2_CID_USER_RK_BASE + 3)
#define RK_V4L2_CID_VTS (V4L2_CID_USER_RK_BASE + 4)
#define RK_V4L2_CID_CLS_EXP (V4L2_CID_USER_RK_BASE + 5)
#define RK_V4L2_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_RK_BASE + 0x100)
#define RK_V4L2_CID_AUDIO_PRESENT (V4L2_CID_USER_RK_BASE + 0x101)