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perf mem: Add support for printing PERF_MEM_LVLNUM_L0

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Add support for printing PERF_MEM_LVLNUM_L0 in perf mem report.

The L0 cache is newly added a small piece of cache which is the closest,
lowest-latency memory cache tied directly to the execution pipeline.

The table "Table 9-4. Data Source Field Encodings for Panther Cove and
Coyote Cove Microarchitectures" in the ISE doc chapter "9.2.1 Panther
Cove and Coyote Cove Microarchitectures Memory Auxiliary Field
Layout"[1] indicates the code "01H" means the "L0 Hit - Minimal latency
core cache hit. This request was satisfied by the L0 data cache."

[1]: https://www.intel.com/content/www/us/en/content-details/922690/intel-architecture-instruction-set-extensions-programming-reference.html

Assisted-by: Sashiko:gemini-3.1-pro-preview
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Reviewed-by: Namhyung Kim <namhyung@kernel.org>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Co-developed-by: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Dapeng Mi 2026-09-23 12:08:59 -05:00 committed by Arnaldo Carvalho de Melo
parent 06d5ce78e4
commit f6659329a4
4 changed files with 8 additions and 1 deletions
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2
tools/perf/Documentation/perf-record.txt
View File

@ -212,7 +212,7 @@ OPTIONS
The <value> can be one of:
<number> (for any term)
na, load, store, pfetch, exec (for mem_op)
l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl)
l0, l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl)
na, none, hit, miss, hitm, fwd, peer (for mem_snoop)
remote (for mem_remote)
na, locked (for mem_locked)

1
tools/perf/util/bpf-filter.l
View File

@ -131,6 +131,7 @@ store { return constant(PERF_MEM_OP_STORE); }
pfetch { return constant(PERF_MEM_OP_PFETCH); }
exec { return constant(PERF_MEM_OP_EXEC); }
l0 { return constant(PERF_MEM_LVLNUM_L0); }
l1 { return constant(PERF_MEM_LVLNUM_L1); }
l2 { return constant(PERF_MEM_LVLNUM_L2); }
l3 { return constant(PERF_MEM_LVLNUM_L3); }

5
tools/perf/util/mem-events.c
View File

@ -391,6 +391,7 @@ static const char * const mem_lvlnum[] = {
[PERF_MEM_LVLNUM_L4] = "L4",
[PERF_MEM_LVLNUM_L2_MHB] = "L2 MHB",
[PERF_MEM_LVLNUM_MSC] = "Memory-side Cache",
[PERF_MEM_LVLNUM_L0] = "L0",
[PERF_MEM_LVLNUM_UNC] = "Uncached",
[PERF_MEM_LVLNUM_CXL] = "CXL",
[PERF_MEM_LVLNUM_IO] = "I/O",
@ -831,6 +832,8 @@ int mem_stat_index(const enum mem_stat_type mst, const u64 val)
}
case PERF_MEM_STAT_CACHE:
switch (src.mem_lvl_num) {
case PERF_MEM_LVLNUM_L0:
return MEM_STAT_CACHE_L0;
case PERF_MEM_LVLNUM_L1:
return MEM_STAT_CACHE_L1;
case PERF_MEM_LVLNUM_L2:
@ -915,6 +918,8 @@ const char *mem_stat_name(const enum mem_stat_type mst, const int idx)
}
case PERF_MEM_STAT_CACHE:
switch (idx) {
case MEM_STAT_CACHE_L0:
return "L0";
case MEM_STAT_CACHE_L1:
return "L1";
case MEM_STAT_CACHE_L2:

1
tools/perf/util/mem-events.h
View File

@ -109,6 +109,7 @@ enum mem_stat_op {
};
enum mem_stat_cache {
MEM_STAT_CACHE_L0,
MEM_STAT_CACHE_L1,
MEM_STAT_CACHE_L2,
MEM_STAT_CACHE_L3,