From f662fca3dc872fed4c9ab92def19305ac5a7ad2d Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 9 Jun 2026 22:34:05 +0530 Subject: [PATCH] arm64: dts: qcom: ipq5332: Move PHYs and PERST# to Root Port node Follow the new binding style by defining PHYs and PERST# (now RESET#) under the Root Port node. Avoid mixing styles and move these properties to the RP node. Reviewed-by: Dmitry Baryshkov Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260609-move_perst_to_rp-v2-1-6c731523d08c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 14 ++++++-------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 79ec77cfe552..7fcf632e289f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -36,9 +36,6 @@ &pcie0 { pinctrl-0 = <&pcie0_default>; pinctrl-names = "default"; - perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; - status = "okay"; }; @@ -46,13 +43,15 @@ &pcie0_phy { status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; +}; + &pcie1 { pinctrl-0 = <&pcie1_default>; pinctrl-names = "default"; - perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; - status = "okay"; }; @@ -60,6 +59,11 @@ &pcie1_phy { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; +}; + &tlmm { i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index fbc6c4d37fa3..74d9de8d7641 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -741,19 +741,18 @@ pcie1: pcie@18000000 { "aux", "ahb"; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>, <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -845,19 +844,18 @@ pcie0: pcie@20000000 { "aux", "ahb"; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>, <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges;