gpu: nova-core: Hopper/Blackwell: larger WPR2 (GSP) heap

The GSP-RM boot working memory portion of the WPR2 heap must be
larger on Hopper and later GPUs than on Turing, Ampere, and Ada.
Select the larger value for those generations.

Signed-off-by: John Hubbard <jhubbard@nvidia.com>
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Link: https://patch.msgid.link/20260602032111.224790-6-jhubbard@nvidia.com
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
This commit is contained in:
John Hubbard 2026-06-01 20:20:53 -07:00 committed by Alexandre Courbot
parent fcdd74aa8c
commit f66287cf15
2 changed files with 15 additions and 6 deletions

View File

@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
pub(crate) mod commands;
mod r570_144;
@ -29,7 +30,10 @@
use crate::{
fb::FbLayout,
firmware::gsp::GspFirmware,
gpu::Chipset,
gpu::{
Architecture,
Chipset, //
},
gsp::{
cmdq::Cmdq, //
GSP_PAGE_SIZE,
@ -106,11 +110,15 @@ enum GspFwHeapParams {}
impl GspFwHeapParams {
/// Returns the amount of GSP-RM heap memory used during GSP-RM boot and initialization (up to
/// and including the first client subdevice allocation).
fn base_rm_size(_chipset: Chipset) -> u64 {
// TODO: this needs to be updated to return the correct value for Hopper+ once support for
// them is added:
// u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100)
u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X)
fn base_rm_size(chipset: Chipset) -> u64 {
match chipset.arch() {
Architecture::Turing | Architecture::Ampere | Architecture::Ada => {
u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X)
}
Architecture::Hopper | Architecture::BlackwellGB10x | Architecture::BlackwellGB20x => {
u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100)
}
}
}
/// Returns the amount of heap memory required to support a single channel allocation.

View File

@ -37,6 +37,7 @@ fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2: u32 = 0;
pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL: u32 = 23068672;
pub const GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X: u32 = 8388608;
pub const GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100: u32 = 14680064;
pub const GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB: u32 = 98304;
pub const GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE: u32 = 100663296;
pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB: u32 = 64;