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ARM: dts: rk3036: remove the old rk3036 dts
The original rk3036.dtsi is suit for the kernel 3.10 develop, So I should remove or rename it with insteading of upstream dts. Change-Id: Ib45129573c5a6240a9f356be98186946a61b3f3f Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This commit is contained in:
Caesar Wang
parent
ff9877f38b
commit
f64d3866a8
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@ -1,787 +0,0 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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#include "rk3036-clocks.dtsi"
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#include "rk3036-pinctrl.dtsi"
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#include <dt-bindings/suspend/rockchip-pm.h>
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/ {
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compatible = "rockchip,rk3036";
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rockchip,sram = <&sram>;
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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lcdc = &lcdc;
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spi0 = &spi0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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};
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};
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gic: interrupt-controller@10139000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x10139000 0x1000>,
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<0x1013a000 0x1000>;
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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};
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cpu_axi_bus: cpu_axi_bus {
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compatible = "rockchip,cpu_axi_bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qos {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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core {
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reg = <0x1012a000 0x20>;
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rockchip,priority = <3 2>;
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};
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peri {
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reg = <0x1012c000 0x20>;
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};
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gpu {
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reg = <0x1012d000 0x20>;
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};
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vpu {
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reg = <0x1012e000 0x20>;
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};
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hevc {
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reg = <0x1012e080 0x20>;
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};
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vio {
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reg = <0x1012f000 0x20>;
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rockchip,priority = <3 3>;
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};
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};
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msch {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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msch@10128000 {
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reg = <0x10128000 0x40>;
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rockchip,read-latency = <0x80>;
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};
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};
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};
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sram: sram@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x2000>;
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map-exec;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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timer@20044000 {
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compatible = "rockchip,timer";
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reg = <0x20044000 0x20>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,broadcast = <1>;
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};
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watchdog: wdt@2004c000 {
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compatible = "rockchip,watch dog";
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reg = <0x2004c000 0x100>;
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clocks = <&clk_gates7 15>;
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clock-names = "pclk_wdt";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,irq = <1>;
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rockchip,timeout = <60>;
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rockchip,atboot = <1>;
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rockchip,debug = <0>;
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status = "disabled";
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus";
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interrupt-parent = <&gic>;
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ranges;
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pdma: pdma@20078000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20078000 0x4000>;
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clocks = <&clk_gates5 1>;
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clock-names = "apb_pclk";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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};
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};
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reset: reset@20000110{
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compatible = "rockchip,reset";
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reg = <0x20000110 0x24>;
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rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
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#reset-cells = <1>;
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};
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nandc: nandc@10500000 {
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compatible = "rockchip,rk-nandc";
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reg = <0x10500000 0x4000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
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nandc_id = <0>;
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clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
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clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
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};
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nandc0reg: nandc0@10500000 {
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compatible = "rockchip,rk-nandc";
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reg = <0x10500000 0x4000>;
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};
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spi0: spi@20074000 {
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compatible = "rockchip,rockchip-spi";
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reg = <0x20074000 0x1000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
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rockchip,spi-src-clk = <0>;
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num-cs = <2>;
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clocks =<&clk_spi0>, <&clk_gates2 9>;
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clock-names = "spi","pclk_spi0";
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dmas = <&pdma 8>, <&pdma 9>;
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#dma-cells = <2>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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uart0: serial@20060000 {
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compatible = "rockchip,serial";
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reg = <0x20060000 0x100>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&clk_uart0>, <&clk_gates8 0>;
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clock-names = "sclk_uart", "pclk_uart";
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reg-shift = <2>;
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reg-io-width = <4>;
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dmas = <&pdma 2>, <&pdma 3>;
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#dma-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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status = "disabled";
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};
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uart1: serial@20064000 {
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compatible = "rockchip,serial";
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reg = <0x20064000 0x100>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&clk_uart1>, <&clk_gates8 1>;
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clock-names = "sclk_uart", "pclk_uart";
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reg-shift = <2>;
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reg-io-width = <4>;
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dmas = <&pdma 4>, <&pdma 5>;
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#dma-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "disabled";
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};
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uart2: serial@20068000 {
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compatible = "rockchip,serial";
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reg = <0x20068000 0x100>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&clk_uart2>, <&clk_gates8 2>;
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clock-names = "sclk_uart", "pclk_uart";
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reg-shift = <2>;
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reg-io-width = <4>;
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dmas = <&pdma 6>, <&pdma 7>;
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#dma-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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status = "disabled";
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,signal-irq = <106>;
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rockchip,wake-irq = <0>;
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status = "disabled";
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};
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clocks-init{
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compatible = "rockchip,clocks-init";
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rockchip,clocks-init-parent =
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<&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
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<&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
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<&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
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<&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
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<&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
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rockchip,clocks-init-rate =
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<&clk_core 1200000000>, <&clk_gpll 1188000000>,
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<&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
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<&pclk_cpu_pre 75000000>, <&aclk_peri_pre 150000000>,
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<&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
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<&clk_gpu 400000000>, <&aclk_vio_pre 300000000>,
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<&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
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<&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
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<&clk_mac_ref_div 25000000>;
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/* rockchip,clocks-uboot-has-init =
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<&aclk_vio1>;*/
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};
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clocks-enable {
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compatible = "rockchip,clocks-enable";
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clocks =
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/*PD_CORE*/
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<&clk_gates0 0>, <&clk_gates0 7>,
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/*PD_CPU*/
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<&clk_gates0 3>, <&clk_gates0 4>,
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<&clk_gates0 5>,
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/*TIMER*/
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<&clk_gates1 0>, <&clk_gates1 1>,
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<&clk_gates2 4>, <&clk_gates2 5>,
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/*PD_PERI*/
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<&clk_gates2 0>, <&hclk_peri_pre>,
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<&pclk_peri_pre>, <&clk_gates2 1>,
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/*aclk_cpu_pre*/
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<&clk_gates4 12>,/*aclk_intmem*/
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<&clk_gates4 10>,/*aclk_strc_sys*/
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/*hclk_cpu_pre*/
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<&clk_gates5 6>,/*hclk_rom*/
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/*pclk_cpu_pre*/
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<&clk_gates5 4>,/*pclk_grf*/
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<&clk_gates5 7>,/*pclk_ddrupctl*/
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<&clk_gates5 14>,/*pclk_acodec*/
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<&clk_gates3 8>,/*pclk_hdmi*/
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/*aclk_peri_pre*/
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<&clk_gates4 3>,/*aclk_peri_axi_matrix*/
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//<&clk_gates5 1>,/*aclk_dmac2*/
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<&clk_gates9 15>,/*aclk_peri_niu*/
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<&clk_gates4 2>,/*aclk_cpu_peri*/
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/*hclk_peri_pre*/
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<&clk_gates4 0>,/*hclk_peri_matrix*/
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<&clk_gates9 13>,/*hclk_usb_peri*/
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<&clk_gates9 14>,/*hclk_peri_arbi*/
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/*pclk_peri_pre*/
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<&clk_gates4 1>,/*pclk_peri_axi_matrix*/
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/*hclk_vio_pre*/
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<&clk_gates6 12>,/*hclk_vio_bus*/
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<&clk_gates9 5>,/*hclk_lcdc*/
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/*aclk_vio_pre*/
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<&clk_gates6 13>,/*aclk_vio*/
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<&clk_gates9 6>,/*aclk_lcdc*/
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/*UART*/
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<&clk_gates1 12>,
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<&clk_gates1 13>,
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<&clk_gates8 2>,/*pclk_uart2*/
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<&clk_gpu>,
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/*jtag*/
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<&clk_gates1 3>;/*clk_jtag*/
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};
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i2c0: i2c@20072000 {
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compatible = "rockchip,rk30-i2c";
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reg = <0x20072000 0x1000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c0_sda &i2c0_scl>;
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pinctrl-1 = <&i2c0_gpio>;
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gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
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clocks = <&clk_gates8 4>;
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rockchip,check-idle = <1>;
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status = "disabled";
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};
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i2c1: i2c@20056000 {
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compatible = "rockchip,rk30-i2c";
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reg = <0x20056000 0x1000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c1_sda &i2c1_scl>;
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pinctrl-1 = <&i2c1_gpio>;
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gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
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clocks = <&clk_gates8 5>;
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rockchip,check-idle = <1>;
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status = "disabled";
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};
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i2c2: i2c@2005a000 {
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compatible = "rockchip,rk30-i2c";
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reg = <0x2005a000 0x1000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c2_sda &i2c2_scl>;
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pinctrl-1 = <&i2c2_gpio>;
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gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
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clocks = <&clk_gates8 6>;
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rockchip,check-idle = <1>;
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status = "disabled";
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};
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i2s: i2s@10220000 {
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compatible = "rockchip-i2s";
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reg = <0x10220000 0x1000>;
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i2s-id = <0>;
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clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
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clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&pdma 0>, <&pdma 1>;
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//#dma-cells = <2>;
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dma-names = "tx", "rx";
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//pinctrl-names = "default", "sleep";
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//pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
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//pinctrl-1 = <&i2s_gpio>;
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};
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codec: codec@20030000 {
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compatible = "rk3036-codec";
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reg = <0x20030000 0x1000>;
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spk_ctl_io = <&gpio1 GPIO_A0 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_gpio>;
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boot_depop = <1>;
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pa_enable_time = <1000>;
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clocks = <&clk_gates5 14>;
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clock-names = "g_pclk_acodec";
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};
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spdif: spdif@10204000 {
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compatible = "rockchip-spdif";
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reg = <0x10204000 0x1000>;
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clocks = <&clk_spdif>;
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clock-names = "spdif_mclk";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&pdma 13>;
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//#dma-cells = <1>;
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dma-names = "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&spdif_tx>;
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};
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pwm0: pwm@20050000 {
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compatible = "rockchip,rk-pwm";
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reg = <0x20050000 0x10>;
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#pwm-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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clocks = <&clk_gates7 10>;
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clock-names = "pclk_pwm";
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status = "disabled";
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||||
};
|
||||
|
||||
pwm1: pwm@20050010 {
|
||||
compatible = "rockchip,rk-pwm";
|
||||
reg = <0x20050010 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1_pin>;
|
||||
clocks = <&clk_gates7 10>;
|
||||
clock-names = "pclk_pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@20050020 {
|
||||
compatible = "rockchip,rk-pwm";
|
||||
reg = <0x20050020 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2_pin>;
|
||||
clocks = <&clk_gates7 10>;
|
||||
clock-names = "pclk_pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@20050030 {
|
||||
compatible = "rockchip,rk-pwm";
|
||||
reg = <0x20050030 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_pin>;
|
||||
clocks = <&clk_gates7 10>;
|
||||
clock-names = "pclk_pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
remotectl: pwm@20050030 {
|
||||
compatible = "rockchip,remotectl-pwm";
|
||||
reg = <0x20050030 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_pin>;
|
||||
clocks = <&clk_gates7 10>;
|
||||
clock-names = "pclk_pwm";
|
||||
remote_pwm_id = <3>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
emmc: rksdmmc@1021c000 {
|
||||
compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
|
||||
reg = <0x1021c000 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
//pinctrl-names = "default",,"suspend";
|
||||
//pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
|
||||
clocks = <&clk_emmc>, <&clk_gates7 0>;
|
||||
clock-names = "clk_mmc", "hclk_mmc";
|
||||
dmas = <&pdma 12>;
|
||||
dma-names = "dw_mci";
|
||||
num-slots = <1>;
|
||||
fifo-depth = <0x100>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
|
||||
sdmmc: rksdmmc@10214000 {
|
||||
compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
|
||||
reg = <0x10214000 0x4000>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default", "idle", "udbg";
|
||||
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
|
||||
pinctrl-1 = <&sdmmc0_gpio>;
|
||||
pinctrl-2 = <&uart2_xfer &sdmmc0_dectn>;
|
||||
cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
|
||||
clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
|
||||
clock-names = "clk_mmc", "hclk_mmc";
|
||||
dmas = <&pdma 10>;
|
||||
dma-names = "dw_mci";
|
||||
num-slots = <1>;
|
||||
fifo-depth = <0x100>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sdio: rksdmmc@10218000 {
|
||||
compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
|
||||
reg = <0x10218000 0x4000>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default","idle";
|
||||
pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
|
||||
pinctrl-1 = <&sdio0_gpio>;
|
||||
clocks = <&clk_sdio>, <&clk_gates5 11>;
|
||||
clock-names = "clk_mmc", "hclk_mmc";
|
||||
dmas = <&pdma 11>;
|
||||
dma-names = "dw_mci";
|
||||
num-slots = <1>;
|
||||
fifo-depth = <0x100>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
gpu {
|
||||
compatible = "arm,mali400";
|
||||
reg = <0x10091000 0x200>,
|
||||
<0x10090000 0x100>,
|
||||
<0x10093000 0x100>,
|
||||
<0x10098000 0x1100>,
|
||||
<0x10094000 0x100>;
|
||||
reg-names = "Mali_L2",
|
||||
"Mali_GP",
|
||||
"Mali_GP_MMU",
|
||||
"Mali_PP0",
|
||||
"Mali_PP0_MMU";
|
||||
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "Mali_GP_IRQ",
|
||||
"Mali_GP_MMU_IRQ",
|
||||
"Mali_PP0_IRQ",
|
||||
"Mali_PP0_MMU_IRQ";
|
||||
};
|
||||
dwc_control_usb: dwc-control-usb@20008000 {
|
||||
compatible = "rockchip,rk3036-dwc-control-usb";
|
||||
reg = <0x20008000 0x4>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "otg_bvalid",
|
||||
"otg0_linestate",
|
||||
"otg1_linestate";
|
||||
clocks = <&clk_gates9 13>;
|
||||
clock-names = "hclk_usb_peri";
|
||||
rockchip,remote_wakeup;
|
||||
rockchip,usb_irq_wakeup;
|
||||
resets = <&reset RK3036_RST_USBPOR>;
|
||||
reset-names = "usbphy_por";
|
||||
usb_bc{
|
||||
compatible = "rockchip,ctrl";
|
||||
rk_usb,bvalid = <0x14c 8 1>;
|
||||
rk_usb,iddig = <0x14c 11 1>;
|
||||
rk_usb,line = <0x14c 9 2>;
|
||||
rk_usb,softctrl = <0x17c 0 1>;
|
||||
rk_usb,opmode = <0x17c 2 2>;
|
||||
rk_usb,xcvrsel = <0x17c 4 2>;
|
||||
rk_usb,termsel = <0x17c 6 1>;
|
||||
};
|
||||
};
|
||||
usb0: usb@10180000 {
|
||||
compatible = "rockchip,rk3036_usb20_otg";
|
||||
reg = <0x10180000 0x40000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates1 5>, <&clk_gates5 13>;
|
||||
clock-names = "clk_usbphy0", "hclk_usb0";
|
||||
resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
|
||||
<&reset RK3036_RST_OTGC0>;
|
||||
reset-names = "otg_ahb", "otg_phy", "otg_controller";
|
||||
/*0 - Normal, 1 - Force Host, 2 - Force Device*/
|
||||
rockchip,usb-mode = <0>;
|
||||
};
|
||||
|
||||
usb1: usb@101c0000 {
|
||||
compatible = "rockchip,rk3036_usb20_host";
|
||||
reg = <0x101c0000 0x40000>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates1 6>, <&clk_gates7 3>;
|
||||
clock-names = "clk_usbphy1", "hclk_usb1";
|
||||
resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
|
||||
<&reset RK3036_RST_OTGC1>;
|
||||
reset-names = "host_ahb", "host_phy", "host_controller";
|
||||
};
|
||||
|
||||
fb: fb{
|
||||
compatible = "rockchip,rk-fb";
|
||||
rockchip,disp-mode = <NO_DUAL>;
|
||||
rockchip,disp-policy = <DISPLAY_POLICY_BOX>;
|
||||
};
|
||||
|
||||
rk_screen: rk_screen{
|
||||
compatible = "rockchip,screen";
|
||||
};
|
||||
|
||||
lcdc: lcdc@10118000 {
|
||||
compatible = "rockchip,rk3036-lcdc";
|
||||
reg = <0x10118000 0x1000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
|
||||
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
|
||||
rockchip,iommu-enabled = <1>;
|
||||
};
|
||||
|
||||
hdmi: hdmi@20034000 {
|
||||
compatible = "rockchip,rk3036-hdmi";
|
||||
reg = <0x20034000 0x4000>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
rockchip,hdmi_lcdc_source = <0>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
|
||||
pinctrl-1 = <&hdmi_gpio>;
|
||||
clocks = <&clk_gates3 8>;
|
||||
clock-names = "pclk_hdmi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tve: tve{
|
||||
compatible = "rockchip,rk3036-tve";
|
||||
reg = <0x10118200 0x100>;
|
||||
saturation = <0x00386346>;
|
||||
brightcontrast = <0x00008b00>;
|
||||
adjtiming = <0xa6c00880>;
|
||||
lumafilter0 = <0x02ff0000>;
|
||||
lumafilter1 = <0xf40202fd>;
|
||||
lumafilter2 = <0xf332d919>;
|
||||
daclevel = <0x3e>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ion {
|
||||
compatible = "rockchip,ion";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
|
||||
compatible = "rockchip,ion-heap";
|
||||
rockchip,ion_heap = <4>;
|
||||
reg = <0x00000000 0x00000000>; /* 0MB */
|
||||
};
|
||||
rockchip,ion-heap@0 { /* VMALLOC HEAP */
|
||||
compatible = "rockchip,ion-heap";
|
||||
rockchip,ion_heap = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/*vpu: vpu_service@10108000 {
|
||||
compatible = "vpu_service";
|
||||
iommu_enabled = <1>;
|
||||
reg = <0x10108000 0x800>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "irq_dec";
|
||||
clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
|
||||
clock-names = "aclk_vcodec", "hclk_vcodec";
|
||||
name = "vpu_service";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hevc: hevc_service@1010c000 {
|
||||
compatible = "rockchip,hevc_service";
|
||||
iommu_enabled = <1>;
|
||||
reg = <0x1010c000 0x400>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "irq_dec";
|
||||
clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
|
||||
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
|
||||
name = "hevc_service";
|
||||
status = "okay";
|
||||
};*/
|
||||
vpu: vpu_service {
|
||||
compatible = "rockchip,vpu_sub";
|
||||
iommu_enabled = <1>;
|
||||
reg = <0x10108400 0x400>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "irq_dec";
|
||||
dev_mode = <0>;
|
||||
name = "vpu_service";
|
||||
};
|
||||
|
||||
hevc: hevc_service {
|
||||
compatible = "rockchip,hevc_sub";
|
||||
iommu_enabled = <1>;
|
||||
reg = <0x1010c000 0x400>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "irq_dec";
|
||||
dev_mode = <1>;
|
||||
name = "hevc_service";
|
||||
};
|
||||
|
||||
vpu_combo: vpu_combo@ff9a0000 {
|
||||
compatible = "rockchip,vpu_combo";
|
||||
subcnt = <2>;
|
||||
rockchip,sub = <&vpu>, <&hevc>;
|
||||
clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
|
||||
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
|
||||
mode_bit = <3>;
|
||||
mode_ctrl = <0x144>;
|
||||
name = "vpu_combo";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vop_mmu {
|
||||
dbgname = "vop";
|
||||
compatible = "rockchip,vop_mmu";
|
||||
reg = <0x10118300 0x100>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "vop_mmu";
|
||||
};
|
||||
|
||||
hevc_mmu {
|
||||
dbgname = "hevc";
|
||||
compatible = "rockchip,hevc_mmu";
|
||||
reg = <0x1010c440 0x40>,
|
||||
<0x1010c480 0x40>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hevc_mmu";
|
||||
};
|
||||
|
||||
vpu_mmu {
|
||||
dbgname = "vpu";
|
||||
compatible = "rockchip,vpu_mmu";
|
||||
reg = <0x10108800 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "vpu_mmu";
|
||||
};
|
||||
|
||||
rockchip_suspend: rockchip_suspend {
|
||||
rockchip,ctrbits = <
|
||||
(0
|
||||
//|RKPM_CTR_PWR_DMNS
|
||||
|RKPM_CTR_GTCLKS
|
||||
|RKPM_CTR_PLLS
|
||||
|RKPM_CTR_IDLESRAM_MD
|
||||
|RKPM_CTR_DDR
|
||||
|RKPM_CTR_VOLTS
|
||||
|RKPM_CTR_VOL_PWM2
|
||||
|
||||
//|RKPM_CTR_GPIOS
|
||||
//|RKPM_CTR_SYSCLK_DIV
|
||||
//|RKPM_CTR_IDLEAUTO_MD
|
||||
//|RKPM_CTR_ARMOFF_LPMD
|
||||
//|RKPM_CTR_ARMOFF_LOGDP_LPMD
|
||||
)
|
||||
>;
|
||||
/*
|
||||
rockchip,pmic-suspend_gpios = <
|
||||
RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
|
||||
>;
|
||||
rockchip,pmic-resume_gpios = <
|
||||
RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
|
||||
>;
|
||||
*/
|
||||
};
|
||||
|
||||
vmac: eth@10200000 {
|
||||
compatible = "rockchip,vmac";
|
||||
reg = <0x10200000 0x4000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&clk_mac_pll>, <&clk_mac_ref>,
|
||||
<&clk_mac_pll_div>, <&clk_mac_ref_div>,
|
||||
<&clk_gates2 6>, <&clk_gates3 5>;
|
||||
clock-names = "clk_mac_pll", "clk_mac_ref",
|
||||
"clk_mac_pll_div", "clk_mac_ref_div",
|
||||
"clk_tx_rx_gate", "hclk_mac";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_crs &mac_mdpins>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user