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arm64: kernel: Disable CNP on HiSilicon HIP09

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HiSilicon HIP09 implements TLB entry matching behavior that deviates
from the ARM architecture specification when the CNP (Common not Private)
bit is set in TTBRx_ELx.

When TTBRx.CNP=1, TLB entries may be incorrectly shared between CPU
cores, leading to TLB conflicts and stale mappings. This affects
coherency and can result in incorrect translations.

Add the hardware erratum workaround (Hisilicon erratum 162100125) to
disable CNP on affected HIP09 cores.

Co-developed-by: Tong Tiangen <tongtiangen@huawei.com>
Signed-off-by: Tong Tiangen <tongtiangen@huawei.com>
Signed-off-by: Zeng Heng <zengheng4@huawei.com>
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Zeng Heng 2026-06-03 14:20:25 +08:00 committed by Will Deacon
parent 25996982eb
commit f64328ecf4
3 changed files with 22 additions and 2 deletions
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2
Documentation/arch/arm64/silicon-errata.rst
View File

@ -287,6 +287,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Hisilicon | Hip09 | #162100801 | HISILICON_ERRATUM_162100801 |
+----------------+-----------------+-----------------+-----------------------------+
| Hisilicon | Hip09 | #162100125 | HISILICON_ERRATUM_162100125 |
+----------------+-----------------+-----------------+-----------------------------+
+----------------+-----------------+-----------------+-----------------------------+
| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
+----------------+-----------------+-----------------+-----------------------------+

16
arch/arm64/Kconfig
View File

@ -1273,6 +1273,22 @@ config HISILICON_ERRATUM_162100801
If unsure, say Y.
config HISILICON_ERRATUM_162100125
bool "Hisilicon erratum 162100125"
default y
select ARM64_WORKAROUND_DISABLE_CNP
help
On HiSilicon HIP09, TLB entry matching behavior when CNP
(TTBRx.CNP=1) is enabled differs from the ARM architecture
specification.
TLB entries may be incorrectly shared between CPUs, potentially
causing TLB conflicts and stale mappings.
Disable CNP support for affected HiSilicon HIP09 cores.
If unsure, say Y.
config QCOM_FALKOR_ERRATUM_1003
bool "Falkor E1003: Incorrect translation due to ASID change"
default y

6
arch/arm64/kernel/cpu_errata.c
View File

@ -612,6 +612,9 @@ static const struct midr_range erratum_ac04_cpu_23_list[] = {
static const struct midr_range cnp_erratum_cpus[] = {
#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
#endif
#ifdef CONFIG_HISILICON_ERRATUM_162100125
MIDR_ALL_VERSIONS(MIDR_HISI_HIP09),
#endif
{},
};
@ -812,8 +815,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
#endif
#ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP
{
/* NVIDIA Carmel */
.desc = "NVIDIA Carmel CNP erratum",
.desc = "NVIDIA Carmel CNP erratum, or Hisilicon erratum 162100125",
.capability = ARM64_WORKAROUND_DISABLE_CNP,
ERRATA_MIDR_RANGE_LIST(cnp_erratum_cpus),
},