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net: wireless: rockchip_wlan: add rtl8723bs support

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update rtl8723bs wifi driver to version v4.4.2_17831.20160519_BTCOEX20151223-654a

Change-Id: I1976f1ece2f318ab7eb11308bc019691ff84d319
Signed-off-by: zzc <zzc@rock-chips.com>
This commit is contained in:
zzc 2017-08-03 14:44:12 +08:00 committed by Huang, Tao
parent 4fd28eafda
commit f62b360d66
515 changed files with 157706 additions and 128459 deletions
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1
drivers/net/wireless/rockchip_wlan/Kconfig
View File

@ -21,6 +21,7 @@ source "drivers/net/wireless/rockchip_wlan/rtl8188eu/Kconfig"
source "drivers/net/wireless/rockchip_wlan/rtl8188fu/Kconfig"
source "drivers/net/wireless/rockchip_wlan/rtl8189es/Kconfig"
source "drivers/net/wireless/rockchip_wlan/rtl8189fs/Kconfig"
source "drivers/net/wireless/rockchip_wlan/rtl8723bs/Kconfig"
source "drivers/net/wireless/rockchip_wlan/rtl8723cs/Kconfig"
source "drivers/net/wireless/rockchip_wlan/rtl8723ds/Kconfig"
source "drivers/net/wireless/rockchip_wlan/rtl8822be/Kconfig"

1
drivers/net/wireless/rockchip_wlan/Makefile
View File

@ -3,6 +3,7 @@ obj-$(CONFIG_RTL8188EU) += rtl8188eu/
obj-$(CONFIG_RTL8188FU) += rtl8188fu/
obj-$(CONFIG_RTL8189ES) += rtl8189es/
obj-$(CONFIG_RTL8189FS) += rtl8189fs/
obj-$(CONFIG_RTL8723BS) += rtl8723bs/
obj-$(CONFIG_RTL8723CS) += rtl8723cs/
obj-$(CONFIG_RTL8723DS) += rtl8723ds/
obj-$(CONFIG_RTL8822BE) += rtl8822be/

14
drivers/net/wireless/rockchip_wlan/rtl8723bs/Kconfig Executable file → Normal file
View File

@ -1,16 +1,4 @@
#config RTL8723AS
# tristate "Realtek 8723A SDIO or SPI WiFi"
# ---help---
# Help message of RTL8723AS
config RTL8723BS
tristate "Realtek 8723BS SDIO or SPI WiFi"
tristate "Realtek 8723B SDIO or SPI WiFi"
---help---
Help message of RTL8723BS
#config WLAN_SDIO
# bool "Enable SDIO interface for Realtek"
# depends on RTL8723AS || RTL8723BS
# default n
# ---help---
# Use memory preallocated in platform

814
drivers/net/wireless/rockchip_wlan/rtl8723bs/Makefile Executable file → Normal file
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File diff suppressed because it is too large Load Diff

0
drivers/net/wireless/rockchip_wlan/rtl8723bs/Module.symvers
View File

0
drivers/net/wireless/rockchip_wlan/rtl8723bs/clean Executable file → Normal file
View File

549
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/efuse/rtw_efuse.c Executable file → Normal file
View File

@ -22,6 +22,7 @@
#include <drv_types.h>
#include <hal_data.h>
#include "../hal/efuse/efuse_mask.h"
/*------------------------Define local variable------------------------------*/
u8 fakeEfuseBank=0;
@ -39,6 +40,8 @@ u32 fakeBTEfuseUsedBytes=0;
u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]={0};
u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]={0};
u8 maskfileBuffer[32];
/*------------------------Define local variable------------------------------*/
//------------------------------------------------------------------------------
@ -433,7 +436,8 @@ efuse_OneByteRead(
u32 tmpidx = 0;
u8 bResult;
u8 readbyte;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
//DBG_871X("===> EFUSE_OneByteRead(), addr = %x\n", addr);
//DBG_871X("===> EFUSE_OneByteRead() start, 0x34 = 0x%X\n", rtw_read32(pAdapter, EFUSE_TEST));
@ -442,9 +446,11 @@ efuse_OneByteRead(
bResult = Efuse_Read1ByteFromFakeContent(pAdapter, addr, data);
return bResult;
}
if( IS_HARDWARE_TYPE_8723B(pAdapter) ||
(IS_HARDWARE_TYPE_8192E(pAdapter) && IS_VENDOR_8192E_B_CUT(pAdapter)))
(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) ||
(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID))
)
{
// <20130121, Kordan> For SMIC EFUSE specificatoin.
//0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8])
@ -495,7 +501,8 @@ efuse_OneByteWrite(
u8 tmpidx = 0;
u8 bResult=_FALSE;
u32 efuseValue = 0;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
//DBG_871X("===> EFUSE_OneByteWrite(), addr = %x data=%x\n", addr, data);
//DBG_871X("===> EFUSE_OneByteWrite() start, 0x34 = 0x%X\n", rtw_read32(pAdapter, EFUSE_TEST));
@ -505,6 +512,7 @@ efuse_OneByteWrite(
return bResult;
}
Efuse_PowerSwitch(pAdapter, _TRUE, _TRUE);
// -----------------e-fuse reg ctrl ---------------------------------
//address
@ -515,10 +523,11 @@ efuse_OneByteWrite(
efuseValue &= ~(0x3FFFF);
efuseValue |= ((addr<<8 | data) & 0x3FFFF);
// <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut.
if (IS_HARDWARE_TYPE_8723B(pAdapter)||(IS_HARDWARE_TYPE_8192E(pAdapter) && IS_VENDOR_8192E_B_CUT(pAdapter)))
{
if ( IS_HARDWARE_TYPE_8723B(pAdapter) ||
(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) ||
(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID))
) {
// <20130121, Kordan> For SMIC EFUSE specificatoin.
//0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8])
//PHY_SetMacReg(pAdapter, 0x34, BIT11, 1);
@ -548,11 +557,15 @@ efuse_OneByteWrite(
}
// disable Efuse program enable
if (IS_HARDWARE_TYPE_8723B(pAdapter))
{
if ( IS_HARDWARE_TYPE_8723B(pAdapter) ||
(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) ||
(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID))
) {
PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT(11), 0);
}
Efuse_PowerSwitch(pAdapter, _TRUE, _FALSE);
return bResult;
}
@ -711,6 +724,8 @@ u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *
u16 efuse_GetMaxSize(PADAPTER padapter)
{
u16 max_size;
max_size = 0;
EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_size, _FALSE);
return max_size;
}
@ -724,6 +739,24 @@ u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size)
return _SUCCESS;
}
//------------------------------------------------------------------------------
u16 efuse_bt_GetMaxSize(PADAPTER padapter)
{
u16 max_size;
max_size = 0;
EFUSE_GetEfuseDefinition(padapter, EFUSE_BT , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_size, _FALSE);
return max_size;
}
u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size)
{
Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
*size = Efuse_GetCurrentSize(padapter, EFUSE_BT, _FALSE);
Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
return _SUCCESS;
}
u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
{
u16 mapLen=0;
@ -759,6 +792,165 @@ u8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
return _SUCCESS;
}
BOOLEAN rtw_file_efuse_IsMasked(
PADAPTER pAdapter,
u16 Offset
)
{
int r = Offset/16;
int c = (Offset%16) / 2;
int result = 0;
if(pAdapter->registrypriv.boffefusemask)
return FALSE;
//DBG_871X(" %s ,Offset=%x r= %d , c=%d , maskfileBuffer[r]= %x \n",__func__,Offset,r,c,maskfileBuffer[r]);
if (c < 4) // Upper double word
result = (maskfileBuffer[r] & (0x10 << c));
else
result = (maskfileBuffer[r] & (0x01 << (c-4)));
return (result > 0) ? 0 : 1;
}
u8 rtw_efuse_file_read(PADAPTER padapter,u8 *filepatch,u8 *buf,u32 len)
{
char *ptmp;
char *ptmpbuf=NULL;
u32 rtStatus;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
ptmpbuf = rtw_zmalloc(2048);
if (ptmpbuf == NULL)
return _FALSE;
_rtw_memset(ptmpbuf,'\0',2048);
rtStatus = rtw_retrieve_from_file(filepatch, ptmpbuf, 2048);
if( rtStatus > 100 )
{
u32 i,j;
for(i=0,j=0;j<len;i+=2,j++)
{
if (( ptmpbuf[i] == ' ' ) && (ptmpbuf[i+1] != '\n' && ptmpbuf[i+1] != '\0')) {
i++;
}
if( (ptmpbuf[i+1] != '\n' && ptmpbuf[i+1] != '\0'))
{
buf[j] = simple_strtoul(&ptmpbuf[i],&ptmp, 16);
DBG_871X(" i=%d,j=%d, %x \n",i,j,buf[j]);
} else {
j--;
}
}
} else {
DBG_871X(" %s ,filepatch %s , FAIL %d\n", __func__, filepatch, rtStatus);
return _FALSE;
}
rtw_mfree(ptmpbuf, 2048);
DBG_871X(" %s ,filepatch %s , done %d\n", __func__, filepatch, rtStatus);
return _TRUE;
}
BOOLEAN
efuse_IsMasked(
PADAPTER pAdapter,
u16 Offset
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
//if (bEfuseMaskOFF(pAdapter))
if(pAdapter->registrypriv.boffefusemask)
return FALSE;
#if DEV_BUS_TYPE == RT_USB_INTERFACE
#if defined(CONFIG_RTL8188E)
if (IS_HARDWARE_TYPE_8188E(pAdapter))
return (IS_MASKED(8188E,_MUSB,Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8812A)
if (IS_HARDWARE_TYPE_8812(pAdapter))
return (IS_MASKED(8812A,_MUSB,Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8821A)
//if (IS_HARDWARE_TYPE_8811AU(pAdapter))
// return (IS_MASKED(8811A,_MUSB,Offset)) ? TRUE : FALSE;
if (IS_HARDWARE_TYPE_8821(pAdapter))
return (IS_MASKED(8821A,_MUSB,Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8192E)
if (IS_HARDWARE_TYPE_8192E(pAdapter))
return (IS_MASKED(8192E,_MUSB,Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8723B)
if (IS_HARDWARE_TYPE_8723B(pAdapter))
return (IS_MASKED(8723B,_MUSB,Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8703B)
if (IS_HARDWARE_TYPE_8703B(pAdapter))
return (IS_MASKED(8703B, _MUSB, Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8814A)
if (IS_HARDWARE_TYPE_8814A(pAdapter))
return (IS_MASKED(8814A, _MUSB, Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8188F)
if (IS_HARDWARE_TYPE_8188F(pAdapter))
return (IS_MASKED(8188F, _MUSB, Offset)) ? TRUE : FALSE;
#endif
#elif DEV_BUS_TYPE == RT_PCI_INTERFACE
#if defined(CONFIG_RTL8188E)
if (IS_HARDWARE_TYPE_8188E(pAdapter))
return (IS_MASKED(8188E,_MPCIE,Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8192E)
if (IS_HARDWARE_TYPE_8192E(pAdapter))
return (IS_MASKED(8192E,_MPCIE,Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8812A)
if (IS_HARDWARE_TYPE_8812(pAdapter))
return (IS_MASKED(8812A,_MPCIE,Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8821A)
if (IS_HARDWARE_TYPE_8821(pAdapter))
return (IS_MASKED(8821A,_MPCIE,Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8723B)
if (IS_HARDWARE_TYPE_8723B(pAdapter))
return (IS_MASKED(8723B,_MPCIE,Offset)) ? TRUE : FALSE;
#endif
#if defined(CONFIG_RTL8814A)
if (IS_HARDWARE_TYPE_8814A(pAdapter))
return (IS_MASKED(8814A, _MPCIE, Offset)) ? TRUE : FALSE;
#endif
//else if (IS_HARDWARE_TYPE_8821B(pAdapter))
// return (IS_MASKED(8821B,_MPCIE,Offset)) ? TRUE : FALSE;
#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE
#ifdef CONFIG_RTL8188E_SDIO
if (IS_HARDWARE_TYPE_8188E(pAdapter))
return (IS_MASKED(8188E,_MSDIO,Offset)) ? TRUE : FALSE;
#endif
#ifdef CONFIG_RTL8188F_SDIO
if (IS_HARDWARE_TYPE_8188F(pAdapter))
return (IS_MASKED(8188F, _MSDIO, Offset)) ? TRUE : FALSE;
#endif
#endif
return FALSE;
}
//------------------------------------------------------------------------------
u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
{
@ -775,7 +967,6 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
s32 i, j, idx;
u8 ret = _SUCCESS;
u16 mapLen=0;
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
@ -796,7 +987,24 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
ret = rtw_efuse_map_read(padapter, 0, mapLen, map);
if (ret == _FAIL) goto exit;
Efuse_PowerSwitch(padapter, _TRUE, _TRUE);
if(padapter->registrypriv.boffefusemask==0)
{
for (i =0; i < cnts; i++)
{
if(padapter->registrypriv.bFileMaskEfuse==_TRUE)
{
if (rtw_file_efuse_IsMasked(padapter, addr+i)) /*use file efuse mask. */
data[i] = map[addr+i];
}
else
{
if ( efuse_IsMasked(padapter, addr+i ))
data[i] = map[addr+i];
}
DBG_8192C("%s , data[%d] = %x, map[addr+i]= %x\n", __func__, i, data[i], map[addr+i]);
}
}
/*Efuse_PowerSwitch(padapter, _TRUE, _TRUE);*/
idx = 0;
offset = (addr >> 3);
@ -816,10 +1024,10 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
{
if (IS_C_CUT(pHalData->VersionID) || IS_B_CUT(pHalData->VersionID))
{
if(pEEPROM->adjuseVoltageVal == 6)
if(pHalData->adjuseVoltageVal == 6)
{
newdata[i] = map[addr + idx];
DBG_8192C(" %s ,\n adjuseVoltageVal = %d ,newdata[%d] = %x \n",__func__,pEEPROM->adjuseVoltageVal,i,newdata[i]);
DBG_8192C(" %s ,\n adjuseVoltageVal = %d ,newdata[%d] = %x \n",__func__,pHalData->adjuseVoltageVal,i,newdata[i]);
}
}
}
@ -842,7 +1050,7 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
offset++;
}
Efuse_PowerSwitch(padapter, _TRUE, _FALSE);
/*Efuse_PowerSwitch(padapter, _TRUE, _FALSE);*/
exit:
@ -851,8 +1059,35 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
return ret;
}
u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
{
u8 ret = _SUCCESS;
u16 mapLen = 0, i = 0;
EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
ret = rtw_efuse_map_read(padapter, addr, cnts , data);
if (padapter->registrypriv.boffefusemask == 0) {
for (i = 0; i < cnts; i++) {
if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
if (rtw_file_efuse_IsMasked(padapter, addr+i)) /*use file efuse mask.*/
data[i] = 0xff;
} else {
/*DBG_8192C(" %s , data[%d] = %x\n", __func__, i, data[i]);*/
if (efuse_IsMasked(padapter, addr+i)) {
data[i] = 0xff;
/*DBG_8192C(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/
}
}
}
}
return ret;
}
//------------------------------------------------------------------------------
u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
{
#define RT_ASSERT_RET(expr) \
@ -1005,9 +1240,9 @@ efuse_ShadowRead1Byte(
IN u16 Offset,
IN OUT u8 *Value)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
*Value = pEEPROM->efuse_eeprom_data[Offset];
*Value = pHalData->efuse_eeprom_data[Offset];
} // EFUSE_ShadowRead1Byte
@ -1018,10 +1253,10 @@ efuse_ShadowRead2Byte(
IN u16 Offset,
IN OUT u16 *Value)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
*Value = pEEPROM->efuse_eeprom_data[Offset];
*Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8;
*Value = pHalData->efuse_eeprom_data[Offset];
*Value |= pHalData->efuse_eeprom_data[Offset+1]<<8;
} // EFUSE_ShadowRead2Byte
@ -1032,12 +1267,12 @@ efuse_ShadowRead4Byte(
IN u16 Offset,
IN OUT u32 *Value)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
*Value = pEEPROM->efuse_eeprom_data[Offset];
*Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8;
*Value |= pEEPROM->efuse_eeprom_data[Offset+2]<<16;
*Value |= pEEPROM->efuse_eeprom_data[Offset+3]<<24;
*Value = pHalData->efuse_eeprom_data[Offset];
*Value |= pHalData->efuse_eeprom_data[Offset+1]<<8;
*Value |= pHalData->efuse_eeprom_data[Offset+2]<<16;
*Value |= pHalData->efuse_eeprom_data[Offset+3]<<24;
} // efuse_ShadowRead4Byte
@ -1073,9 +1308,9 @@ efuse_ShadowWrite1Byte(
IN u16 Offset,
IN u8 Value)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
pEEPROM->efuse_eeprom_data[Offset] = Value;
pHalData->efuse_eeprom_data[Offset] = Value;
} // efuse_ShadowWrite1Byte
@ -1086,10 +1321,12 @@ efuse_ShadowWrite2Byte(
IN u16 Offset,
IN u16 Value)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
pEEPROM->efuse_eeprom_data[Offset] = Value&0x00FF;
pEEPROM->efuse_eeprom_data[Offset+1] = Value>>8;
pHalData->efuse_eeprom_data[Offset] = Value&0x00FF;
pHalData->efuse_eeprom_data[Offset+1] = Value>>8;
} // efuse_ShadowWrite1Byte
@ -1100,12 +1337,12 @@ efuse_ShadowWrite4Byte(
IN u16 Offset,
IN u32 Value)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
pEEPROM->efuse_eeprom_data[Offset] = (u8)(Value&0x000000FF);
pEEPROM->efuse_eeprom_data[Offset+1] = (u8)((Value>>8)&0x0000FF);
pEEPROM->efuse_eeprom_data[Offset+2] = (u8)((Value>>16)&0x00FF);
pEEPROM->efuse_eeprom_data[Offset+3] = (u8)((Value>>24)&0xFF);
pHalData->efuse_eeprom_data[Offset] = (u8)(Value&0x000000FF);
pHalData->efuse_eeprom_data[Offset+1] = (u8)((Value>>8)&0x0000FF);
pHalData->efuse_eeprom_data[Offset+2] = (u8)((Value>>16)&0x00FF);
pHalData->efuse_eeprom_data[Offset+3] = (u8)((Value>>24)&0xFF);
} // efuse_ShadowWrite1Byte
@ -1130,25 +1367,25 @@ void EFUSE_ShadowMapUpdate(
IN u8 efuseType,
IN BOOLEAN bPseudoTest)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
u16 mapLen=0;
EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest);
if (pEEPROM->bautoload_fail_flag == _TRUE)
if (pHalData->bautoload_fail_flag == _TRUE)
{
_rtw_memset(pEEPROM->efuse_eeprom_data, 0xFF, mapLen);
_rtw_memset(pHalData->efuse_eeprom_data, 0xFF, mapLen);
}
else
{
#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
if(_SUCCESS != retriveAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pEEPROM)) {
if(_SUCCESS != retriveAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data)) {
#endif
Efuse_ReadAllMap(pAdapter, efuseType, pEEPROM->efuse_eeprom_data, bPseudoTest);
Efuse_ReadAllMap(pAdapter, efuseType, pHalData->efuse_eeprom_data, bPseudoTest);
#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
storeAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pEEPROM);
storeAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data);
}
#endif
}
@ -1265,6 +1502,40 @@ Efuse_InitSomeVar(
_rtw_memset((PVOID)&fakeBTEfuseModifiedMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN);
}
const u8 _mac_hidden_max_bw_to_hal_bw_cap[MAC_HIDDEN_MAX_BW_NUM] = {
0,
0,
(BW_CAP_160M|BW_CAP_80M|BW_CAP_40M|BW_CAP_20M|BW_CAP_10M|BW_CAP_5M),
(BW_CAP_5M),
(BW_CAP_10M|BW_CAP_5M),
(BW_CAP_20M|BW_CAP_10M|BW_CAP_5M),
(BW_CAP_40M|BW_CAP_20M|BW_CAP_10M|BW_CAP_5M),
(BW_CAP_80M|BW_CAP_40M|BW_CAP_20M|BW_CAP_10M|BW_CAP_5M),
};
const u8 _mac_hidden_proto_to_hal_proto_cap[MAC_HIDDEN_PROTOCOL_NUM] = {
0,
0,
(PROTO_CAP_11N|PROTO_CAP_11G|PROTO_CAP_11B),
(PROTO_CAP_11AC|PROTO_CAP_11N|PROTO_CAP_11G|PROTO_CAP_11B),
};
u8 mac_hidden_wl_func_to_hal_wl_func(u8 func)
{
u8 wl_func = 0;
if (func & BIT0)
wl_func |= WL_FUNC_MIRACAST;
if (func & BIT1)
wl_func |= WL_FUNC_P2P;
if (func & BIT2)
wl_func |= WL_FUNC_TDLS;
if (func & BIT3)
wl_func |= WL_FUNC_FTM;
return wl_func;
}
#ifdef PLATFORM_LINUX
#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
//#include <rtw_eeprom.h>
@ -1274,12 +1545,12 @@ Efuse_InitSomeVar(
return _TRUE;
}
int storeAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv)
int storeAdaptorInfoFile(char *path, u8* efuse_data)
{
int ret =_SUCCESS;
if(path && eeprom_priv) {
ret = rtw_store_to_file(path, eeprom_priv->efuse_eeprom_data, EEPROM_MAX_SIZE_512);
if(path && efuse_data) {
ret = rtw_store_to_file(path, efuse_data, EEPROM_MAX_SIZE_512);
if(ret == EEPROM_MAX_SIZE)
ret = _SUCCESS;
else
@ -1291,15 +1562,15 @@ int storeAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv)
return ret;
}
int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv)
int retriveAdaptorInfoFile(char *path, u8* efuse_data)
{
int ret = _SUCCESS;
mm_segment_t oldfs;
struct file *fp;
if(path && eeprom_priv) {
if(path && efuse_data) {
ret = rtw_retrive_from_file(path, eeprom_priv->efuse_eeprom_data, EEPROM_MAX_SIZE);
ret = rtw_retrieve_from_file(path, efuse_data, EEPROM_MAX_SIZE);
if(ret == EEPROM_MAX_SIZE)
ret = _SUCCESS;
@ -1320,117 +1591,141 @@ int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv)
}
return ret;
}
#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE
#endif //PLATFORM_LINUX
#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */
#ifdef CONFIG_EFUSE_CONFIG_FILE
void Rtw_Hal_ReadMACAddrFromFile(PADAPTER padapter)
u32 rtw_read_efuse_from_file(const char *path, u8 *buf)
{
u32 i;
u8 temp[3];
u32 ret = _FAIL;
struct file *fp;
mm_segment_t fs;
u8 source_addr[18];
loff_t pos = 0;
u32 curtime = rtw_get_current_time();
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
u8 *head, *end;
u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
_rtw_memset(source_addr, 0, 18);
_rtw_memset(pEEPROM->mac_addr, 0, ETH_ALEN);
fp = filp_open(path, O_RDONLY, 0);
if (fp == NULL || IS_ERR(fp)) {
if (fp != NULL)
DBG_871X_LEVEL(_drv_always_, "%s open %s fail, err:%ld\n"
, __func__, path, PTR_ERR(fp));
else
DBG_871X_LEVEL(_drv_always_, "%s open %s fail, fp is NULL\n"
, __func__, path);
fp = filp_open("/data/wifimac.txt", O_RDWR, 0644);
if (IS_ERR(fp)) {
pEEPROM->bloadmac_fail_flag = _TRUE;
DBG_871X("Error, wifi mac address file doesn't exist.\n");
} else {
fs = get_fs();
set_fs(KERNEL_DS);
goto exit;
}
DBG_871X("wifi mac address:\n");
vfs_read(fp, source_addr, 18, &pos);
source_addr[17] = ':';
temp[2] = 0; /* add end of string '\0' */
head = end = source_addr;
for (i=0; i<ETH_ALEN; i++) {
while (end && (*end != ':') )
end++;
fs = get_fs();
set_fs(KERNEL_DS);
if (end && (*end == ':') )
*end = '\0';
pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
if (end) {
end++;
head = end;
}
DBG_871X("%02x \n", pEEPROM->mac_addr[i]);
for (i = 0 ; i < HWSET_MAX_SIZE ; i++) {
vfs_read(fp, temp, 2, &pos);
if (sscanf(temp, "%hhx", &buf[i]) != 1) {
if (0)
DBG_871X_LEVEL(_drv_err_, "%s sscanf fail\n", __func__);
buf[i] = 0xFF;
}
if ((i % EFUSE_FILE_COLUMN_NUM) == (EFUSE_FILE_COLUMN_NUM - 1)) {
/* Filter the lates space char. */
vfs_read(fp, temp, 1, &pos);
if (strchr(temp, ' ') == NULL) {
pos--;
vfs_read(fp, temp, 2, &pos);
}
} else {
pos += 1; /* Filter the space character */
}
DBG_871X("\n");
set_fs(fs);
pEEPROM->bloadmac_fail_flag = _FALSE;
filp_close(fp, NULL);
}
if ( (_rtw_memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) ||
(_rtw_memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) {
pEEPROM->mac_addr[0] = 0x00;
pEEPROM->mac_addr[1] = 0xe0;
pEEPROM->mac_addr[2] = 0x4c;
pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
}
set_fs(fs);
DBG_871X("Hal_ReadMACAddrFromFile: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x !!!\n",
pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
DBG_871X_LEVEL(_drv_always_, "efuse file: %s\n", path);
#ifdef CONFIG_DEBUG
for (i = 0; i < HWSET_MAX_SIZE; i++) {
if (i % 16 == 0)
DBG_871X_SEL_NL(RTW_DBGDUMP, "0x%03x: ", i);
DBG_871X_SEL(RTW_DBGDUMP, "%02X%s"
, buf[i]
, ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ")
);
}
DBG_871X_SEL(RTW_DBGDUMP, "\n");
#endif
ret = _SUCCESS;
exit:
return ret;
}
u32 Rtw_Hal_readPGDataFromConfigFile(PADAPTER padapter)
u32 rtw_read_macaddr_from_file(const char *path, u8 *buf)
{
u32 i;
struct file *fp;
mm_segment_t fs;
u8 temp[3];
loff_t pos = 0;
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
u8 *PROMContent = pEEPROM->efuse_eeprom_data;
u8 source_addr[18];
u8 *head, *end;
int i;
u32 ret = _FAIL;
temp[2] = 0; // add end of string '\0'
_rtw_memset(source_addr, 0, 18);
fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR, 0644);
if (IS_ERR(fp)) {
pEEPROM->bloadfile_fail_flag = _TRUE;
DBG_871X("Error, Efuse configure file doesn't exist.\n");
return _FAIL;
fp = filp_open(path, O_RDONLY, 0);
if (fp == NULL || IS_ERR(fp)) {
if (fp != NULL)
DBG_871X_LEVEL(_drv_always_, "%s open %s fail, err:%ld\n"
, __func__, path, PTR_ERR(fp));
else
DBG_871X_LEVEL(_drv_always_, "%s open %s fail, fp is NULL\n"
, __func__, path);
goto exit;
}
fs = get_fs();
set_fs(KERNEL_DS);
DBG_871X("Efuse configure file:\n");
for (i=0; i< EFUSE_MAP_SIZE ; i++) {
vfs_read(fp, temp, 2, &pos);
PROMContent[i] = simple_strtoul(temp, NULL, 16 );
pos += 1; // Filter the space character
DBG_871X("%02X \n", PROMContent[i]);
vfs_read(fp, source_addr, 18, &pos);
source_addr[17] = ':';
head = end = source_addr;
for (i = 0; i < ETH_ALEN; i++) {
while (end && (*end != ':'))
end++;
if (end && (*end == ':'))
*end = '\0';
if (sscanf(head, "%hhx", &buf[i]) != 1) {
if (0)
DBG_871X_LEVEL(_drv_err_, "%s sscanf fail\n", __func__);
buf[i] = 0xFF;
}
if (end) {
end++;
head = end;
}
}
DBG_871X("\n");
set_fs(fs);
filp_close(fp, NULL);
pEEPROM->bloadfile_fail_flag = _FALSE;
return _SUCCESS;
}
DBG_871X_LEVEL(_drv_always_, "wifi_mac file: %s\n", path);
#ifdef CONFIG_DEBUG
DBG_871X(MAC_FMT"\n", MAC_ARG(buf));
#endif
ret = _SUCCESS;
exit:
return ret;
}
#endif /* CONFIG_EFUSE_CONFIG_FILE */
#endif /* PLATFORM_LINUX */
#endif //#CONFIG_EFUSE_CONFIG_FILE

1623
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_ap.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

454
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_beamforming.c Executable file → Normal file
View File

@ -24,6 +24,7 @@
#ifdef CONFIG_BEAMFORMING
#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/
struct beamforming_entry *beamforming_get_entry_by_addr(struct mlme_priv *pmlmepriv, u8* ra,u8* idx)
{
u8 i = 0;
@ -92,18 +93,21 @@ struct beamforming_entry *beamforming_add_entry(PADAPTER adapter, u8* ra, u16 ai
pEntry->sound_bw = bw;
if (check_fwstate(pmlmepriv, WIFI_AP_STATE))
{
u16 BSSID = ((adapter->eeprompriv.mac_addr[5] & 0xf0) >> 4) ^
(adapter->eeprompriv.mac_addr[5] & 0xf); // BSSID[44:47] xor BSSID[40:43]
u16 BSSID = ((*(adapter_mac_addr(adapter) + 5) & 0xf0) >> 4) ^
(*(adapter_mac_addr(adapter) + 5) & 0xf); /* BSSID[44:47] xor BSSID[40:43] */
pEntry->p_aid = (aid + BSSID * 32) & 0x1ff; // (dec(A) + dec(B)*32) mod 512
pEntry->g_id = 63;
}
else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))
{
pEntry->p_aid = 0;
pEntry->g_id = 63;
}
else
{
pEntry->p_aid = ra[5]; // BSSID[39:47]
pEntry->p_aid = (pEntry->p_aid << 1) | (ra[4] >> 7 );
pEntry->g_id = 0;
}
_rtw_memcpy(pEntry->mac_addr, ra, ETH_ALEN);
pEntry->bSound = _FALSE;
@ -113,9 +117,12 @@ struct beamforming_entry *beamforming_add_entry(PADAPTER adapter, u8* ra, u16 ai
pEntry->beamforming_entry_cap = beamfrom_cap;
pEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
pEntry->LogSeq = 0xff;
pEntry->LogRetryCnt = 0;
pEntry->LogSuccessCnt = 0;
pEntry->PreLogSeq = 0; /*Modified by Jeffery @2015-04-13*/
pEntry->LogSeq = 0; /*Modified by Jeffery @2014-10-29*/
pEntry->LogRetryCnt = 0; /*Modified by Jeffery @2014-10-29*/
pEntry->LogSuccess = 0; /*LogSuccess is NOT needed to be accumulated, so LogSuccessCnt->LogSuccess, 2015-04-13, Jeffery*/
pEntry->ClockResetTimes = 0; /*Modified by Jeffery @2015-04-13*/
pEntry->LogStatusFailCnt = 0;
return pEntry;
@ -145,7 +152,7 @@ void beamforming_dym_ndpa_rate(PADAPTER adapter)
u16 NDPARate = MGN_6M;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
if(pHalData->dmpriv.MinUndecoratedPWDBForDM > 30) // link RSSI > 30%
if(pHalData->MinUndecoratedPWDBForDM > 30) // link RSSI > 30%
NDPARate = MGN_24M;
else
NDPARate = MGN_6M;
@ -209,103 +216,85 @@ void beamforming_dym_period(PADAPTER Adapter)
rtw_hal_set_hwreg(Adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&Idx);
}
u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame)
BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx)
{
u32 ret = _SUCCESS;
struct beamforming_entry *pBeamformEntry = NULL;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
u8 *pframe = precv_frame->u.hdr.rx_data;
u32 frame_len = precv_frame->u.hdr.len;
u8 *ta;
u8 idx, offset;
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
struct rtw_ieee80211_hdr *pwlanhdr;
struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv);
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
u8 *pframe;
u16 *fctrl;
u16 duration = 0;
u8 aSifsTime = 0;
u8 NDPTxRate = 0;
DBG_871X("%s: issue_ht_sw_ndpa_packet!\n", __func__);
NDPTxRate = MGN_MCS8;
DBG_871X("%s: NDPTxRate =%d\n", __func__, NDPTxRate);
pmgntframe = alloc_mgtxmitframe(pxmitpriv);
//DBG_871X("beamforming_get_report_frame\n");
if (pmgntframe == NULL)
return _FALSE;
//Memory comparison to see if CSI report is the same with previous one
ta = GetAddr2Ptr(pframe);
pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ta, &idx);
if(pBeamformEntry->beamforming_entry_cap & BEAMFORMER_CAP_VHT_SU)
offset = 31; //24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
else if(pBeamformEntry->beamforming_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)
offset = 34; //24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
/*update attribute*/
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(Adapter, pattrib);
pattrib->qsel = QSLT_MGNT;
pattrib->rate = NDPTxRate;
pattrib->bwmode = bw;
pattrib->order = 1;
pattrib->subtype = WIFI_ACTION_NOACK;
_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
fctrl = &pwlanhdr->frame_ctl;
*(fctrl) = 0;
SetOrderBit(pframe);
SetFrameSubType(pframe, WIFI_ACTION_NOACK);
_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
aSifsTime = 10;
else
return ret;
aSifsTime = 16;
//DBG_871X("%s MacId %d offset=%d\n", __FUNCTION__, pBeamformEntry->mac_id, offset);
if(_rtw_memcmp(pBeamformEntry->PreCsiReport + offset, pframe+offset, frame_len-offset) == _FALSE)
{
pBeamformEntry->DefaultCsiCnt = 0;
//DBG_871X("%s CSI report is NOT the same with previos one\n", __FUNCTION__);
}
else
{
pBeamformEntry->DefaultCsiCnt ++;
//DBG_871X("%s CSI report is the SAME with previos one\n", __FUNCTION__);
}
_rtw_memcpy(&pBeamformEntry->PreCsiReport, pframe, frame_len);
pBeamformEntry->bDefaultCSI = _FALSE;
if(pBeamformEntry->DefaultCsiCnt > 20)
pBeamformEntry->bDefaultCSI = _TRUE;
else
pBeamformEntry->bDefaultCSI = _FALSE;
duration = 2*aSifsTime + 40;
return ret;
if (bw == CHANNEL_WIDTH_40)
duration += 87;
else
duration += 180;
SetDuration(pframe, duration);
/*HT control field*/
SET_HT_CTRL_CSI_STEERING(pframe+24, 3);
SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1);
_rtw_memcpy(pframe+28, ActionHdr, 4);
pattrib->pktlen = 32;
pattrib->last_txcmdsz = pattrib->pktlen;
dump_mgntframe(Adapter, pmgntframe);
return _TRUE;
}
void beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame)
{
u8 *ta;
u8 idx, Sequence;
u8 *pframe = precv_frame->u.hdr.rx_data;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
struct beamforming_entry *pBeamformEntry = NULL;
//DBG_871X("beamforming_get_ndpa_frame\n");
if(IS_HARDWARE_TYPE_8812(Adapter) == _FALSE)
return;
else if(GetFrameSubType(pframe) != WIFI_NDPA)
return;
ta = GetAddr2Ptr(pframe);
// Remove signaling TA.
ta[0] = ta[0] & 0xFE;
pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ta, &idx);
if(pBeamformEntry == NULL)
return;
else if(!(pBeamformEntry->beamforming_entry_cap & BEAMFORMEE_CAP_VHT_SU))
return;
else if(pBeamformEntry->LogSuccessCnt > 1)
return;
Sequence = (pframe[16]) >> 2;
if(pBeamformEntry->LogSeq != Sequence)
{
/* Previous frame doesn't retry when meet new sequence number */
if(pBeamformEntry->LogSeq != 0xff && pBeamformEntry->LogRetryCnt == 0)
pBeamformEntry->LogSuccessCnt++;
pBeamformEntry->LogSeq = Sequence;
pBeamformEntry->LogRetryCnt = 0;
}
else
{
if(pBeamformEntry->LogRetryCnt == 3)
beamforming_wk_cmd(Adapter, BEAMFORMING_CTRL_SOUNDING_CLK, NULL, 0, 1);
pBeamformEntry->LogRetryCnt++;
}
DBG_871X("%s LogSeq %d LogRetryCnt %d LogSuccessCnt %d\n",
__FUNCTION__, pBeamformEntry->LogSeq, pBeamformEntry->LogRetryCnt, pBeamformEntry->LogSuccessCnt);
}
BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx)
{
struct xmit_frame *pmgntframe;
@ -320,12 +309,12 @@ BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx
u16 duration = 0;
u8 aSifsTime = 0;
if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
{
return _FALSE;
}
pmgntframe = alloc_mgtxmitframe(pxmitpriv);
//update attribute
if (pmgntframe == NULL)
return _FALSE;
/*update attribute*/
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(Adapter, pattrib);
@ -349,7 +338,7 @@ BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx
SetFrameSubType(pframe, WIFI_ACTION_NOACK);
_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, myid(&(Adapter->eeprompriv)), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
if( pmlmeext->cur_wireless_mode == WIRELESS_11B)
@ -385,7 +374,100 @@ BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH
{
return issue_ht_ndpa_packet(Adapter, ra, bw, qidx);
}
BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx)
{
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
struct rtw_ieee80211_hdr *pwlanhdr;
struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv);
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
struct rtw_ndpa_sta_info sta_info;
u8 NDPTxRate = 0;
u8 *pframe;
u16 *fctrl;
u16 duration = 0;
u8 sequence = 0, aSifsTime = 0;
DBG_871X("%s: issue_vht_sw_ndpa_packet!\n", __func__);
NDPTxRate = MGN_VHT2SS_MCS0;
DBG_871X("%s: NDPTxRate =%d\n", __func__, NDPTxRate);
pmgntframe = alloc_mgtxmitframe(pxmitpriv);
if (pmgntframe == NULL) {
DBG_871X("%s, alloc mgnt frame fail\n", __func__);
return _FALSE;
}
/*update attribute*/
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(Adapter, pattrib);
pattrib->qsel = QSLT_MGNT;
pattrib->rate = NDPTxRate;
pattrib->bwmode = bw;
pattrib->subtype = WIFI_NDPA;
_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
fctrl = &pwlanhdr->frame_ctl;
*(fctrl) = 0;
SetFrameSubType(pframe, WIFI_NDPA);
_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode))
aSifsTime = 16;
else
aSifsTime = 10;
duration = 2*aSifsTime + 44;
if (bw == CHANNEL_WIDTH_80)
duration += 40;
else if (bw == CHANNEL_WIDTH_40)
duration += 87;
else
duration += 180;
SetDuration(pframe, duration);
sequence = pBeamInfo->sounding_sequence << 2;
if (pBeamInfo->sounding_sequence >= 0x3f)
pBeamInfo->sounding_sequence = 0;
else
pBeamInfo->sounding_sequence++;
_rtw_memcpy(pframe+16, &sequence, 1);
if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
aid = 0;
sta_info.aid = aid;
sta_info.feedback_type = 0;
sta_info.nc_index = 0;
_rtw_memcpy(pframe+17, (u8 *)&sta_info, 2);
pattrib->pktlen = 19;
pattrib->last_txcmdsz = pattrib->pktlen;
dump_mgntframe(Adapter, pmgntframe);
return _TRUE;
}
BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx)
{
struct xmit_frame *pmgntframe;
@ -403,11 +485,9 @@ BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH b
u8 sequence = 0, aSifsTime = 0;
if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
{
return _FALSE;
}
//update attribute
/*update attribute*/
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(Adapter, pattrib);
@ -429,7 +509,7 @@ BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH b
SetFrameSubType(pframe, WIFI_NDPA);
_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, myid(&(Adapter->eeprompriv)), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode))
aSifsTime = 16;
@ -771,6 +851,8 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8* idx)
}
pBeamformEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
psta->txbf_paid = pBeamformEntry->p_aid;
psta->txbf_gid = pBeamformEntry->g_id;
DBG_871X("%s Idx %d\n", __FUNCTION__, *idx);
} else {
@ -913,14 +995,158 @@ void beamforming_watchdog(PADAPTER Adapter)
beamforming_dym_period(Adapter);
beamforming_dym_ndpa_rate(Adapter);
}
#endif/* #if (BEAMFORMING_SUPPORT ==0) - for diver defined beamforming*/
u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame)
{
u32 ret = _SUCCESS;
#if (BEAMFORMING_SUPPORT == 1)
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
ret = Beamforming_GetReportFrame(pDM_Odm, precv_frame);
#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/
struct beamforming_entry *pBeamformEntry = NULL;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
u8 *pframe = precv_frame->u.hdr.rx_data;
u32 frame_len = precv_frame->u.hdr.len;
u8 *ta;
u8 idx, offset;
/*DBG_871X("beamforming_get_report_frame\n");*/
/*Memory comparison to see if CSI report is the same with previous one*/
ta = GetAddr2Ptr(pframe);
pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ta, &idx);
if (pBeamformEntry->beamforming_entry_cap & BEAMFORMER_CAP_VHT_SU)
offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/
else if (pBeamformEntry->beamforming_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)
offset = 34; /*24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/
else
return ret;
/*DBG_871X("%s MacId %d offset=%d\n", __FUNCTION__, pBeamformEntry->mac_id, offset);*/
if (_rtw_memcmp(pBeamformEntry->PreCsiReport + offset, pframe+offset, frame_len-offset) == _FALSE)
pBeamformEntry->DefaultCsiCnt = 0;
else
pBeamformEntry->DefaultCsiCnt++;
_rtw_memcpy(&pBeamformEntry->PreCsiReport, pframe, frame_len);
pBeamformEntry->bDefaultCSI = _FALSE;
if (pBeamformEntry->DefaultCsiCnt > 20)
pBeamformEntry->bDefaultCSI = _TRUE;
else
pBeamformEntry->bDefaultCSI = _FALSE;
#endif
return ret;
}
void beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame)
{
#if (BEAMFORMING_SUPPORT == 1)
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
Beamforming_GetNDPAFrame(pDM_Odm, precv_frame);
#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/
u8 *ta;
u8 idx, Sequence;
u8 *pframe = precv_frame->u.hdr.rx_data;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
struct beamforming_entry *pBeamformEntry = NULL;
/*DBG_871X("beamforming_get_ndpa_frame\n");*/
if (IS_HARDWARE_TYPE_8812(Adapter) == _FALSE)
return;
else if (GetFrameSubType(pframe) != WIFI_NDPA)
return;
ta = GetAddr2Ptr(pframe);
/*Remove signaling TA. */
ta[0] = ta[0] & 0xFE;
pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ta, &idx);
if (pBeamformEntry == NULL)
return;
else if (!(pBeamformEntry->beamforming_entry_cap & BEAMFORMEE_CAP_VHT_SU))
return;
/*LogSuccess: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/
/*ClockResetTimes: While BFer entry always doesn't receive our CSI, clock will reset again and again.So ClockResetTimes is limited to 5 times.2015-04-13, Jeffery*/
else if ((pBeamformEntry->LogSuccess == 1) || (pBeamformEntry->ClockResetTimes == 5)) {
DBG_871X("[%s] LogSeq=%d, PreLogSeq=%d\n", __func__, pBeamformEntry->LogSeq, pBeamformEntry->PreLogSeq);
return;
}
Sequence = (pframe[16]) >> 2;
DBG_871X("[%s] Start, Sequence=%d, LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, ClockResetTimes=%d, LogSuccess=%d\n",
__func__, Sequence, pBeamformEntry->LogSeq, pBeamformEntry->PreLogSeq, pBeamformEntry->LogRetryCnt, pBeamformEntry->ClockResetTimes, pBeamformEntry->LogSuccess);
if ((pBeamformEntry->LogSeq != 0) && (pBeamformEntry->PreLogSeq != 0)) {
/*Success condition*/
if ((pBeamformEntry->LogSeq != Sequence) && (pBeamformEntry->PreLogSeq != pBeamformEntry->LogSeq)) {
/* break option for clcok reset, 2015-03-30, Jeffery */
pBeamformEntry->LogRetryCnt = 0;
/*As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/
/*That is, LogSuccess is NOT needed to be reset to zero, 2015-04-13, Jeffery*/
pBeamformEntry->LogSuccess = 1;
} else {/*Fail condition*/
if (pBeamformEntry->LogRetryCnt == 5) {
pBeamformEntry->ClockResetTimes++;
pBeamformEntry->LogRetryCnt = 0;
DBG_871X("[%s] Clock Reset!!! ClockResetTimes=%d\n", __func__, pBeamformEntry->ClockResetTimes);
beamforming_wk_cmd(Adapter, BEAMFORMING_CTRL_SOUNDING_CLK, NULL, 0, 1);
} else
pBeamformEntry->LogRetryCnt++;
}
}
/*Update LogSeq & PreLogSeq*/
pBeamformEntry->PreLogSeq = pBeamformEntry->LogSeq;
pBeamformEntry->LogSeq = Sequence;
#endif
}
void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
_func_enter_;
switch(type)
#if (BEAMFORMING_SUPPORT == 1) /*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/
switch (type) {
case BEAMFORMING_CTRL_ENTER:
{
struct sta_info *psta = (PVOID)pbuf;
u16 staIdx = psta->mac_id;
Beamforming_Enter(pDM_Odm, staIdx);
break;
}
case BEAMFORMING_CTRL_LEAVE:
Beamforming_Leave(pDM_Odm, pbuf);
break;
default:
break;
}
#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/
switch (type) {
case BEAMFORMING_CTRL_ENTER:
beamforming_enter(padapter, (PVOID)pbuf);
break;
@ -940,7 +1166,7 @@ _func_enter_;
default:
break;
}
#endif
_func_exit_;
}
@ -1006,5 +1232,13 @@ _func_exit_;
return res;
}
#endif //CONFIG_BEAMFORMING
void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
{
if (psta) {
pattrib->txbf_g_id = psta->txbf_gid;
pattrib->txbf_p_aid = psta->txbf_paid;
}
}
#endif

5
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_br_ext.c Executable file → Normal file
View File

@ -48,8 +48,11 @@
#include <linux/ipv6.h>
#include <linux/icmpv6.h>
#include <net/ndisc.h>
#include <net/checksum.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
#include <net/ip6_checksum.h>
#else
#include <net/checksum.h>
#endif
#endif
#endif

34
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_bt_mp.c Executable file → Normal file
View File

@ -22,13 +22,11 @@
#include <drv_types.h>
#include <rtw_bt_mp.h>
#ifdef CONFIG_RTL8723A
#include <rtl8723a_hal.h>
#elif defined(CONFIG_RTL8723B)
#if defined(CONFIG_RTL8723B)
#include <rtl8723b_hal.h>
#endif
#if defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
void MPh2c_timeout_handle(void *FunctionContext)
{
PADAPTER pAdapter;
@ -135,9 +133,7 @@ mptbt_SendH2c(
pMptCtx->MptH2cRspEvent = _FALSE;
pMptCtx->MptBtC2hEvent = _FALSE;
#if defined(CONFIG_RTL8723A)
rtw_hal_fill_h2c_cmd(Adapter, 70, h2cCmdLen, (pu1Byte)pH2c);
#elif defined(CONFIG_RTL8723B)
#if defined(CONFIG_RTL8723B)
rtl8723b_set_FwBtMpOper_cmd(Adapter, pH2c->opCode, pH2c->opCodeVer, pH2c->reqNum, pH2c->buf);
#endif
pMptCtx->h2cReqNum++;
@ -397,14 +393,14 @@ void mptbt_close_WiFiRF(PADAPTER Adapter)
{
PHY_SetBBReg(Adapter, 0x824, 0xF, 0x0);
PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x0);
PHY_SetRFReg(Adapter, RF90_PATH_A, 0x0, 0xF0000, 0x0);
PHY_SetRFReg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x0);
}
void mptbt_open_WiFiRF(PADAPTER Adapter)
{
PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x3);
PHY_SetBBReg(Adapter, 0x824, 0xF, 0x2);
PHY_SetRFReg(Adapter, RF90_PATH_A, 0x0, 0xF0000, 0x3);
PHY_SetRFReg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x3);
}
u4Byte mptbt_switch_RF(PADAPTER Adapter, u1Byte Enter)
@ -1089,25 +1085,7 @@ mptbt_BtSetGeneral(
calVal = pBtReq->pParamStart[1];
break;
case BT_GSET_UPDATE_BT_PATCH:
if(IS_HARDWARE_TYPE_8723AE(Adapter) && Adapter->bFWReady)
{
u1Byte i;
DBG_8192C ("[MPT], write regs for load patch\n");
//BTFwPatch8723A(Adapter);
PlatformEFIOWrite1Byte(Adapter, 0xCC, 0x2d);
rtw_msleep_os(50);
PlatformEFIOWrite4Byte(Adapter, 0x68, 0xa005000c);
rtw_msleep_os(50);
PlatformEFIOWrite4Byte(Adapter, 0x68, 0xb005000c);
rtw_msleep_os(50);
PlatformEFIOWrite1Byte(Adapter, 0xCC, 0x29);
for(i=0; i<12; i++)
rtw_msleep_os(100);
//#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
// BTFwPatch8723A(Adapter);
//#endif
DBG_8192C("[MPT], load BT FW Patch finished!!!\n");
}
break;
default:
{

1466
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_btcoex.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

1541
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_cmd.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

2034
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_debug.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

54
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_eeprom.c Executable file → Normal file
View File

@ -48,8 +48,8 @@ void shift_out_bits(_adapter * padapter, u16 data, u16 count)
u16 x,mask;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
mask = 0x01 << (count - 1);
@ -62,9 +62,9 @@ _func_enter_;
x &= ~_EEDI;
if(data & mask)
x |= _EEDI;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
rtw_write8(padapter, EE_9346CR, (u8)x);
rtw_udelay_os(CLOCK_RATE);
@ -72,8 +72,8 @@ _func_enter_;
down_clk(padapter, &x);
mask = mask >> 1;
} while(mask);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~_EEDI;
@ -86,8 +86,8 @@ u16 shift_in_bits (_adapter * padapter)
{
u16 x,d=0,i;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
@ -99,8 +99,8 @@ _func_enter_;
{
d = d << 1;
up_clk(padapter, &x);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
@ -157,24 +157,24 @@ void eeprom_clean(_adapter * padapter)
{
u16 x;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~(_EECS | _EEDI);
rtw_write8(padapter, EE_9346CR, (u8)x);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
up_clk(padapter, &x);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
down_clk(padapter, &x);
@ -288,15 +288,15 @@ u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom
#endif
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
// select EEPROM, reset bits, set _EECS
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
@ -337,15 +337,15 @@ void eeprom_read_sz(_adapter * padapter, u16 reg, u8* data, u32 sz)
u16 x, data16;
u32 i;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
// select EEPROM, reset bits, set _EECS
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
if (rtw_is_surprise_removed(padapter)) {
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}

1314
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_ieee80211.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

250
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_io.c Executable file → Normal file
View File

@ -50,6 +50,7 @@ jackson@realtek.com.tw
#define _RTW_IO_C_
#include <drv_types.h>
#include <hal_data.h>
#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
#error "Shall be Linux or Windows, but not both!\n"
@ -197,6 +198,111 @@ u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr)
_func_exit_;
return r_val;
}
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
u8 _rtw_sd_iread8(_adapter *adapter, u32 addr)
{
u8 r_val = 0x00;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u8 (*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);
_sd_iread8 = pintfhdl->io_ops._sd_iread8;
if (_sd_iread8)
r_val = _sd_iread8(pintfhdl, addr);
else
DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iread8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
return r_val;
}
u16 _rtw_sd_iread16(_adapter *adapter, u32 addr)
{
u16 r_val = 0x00;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u16 (*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);
_sd_iread16 = pintfhdl->io_ops._sd_iread16;
if (_sd_iread16)
r_val = _sd_iread16(pintfhdl, addr);
else
DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iread16 callback is NULL\n", FUNC_ADPT_ARG(adapter));
return r_val;
}
u32 _rtw_sd_iread32(_adapter *adapter, u32 addr)
{
u32 r_val = 0x00;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u32 (*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);
_sd_iread32 = pintfhdl->io_ops._sd_iread32;
if (_sd_iread32)
r_val = _sd_iread32(pintfhdl, addr);
else
DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iread32 callback is NULL\n", FUNC_ADPT_ARG(adapter));
return r_val;
}
int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
int ret = -1;
_sd_iwrite8 = pintfhdl->io_ops._sd_iwrite8;
if (_sd_iwrite8)
ret = _sd_iwrite8(pintfhdl, addr, val);
else
DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iwrite8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
return RTW_STATUS_CODE(ret);
}
int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
int ret = -1;
_sd_iwrite16 = pintfhdl->io_ops._sd_iwrite16;
if (_sd_iwrite16)
ret = _sd_iwrite16(pintfhdl, addr, val);
else
DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iwrite16 callback is NULL\n", FUNC_ADPT_ARG(adapter));
return RTW_STATUS_CODE(ret);
}
int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
int ret = -1;
_sd_iwrite32 = pintfhdl->io_ops._sd_iwrite32;
if (_sd_iwrite32)
ret = _sd_iwrite32(pintfhdl, addr, val);
else
DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iwrite32 callback is NULL\n", FUNC_ADPT_ARG(adapter));
return RTW_STATUS_CODE(ret);
}
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
@ -254,10 +360,11 @@ void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
_func_enter_;
if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
{
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
return;
if (RTW_CANNOT_RUN(adapter)) {
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%s) OR bSurpriseRemoved(%s)"
, rtw_is_drv_stopped(adapter)?"True":"False"
, rtw_is_surprise_removed(adapter)?"True":"False"));
return;
}
_read_mem = pintfhdl->io_ops._read_mem;
@ -294,9 +401,10 @@ void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
_func_enter_;
if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
{
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
if (RTW_CANNOT_RUN(adapter)) {
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%s) OR bSurpriseRemoved(%s)"
, rtw_is_drv_stopped(adapter)?"True":"False"
, rtw_is_surprise_removed(adapter)?"True":"False"));
return;
}
@ -416,19 +524,19 @@ void rtw_reset_continual_io_error(struct dvobj_priv *dvobj)
#ifdef DBG_IO
u16 read_sniff_ranges[][2] = {
u32 read_sniff_ranges[][2] = {
//{0x520, 0x523},
};
u16 write_sniff_ranges[][2] = {
u32 write_sniff_ranges[][2] = {
//{0x520, 0x523},
//{0x4c, 0x4c},
};
int read_sniff_num = sizeof(read_sniff_ranges)/sizeof(u16)/2;
int write_sniff_num = sizeof(write_sniff_ranges)/sizeof(u16)/2;
int read_sniff_num = sizeof(read_sniff_ranges)/sizeof(u32)/2;
int write_sniff_num = sizeof(write_sniff_ranges)/sizeof(u32)/2;
bool match_read_sniff_ranges(u16 addr, u16 len)
bool match_read_sniff_ranges(u32 addr, u16 len)
{
int i;
for (i = 0; i<read_sniff_num; i++) {
@ -439,7 +547,7 @@ bool match_read_sniff_ranges(u16 addr, u16 len)
return _FALSE;
}
bool match_write_sniff_ranges(u16 addr, u16 len)
bool match_write_sniff_ranges(u32 addr, u16 len)
{
int i;
for (i = 0; i<write_sniff_num; i++) {
@ -450,6 +558,51 @@ bool match_write_sniff_ranges(u16 addr, u16 len)
return _FALSE;
}
struct rf_sniff_ent {
u8 path;
u16 reg;
u32 mask;
};
struct rf_sniff_ent rf_read_sniff_ranges[] = {
/* example for all path addr 0x55 with all RF Reg mask */
/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
};
struct rf_sniff_ent rf_write_sniff_ranges[] = {
/* example for all path addr 0x55 with all RF Reg mask */
/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
};
int rf_read_sniff_num = sizeof(rf_read_sniff_ranges)/sizeof(struct rf_sniff_ent);
int rf_write_sniff_num = sizeof(rf_write_sniff_ranges)/sizeof(struct rf_sniff_ent);
bool match_rf_read_sniff_ranges(u8 path, u32 addr, u32 mask)
{
int i;
for (i = 0; i < rf_read_sniff_num; i++) {
if (rf_read_sniff_ranges[i].path == MAX_RF_PATH || rf_read_sniff_ranges[i].path == path)
if (addr == rf_read_sniff_ranges[i].reg && (mask & rf_read_sniff_ranges[i].mask))
return _TRUE;
}
return _FALSE;
}
bool match_rf_write_sniff_ranges(u8 path, u32 addr, u32 mask)
{
int i;
for (i = 0; i < rf_write_sniff_num; i++) {
if (rf_write_sniff_ranges[i].path == MAX_RF_PATH || rf_write_sniff_ranges[i].path == path)
if (addr == rf_write_sniff_ranges[i].reg && (mask & rf_write_sniff_ranges[i].mask))
return _TRUE;
}
return _FALSE;
}
u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u8 val = _rtw_read8(adapter, addr);
@ -508,6 +661,77 @@ int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const cha
return _rtw_writeN(adapter, addr, length, data);
}
#ifdef CONFIG_SDIO_HCI
u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u8 val = _rtw_sd_f0_read8(adapter, addr);
#if 0
if (match_read_sniff_ranges(addr, 1))
DBG_871X("DBG_IO %s:%d rtw_sd_f0_read8(0x%04x) return 0x%02x\n", caller, line, addr, val);
#endif
return val;
}
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u8 val = rtw_sd_iread8(adapter, addr);
if (match_read_sniff_ranges(addr, 1))
DBG_871X("DBG_IO %s:%d rtw_sd_iread8(0x%04x) return 0x%02x\n", caller, line, addr, val);
return val;
}
u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u16 val = _rtw_sd_iread16(adapter, addr);
if (match_read_sniff_ranges(addr, 2))
DBG_871X("DBG_IO %s:%d rtw_sd_iread16(0x%04x) return 0x%04x\n", caller, line, addr, val);
return val;
}
u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u32 val = _rtw_sd_iread32(adapter, addr);
if (match_read_sniff_ranges(addr, 4))
DBG_871X("DBG_IO %s:%d rtw_sd_iread32(0x%04x) return 0x%08x\n", caller, line, addr, val);
return val;
}
int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 1))
DBG_871X("DBG_IO %s:%d rtw_sd_iwrite8(0x%04x, 0x%02x)\n", caller, line, addr, val);
return _rtw_sd_iwrite8(adapter, addr, val);
}
int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 2))
DBG_871X("DBG_IO %s:%d rtw_sd_iwrite16(0x%04x, 0x%04x)\n", caller, line, addr, val);
return _rtw_sd_iwrite16(adapter, addr, val);
}
int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 4))
DBG_871X("DBG_IO %s:%d rtw_sd_iwrite32(0x%04x, 0x%08x)\n", caller, line, addr, val);
return _rtw_sd_iwrite32(adapter, addr, val);
}
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
#endif

2
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_ioctl_query.c Executable file → Normal file
View File

@ -82,7 +82,7 @@ u8 query_802_11_association_information( _adapter *padapter,PNDIS_802_11_ASSOCIA
struct wlan_network *tgt_network;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct security_priv *psecuritypriv=&(padapter->securitypriv);
WLAN_BSSID_EX *psecnetwork=(WLAN_BSSID_EX*)&(psecuritypriv->sec_bss);
WLAN_BSSID_EX *psecnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
u8 * pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
unsigned char i,*auth_ie,*supp_ie;

6
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_ioctl_rtl.c Executable file → Normal file
View File

@ -492,7 +492,6 @@ NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv)
{
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
struct eeprom_priv* peeprompriv = &padapter->eeprompriv;
if(poid_par_priv->type_of_oid != QUERY_OID)
{
@ -500,7 +499,7 @@ NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv)
return status;
}
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
*(u16 *)poid_par_priv->information_buf = peeprompriv->channel_plan ;
*(u16 *)poid_par_priv->information_buf = padapter->mlmepriv.ChannelPlan ;
return status;
}
@ -508,7 +507,6 @@ NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv)
{
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
struct eeprom_priv* peeprompriv = &padapter->eeprompriv;
if(poid_par_priv->type_of_oid != SET_OID)
{
@ -516,7 +514,7 @@ NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv)
return status;
}
peeprompriv->channel_plan = *(u16 *)poid_par_priv->information_buf ;
padapter->mlmepriv.ChannelPlan = *(u16 *)poid_par_priv->information_buf ;
return status;
}

70
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_ioctl_set.c Executable file → Normal file
View File

@ -20,6 +20,7 @@
#define _RTW_IOCTL_SET_C_
#include <drv_types.h>
#include <hal_data.h>
extern void indicate_wx_scan_complete_event(_adapter *padapter);
@ -159,9 +160,8 @@ _func_enter_;
rtw_generate_random_ibss(pibss);
if(rtw_createbss_cmd(padapter)!=_SUCCESS)
{
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("***Error=>do_goin: rtw_createbss_cmd status FAIL*** \n "));
if (rtw_create_ibss_cmd(padapter, 0) != _SUCCESS) {
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("***Error=>do_goin: rtw_create_ibss_cmd status FAIL***\n"));
ret = _FALSE;
goto exit;
}
@ -361,7 +361,7 @@ _func_enter_;
rtw_disassoc_cmd(padapter, 0, _TRUE);
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
rtw_indicate_disconnect(padapter);
rtw_indicate_disconnect(padapter, 0, _FALSE);
rtw_free_assoc_resources(padapter, 1);
@ -415,7 +415,7 @@ _func_enter_;
DBG_871X_LEVEL(_drv_always_, "set ssid [%s] fw_state=0x%08x\n",
ssid->Ssid, get_fwstate(pmlmepriv));
if(padapter->hw_init_completed==_FALSE){
if (!rtw_is_hw_init_completed(padapter)) {
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("set_ssid: hw_init_completed==_FALSE=>exit!!!\n"));
status = _FAIL;
@ -451,7 +451,7 @@ _func_enter_;
rtw_disassoc_cmd(padapter, 0, _TRUE);
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
rtw_indicate_disconnect(padapter);
rtw_indicate_disconnect(padapter, 0, _FALSE);
rtw_free_assoc_resources(padapter, 1);
@ -480,7 +480,7 @@ _func_enter_;
rtw_disassoc_cmd(padapter, 0, _TRUE);
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
rtw_indicate_disconnect(padapter);
rtw_indicate_disconnect(padapter, 0, _FALSE);
rtw_free_assoc_resources(padapter, 1);
@ -549,7 +549,7 @@ _func_enter_;
goto exit;
}
if(padapter->hw_init_completed==_FALSE){
if (!rtw_is_hw_init_completed(padapter)) {
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("set_ssid: hw_init_completed==_FALSE=>exit!!!\n"));
status = _FAIL;
@ -644,7 +644,7 @@ _func_enter_;
{
if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
{
rtw_indicate_disconnect(padapter); //will clr Linked_state; before this function, we must have chked whether issue dis-assoc_cmd or not
rtw_indicate_disconnect(padapter, 0, _FALSE); /*will clr Linked_state; before this function, we must have checked whether issue dis-assoc_cmd or not*/
}
}
@ -673,7 +673,10 @@ _func_enter_;
case Ndis802_11AutoUnknown:
case Ndis802_11InfrastructureMax:
break;
break;
case Ndis802_11Monitor:
set_fwstate(pmlmepriv, WIFI_MONITOR_STATE);
break;
}
//SecClearAllKeys(adapter);
@ -704,7 +707,7 @@ _func_enter_;
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_disassociate: rtw_indicate_disconnect\n"));
rtw_disassoc_cmd(padapter, 0, _TRUE);
rtw_indicate_disconnect(padapter);
rtw_indicate_disconnect(padapter, 0, _FALSE);
//modify for CONFIG_IEEE80211W, none 11w can use it
rtw_free_assoc_resources_cmd(padapter);
if (_FAIL == rtw_pwr_wakeup(padapter))
@ -732,7 +735,7 @@ _func_enter_;
res=_FALSE;
goto exit;
}
if (padapter->hw_init_completed==_FALSE){
if (!rtw_is_hw_init_completed(padapter)) {
res = _FALSE;
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n===rtw_set_802_11_bssid_list_scan:hw_init_completed==_FALSE===\n"));
goto exit;
@ -996,8 +999,8 @@ _func_enter_;
}
}
// Check key length for WEP. For NDTEST, 2005.01.27, by rcnjko.
if( (encryptionalgo== _WEP40_|| encryptionalgo== _WEP104_) && (key->KeyLength != 5 || key->KeyLength != 13)) {
/* Check key length for WEP. For NDTEST, 2005.01.27, by rcnjko. -> modify checking condition*/
if (((encryptionalgo == _WEP40_) && (key->KeyLength != 5)) || ((encryptionalgo == _WEP104_) && (key->KeyLength != 13))) {
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("WEP KeyLength:0x%x != 5 or 13\n", key->KeyLength));
ret=_FAIL;
goto exit;
@ -1252,16 +1255,22 @@ _func_enter_;
//Set key to CAM through H2C command
#if 0
if(bgrouptkey)//never go to here
{
res=rtw_setstakey_cmd(padapter, stainfo, _FALSE, _TRUE);
res=rtw_setstakey_cmd(padapter, stainfo, GROUP_KEY, _TRUE);
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(group)\n"));
}
else{
res=rtw_setstakey_cmd(padapter, stainfo, _TRUE, _TRUE);
res=rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE);
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n"));
}
#else
res = rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE);
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n"));
#endif
if(res ==_FALSE)
ret= _FAIL;
@ -1428,7 +1437,7 @@ int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan)
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
//handle by cmd_thread to sync with scan operation
return rtw_set_chplan_cmd(adapter, channel_plan, 1, 1);
return rtw_set_chplan_cmd(adapter, RTW_CMDF_WAIT_ACK, channel_plan, 1);
}
/*
@ -1440,26 +1449,11 @@ int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan)
*/
int rtw_set_country(_adapter *adapter, const char *country_code)
{
int channel_plan = RT_CHANNEL_DOMAIN_WORLD_WIDE_5G;
DBG_871X("%s country_code:%s\n", __func__, country_code);
//TODO: should have a table to match country code and RT_CHANNEL_DOMAIN
//TODO: should consider 2-character and 3-character country code
if(0 == strcmp(country_code, "US"))
channel_plan = RT_CHANNEL_DOMAIN_FCC;
else if(0 == strcmp(country_code, "EU"))
channel_plan = RT_CHANNEL_DOMAIN_ETSI;
else if(0 == strcmp(country_code, "JP"))
channel_plan = RT_CHANNEL_DOMAIN_MKK;
else if(0 == strcmp(country_code, "CN"))
channel_plan = RT_CHANNEL_DOMAIN_CHINA;
else if(0 == strcmp(country_code, "IN"))
channel_plan = RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN;
else
DBG_871X("%s unknown country_code:%s\n", __FUNCTION__, country_code);
return rtw_set_channel_plan(adapter, channel_plan);
#ifdef CONFIG_RTW_IOCTL_SET_COUNTRY
return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1);
#else
return _FAIL;
#endif
}
/*
@ -1469,7 +1463,7 @@ int rtw_set_country(_adapter *adapter, const char *country_code)
*
* Return _SUCCESS or _FAIL
*/
int rtw_set_band(_adapter *adapter, enum _BAND band)
int rtw_set_band(_adapter *adapter, u8 band)
{
if (rtw_band_valid(band)) {
DBG_871X(FUNC_ADPT_FMT" band:%d\n", FUNC_ADPT_ARG(adapter), band);

0
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_iol.c Executable file → Normal file
View File

29
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_mem.c Executable file → Normal file
View File

@ -16,10 +16,28 @@ struct u8 * rtw_get_buf_premem(int index)
return rtk_buf_mem[index];
}
struct sk_buff *rtw_alloc_skb_premem(void)
u16 rtw_rtkm_get_buff_size(void)
{
return MAX_RTKM_RECVBUF_SZ;
}
EXPORT_SYMBOL(rtw_rtkm_get_buff_size);
u8 rtw_rtkm_get_nr_recv_skb(void)
{
return MAX_RTKM_NR_PREALLOC_RECV_SKB;
}
EXPORT_SYMBOL(rtw_rtkm_get_nr_recv_skb);
struct sk_buff *rtw_alloc_skb_premem(u16 in_size)
{
struct sk_buff *skb = NULL;
if (in_size > MAX_RTKM_RECVBUF_SZ) {
pr_info("warning %s: driver buffer size(%d) > rtkm buffer size(%d)\n", __func__, in_size, MAX_RTKM_RECVBUF_SZ);
WARN_ON(1);
return skb;
}
skb = skb_dequeue(&rtk_skb_mem_q);
printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
@ -33,7 +51,7 @@ int rtw_free_skb_premem(struct sk_buff *pskb)
if(!pskb)
return -1;
if(skb_queue_len(&rtk_skb_mem_q) >= NR_PREALLOC_RECV_SKB)
if (skb_queue_len(&rtk_skb_mem_q) >= MAX_RTKM_NR_PREALLOC_RECV_SKB)
return -1;
skb_queue_tail(&rtk_skb_mem_q, pskb);
@ -52,6 +70,8 @@ static int __init rtw_mem_init(void)
struct sk_buff *pskb=NULL;
printk("%s\n", __func__);
pr_info("MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", MAX_RTKM_NR_PREALLOC_RECV_SKB);
pr_info("MAX_RTKM_RECVBUF_SZ: %d\n", MAX_RTKM_RECVBUF_SZ);
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
for(i=0; i<NR_RECVBUFF; i++)
@ -62,9 +82,9 @@ static int __init rtw_mem_init(void)
skb_queue_head_init(&rtk_skb_mem_q);
for(i=0; i<NR_PREALLOC_RECV_SKB; i++)
for(i=0; i<MAX_RTKM_NR_PREALLOC_RECV_SKB; i++)
{
pskb = __dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
pskb = __dev_alloc_skb(MAX_RTKM_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
if(pskb)
{
tmpaddr = (SIZE_PTR)pskb->data;
@ -100,4 +120,3 @@ static void __exit rtw_mem_exit(void)
module_init(rtw_mem_init);
module_exit(rtw_mem_exit);

1042
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_mlme.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

6788
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_mlme_ext.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

1767
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_mp.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

4
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_mp_ioctl.c Executable file → Normal file
View File

@ -21,7 +21,7 @@
#include <drv_types.h>
#include <rtw_mp_ioctl.h>
#include "../hal/OUTSRC/phydm_precomp.h"
#include "../hal/phydm/phydm_precomp.h"
//**************** oid_rtl_seg_81_85 section start ****************
NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv)
@ -2237,8 +2237,6 @@ NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv)
RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d \n",\
Adapter->mppriv.rx_with_status));
//*(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050);
//*(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054);
RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n",
Adapter->eeprompriv.mac_addr[0],Adapter->eeprompriv.mac_addr[1],Adapter->eeprompriv.mac_addr[2],\
Adapter->eeprompriv.mac_addr[3],Adapter->eeprompriv.mac_addr[4],Adapter->eeprompriv.mac_addr[5]));

253
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_odm.c Executable file → Normal file
View File

@ -40,23 +40,24 @@ const char *odm_comp_str[] = {
/* BIT15 */"ODM_COMP_CFO_TRACKING",
/* BIT16 */"ODM_COMP_ACS",
/* BIT17 */"PHYDM_COMP_ADAPTIVITY",
/* BIT18 */NULL,
/* BIT19 */NULL,
/* BIT18 */"PHYDM_COMP_RA_DBG",
/* BIT19 */"PHYDM_COMP_TXBF",
/* BIT20 */"ODM_COMP_EDCA_TURBO",
/* BIT21 */"ODM_COMP_EARLY_MODE",
/* BIT22 */NULL,
/* BIT22 */"ODM_FW_DEBUG_TRACE",
/* BIT23 */NULL,
/* BIT24 */"ODM_COMP_TX_PWR_TRACK",
/* BIT25 */"ODM_COMP_RX_GAIN_TRACK",
/* BIT26 */"ODM_COMP_CALIBRATION",
/* BIT27 */NULL,
/* BIT28 */NULL,
/* BIT29 */NULL,
/* BIT28 */"ODM_PHY_CONFIG",
/* BIT29 */"BEAMFORMING_DEBUG",
/* BIT30 */"ODM_COMP_COMMON",
/* BIT31 */"ODM_COMP_INIT",
/* BIT32 */"ODM_COMP_NOISY_DETECT",
};
#define RTW_ODM_COMP_MAX 32
#define RTW_ODM_COMP_MAX 33
const char *odm_ability_str[] = {
/* BIT0 */"ODM_BB_DIG",
@ -76,7 +77,7 @@ const char *odm_ability_str[] = {
/* BIT14 */"ODM_BB_CFO_TRACKING",
/* BIT15 */"ODM_BB_NHM_CNT",
/* BIT16 */"ODM_BB_PRIMARY_CCA",
/* BIT17 */NULL,
/* BIT17 */"ODM_BB_TXBF",
/* BIT18 */NULL,
/* BIT19 */NULL,
/* BIT20 */"ODM_MAC_EDCA_TURBO",
@ -106,21 +107,22 @@ void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
int cnt = 0;
u64 dbg_comp;
u64 dbg_comp = 0;
int i;
rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp);
DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx \n", dbg_comp);
rtw_hal_get_odm_var(adapter, HAL_ODM_DBG_FLAG, &dbg_comp, NULL);
DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx\n", dbg_comp);
for (i=0;i<RTW_ODM_COMP_MAX;i++) {
if (odm_comp_str[i])
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
}
}
inline void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps)
{
rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &comps);
rtw_hal_set_odm_var(adapter, HAL_ODM_DBG_FLAG, &comps, _FALSE);
}
void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter)
@ -128,10 +130,10 @@ void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
int cnt = 0;
u32 dbg_level;
u32 dbg_level = 0;
int i;
rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level);
rtw_hal_get_odm_var(adapter, HAL_ODM_DBG_LEVEL, &dbg_level, NULL);
DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level);
for (i=0;i<RTW_ODM_DBG_LEVEL_NUM;i++) {
if (odm_dbg_level_str[i])
@ -141,7 +143,7 @@ void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter)
inline void rtw_odm_dbg_level_set(_adapter *adapter, u32 level)
{
rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &level);
rtw_hal_set_odm_var(adapter, HAL_ODM_DBG_LEVEL, &level, _FALSE);
}
void rtw_odm_ability_msg(void *sel, _adapter *adapter)
@ -152,18 +154,30 @@ void rtw_odm_ability_msg(void *sel, _adapter *adapter)
u32 ability = 0;
int i;
rtw_hal_get_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
ability = rtw_phydm_ability_get(adapter);
DBG_871X_SEL_NL(sel, "odm.SupportAbility = 0x%08x\n", ability);
for (i=0;i<RTW_ODM_ABILITY_MAX;i++) {
if (odm_ability_str[i])
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
}
}
inline void rtw_odm_ability_set(_adapter *adapter, u32 ability)
{
rtw_hal_set_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
rtw_phydm_ability_set(adapter, ability);
}
/* set ODM_CMNINFO_IC_TYPE based on chip_type */
void rtw_odm_init_ic_type(_adapter *adapter)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &hal_data->odmpriv;
u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
rtw_warn_on(!ic_type);
ODM_CmnInfoInit(odm, ODM_CMNINFO_IC_TYPE, ic_type);
}
void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
@ -173,7 +187,6 @@ void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
#define RTW_ADAPTIVITY_EN_DISABLE 0
#define RTW_ADAPTIVITY_EN_ENABLE 1
#define RTW_ADAPTIVITY_EN_AUTO 2
void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
{
@ -188,9 +201,6 @@ void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
DBG_871X_SEL(sel, "DISABLE\n");
} else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) {
DBG_871X_SEL(sel, "ENABLE\n");
} else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_AUTO) {
DBG_871X_SEL(sel, "AUTO, chplan:0x%02x, Regulation:%u,%u\n"
, mlme->ChannelPlan, odm->odm_Regulation2_4G, odm->odm_Regulation5G);
} else {
DBG_871X_SEL(sel, "INVALID\n");
}
@ -214,41 +224,49 @@ void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
}
}
#define RTW_NHM_EN_DISABLE 0
#define RTW_NHM_EN_ENABLE 1
#define RTW_ADAPTIVITY_DML_DISABLE 0
#define RTW_ADAPTIVITY_DML_ENABLE 1
void rtw_odm_nhm_en_msg(void *sel, _adapter *adapter)
void rtw_odm_adaptivity_dml_msg(void *sel, _adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
DBG_871X_SEL_NL(sel, "RTW_NHM_EN_");
DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_DML_");
if (regsty->nhm_en == RTW_NHM_EN_DISABLE) {
if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_DISABLE) {
DBG_871X_SEL(sel, "DISABLE\n");
} else if (regsty->nhm_en == RTW_NHM_EN_ENABLE) {
} else if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_ENABLE) {
DBG_871X_SEL(sel, "ENABLE\n");
} else {
DBG_871X_SEL(sel, "INVALID\n");
}
}
void rtw_odm_adaptivity_dc_backoff_msg(void *sel, _adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_DC_BACKOFF:%u\n", regsty->adaptivity_dc_backoff);
}
void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)
{
rtw_odm_adaptivity_ver_msg(sel, adapter);
rtw_odm_adaptivity_en_msg(sel, adapter);
rtw_odm_adaptivity_mode_msg(sel, adapter);
rtw_odm_adaptivity_dml_msg(sel, adapter);
rtw_odm_adaptivity_dc_backoff_msg(sel, adapter);
}
bool rtw_odm_adaptivity_needed(_adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
struct mlme_priv *mlme = &adapter->mlmepriv;
bool ret = _FALSE;
if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE
|| regsty->adaptivity_en == RTW_ADAPTIVITY_EN_AUTO)
if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
ret = _TRUE;
if (ret == _TRUE) {
rtw_odm_adaptivity_ver_msg(RTW_DBGDUMP, adapter);
rtw_odm_adaptivity_en_msg(RTW_DBGDUMP, adapter);
rtw_odm_adaptivity_mode_msg(RTW_DBGDUMP, adapter);
rtw_odm_nhm_en_msg(RTW_DBGDUMP, adapter);
}
return ret;
}
@ -257,43 +275,35 @@ void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
rtw_odm_adaptivity_ver_msg(sel, adapter);
rtw_odm_adaptivity_en_msg(sel, adapter);
rtw_odm_adaptivity_mode_msg(sel, adapter);
rtw_odm_nhm_en_msg(sel, adapter);
rtw_odm_adaptivity_config_msg(sel, adapter);
DBG_871X_SEL_NL(sel, "%10s %16s %8s %10s %11s %14s\n"
, "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound");
DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n"
DBG_871X_SEL_NL(sel, "%10s %16s %16s %22s %12s\n"
, "TH_L2H_ini", "TH_EDCCA_HL_diff", "TH_L2H_ini_mode2", "TH_EDCCA_HL_diff_mode2", "EDCCA_enable");
DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-14x %-22d %-12d\n"
, (u8)odm->TH_L2H_ini
, odm->TH_EDCCA_HL_diff
, odm->IGI_Base
, odm->ForceEDCCA
, odm->AdapEn_RSSI
, odm->IGI_LowerBound
, (u8)odm->TH_L2H_ini_mode2
, odm->TH_EDCCA_HL_diff_mode2
, odm->EDCCA_enable
);
DBG_871X_SEL_NL(sel, "%8s %9s\n", "EDCCA_ES","Adap_Flag");
DBG_871X_SEL_NL(sel, "%-8x %-9x \n"
, odm->EDCCA_enable_state
DBG_871X_SEL_NL(sel, "%15s %9s\n", "AdapEnableState", "Adap_Flag");
DBG_871X_SEL_NL(sel, "%-15x %-9x\n"
, odm->Adaptivity_enable
, odm->adaptivity_flag
);
}
void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, s8 TH_L2H_ini_mode2, s8 TH_EDCCA_HL_diff_mode2, u8 EDCCA_enable)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
odm->TH_L2H_ini = TH_L2H_ini;
odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
odm->IGI_Base = IGI_Base;
odm->ForceEDCCA = ForceEDCCA;
odm->AdapEn_RSSI = AdapEn_RSSI;
odm->IGI_LowerBound = IGI_LowerBound;
odm->TH_L2H_ini_mode2 = TH_L2H_ini_mode2;
odm->TH_EDCCA_HL_diff_mode2 = TH_EDCCA_HL_diff_mode2;
odm->EDCCA_enable = EDCCA_enable;
}
void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
@ -309,13 +319,12 @@ void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
_irqL irqL;
switch(type)
{
case RT_IQK_SPINLOCK:
_enter_critical_bh(&pdmpriv->IQKSpinLock, &irqL);
_enter_critical_bh(&pHalData->IQKSpinLock, &irqL);
default:
break;
}
@ -324,15 +333,129 @@ void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
_irqL irqL;
switch(type)
{
case RT_IQK_SPINLOCK:
_exit_critical_bh(&pdmpriv->IQKSpinLock, &irqL);
_exit_critical_bh(&pHalData->IQKSpinLock, &irqL);
default:
break;
}
}
#ifdef CONFIG_DFS_MASTER
VOID rtw_odm_radar_detect_reset(_adapter *adapter)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
PDM_ODM_T pDM_Odm = &(hal_data->odmpriv);
if (pDM_Odm->SupportICType & ODM_RTL8192D) {
ODM_SetBBReg(pDM_Odm, 0xc84 , BIT25, 0);
ODM_SetBBReg(pDM_Odm, 0xc84 , BIT25, 1);
} else if (pDM_Odm->SupportICType & ODM_RTL8821) {
ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0);
ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 1);
} else {
/* not supported yet */
rtw_warn_on(1);
}
}
VOID rtw_odm_radar_detect_disable(_adapter *adapter)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
PDM_ODM_T pDM_Odm = &(hal_data->odmpriv);
if (pDM_Odm->SupportICType & ODM_RTL8192D)
ODM_SetBBReg(pDM_Odm, 0xc84 , BIT25, 0);
else if (pDM_Odm->SupportICType & ODM_RTL8821)
ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0);
else
rtw_warn_on(1);
}
/* called after ch, bw is set, chance to adjust parameter for different ch conditions */
VOID rtw_odm_radar_detect_enable(_adapter *adapter)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
PDM_ODM_T pDM_Odm = &(hal_data->odmpriv);
if (pDM_Odm->SupportICType & ODM_RTL8192D) {
ODM_SetBBReg(pDM_Odm, 0xc38, BIT23 | BIT22, 2);
ODM_SetBBReg(pDM_Odm, 0x814, bMaskDWord, 0x04cc4d10);
ODM_SetBBReg(pDM_Odm, 0xc8c, BIT23 | BIT22, 3);
ODM_SetBBReg(pDM_Odm, 0xc30, 0xf, 0xa);
ODM_SetBBReg(pDM_Odm, 0xcdc, 0xf0000, 4);
} else if (pDM_Odm->SupportICType & ODM_RTL8821) {
ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10);
ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06);
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16ecdf);
ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x0152a400);
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0fa21a20);
ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0f57204);
} else {
/* not supported yet */
rtw_warn_on(1);
}
rtw_odm_radar_detect_reset(adapter);
}
BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
PDM_ODM_T pDM_Odm = &(hal_data->odmpriv);
BOOLEAN enable_DFS = FALSE;
BOOLEAN bypass = FALSE;
BOOLEAN radar_detected = FALSE;
static u8Byte last_tx_unicast = 0;
static u8Byte last_rx_unicast = 0;
static u8Byte throughput = 0;
int tp_th = ((*pDM_Odm->pBandWidth == ODM_BW40M) ? 45 : 20); /*refer AP team's testing number*/
throughput = (*(pDM_Odm->pNumTxBytesUnicast) - last_tx_unicast) + (*(pDM_Odm->pNumRxBytesUnicast) - last_rx_unicast);
last_tx_unicast = *(pDM_Odm->pNumTxBytesUnicast);
last_rx_unicast = *(pDM_Odm->pNumRxBytesUnicast);
if (throughput>>18 > tp_th) {
if (pDM_Odm->SupportICType & ODM_RTL8192D)
ODM_SetBBReg(pDM_Odm, 0xcdc, BIT8|BIT9, 0);
bypass = TRUE;
} else {
if (pDM_Odm->SupportICType & ODM_RTL8192D)
ODM_SetBBReg(pDM_Odm, 0xcdc, BIT8|BIT9, 1);
}
if (pDM_Odm->SupportICType & ODM_RTL8192D) {
if (ODM_GetBBReg(pDM_Odm , 0xc84, BIT25))
enable_DFS = TRUE;
} else if (pDM_Odm->SupportICType & ODM_RTL8821) {
if (ODM_GetBBReg(pDM_Odm , 0x924, BIT15))
enable_DFS = TRUE;
}
if (pDM_Odm->SupportICType & ODM_RTL8192D) {
if (ODM_GetBBReg(pDM_Odm , 0xcf8, BIT23))
radar_detected = TRUE;
} else if (pDM_Odm->SupportICType & ODM_RTL8821) {
if (ODM_GetBBReg(pDM_Odm , 0xf98, BIT17))
radar_detected = TRUE;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD
, ("Radar detect: enable_DFS:%d, radar_detected:%d, bypass:%d\n"
, enable_DFS, radar_detected, bypass));
if (0)
DBG_871X("Radar detect: enable_DFS:%d, radar_detected:%d, bypass:%d(throughput:%llu, tp_th:%d)\n"
, enable_DFS, radar_detected, bypass, throughput, tp_th);
if (enable_DFS && radar_detected)
rtw_odm_radar_detect_reset(adapter);
exit:
return (enable_DFS && radar_detected && !bypass);
}
#endif /* CONFIG_DFS_MASTER */

698
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_p2p.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

311
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_pwrctrl.c Executable file → Normal file
View File

@ -38,10 +38,11 @@ int rtw_fw_ps_state(PADAPTER padapter)
_enter_pwrlock(&pwrpriv->check_32k_lock);
if ((padapter->bSurpriseRemoved == _TRUE))
{
DBG_871X("%s: bSurpriseRemoved=%d , hw_init_completed=%d, bDriverStopped=%d \n", __FUNCTION__, padapter->bSurpriseRemoved,
padapter->hw_init_completed,padapter->bDriverStopped);
if (RTW_CANNOT_RUN(padapter)) {
DBG_871X("%s: bSurpriseRemoved=%s , hw_init_completed=%d, bDriverStopped=%s\n", __func__
, rtw_is_surprise_removed(padapter)?"True":"False"
, rtw_get_hw_init_completed(padapter)
, rtw_is_drv_stopped(padapter)?"True":"False");
goto exit_fw_ps_state;
}
rtw_hal_set_hwreg(padapter, HW_VAR_SET_REQ_FW_PS, (u8 *)&dont_care);
@ -210,7 +211,7 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter)
|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS)
|| check_fwstate(pmlmepriv, WIFI_AP_STATE)
|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE)
#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P_IPS)
#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
|| pcfg80211_wdinfo->is_ro_ch
#elif defined(CONFIG_P2P)
|| !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
@ -236,7 +237,7 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter)
|| check_fwstate(b_pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS)
|| check_fwstate(b_pmlmepriv, WIFI_AP_STATE)
|| check_fwstate(b_pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE)
#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P_IPS)
#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
|| b_pcfg80211_wdinfo->is_ro_ch
#elif defined(CONFIG_P2P)
|| !rtw_p2p_chk_state(b_pwdinfo, P2P_STATE_NONE)
@ -354,7 +355,6 @@ void rtw_ps_processor(_adapter*padapter)
{
pwrpriv->change_rfpwrstate = rf_off;
pwrpriv->brfoffbyhw = _TRUE;
padapter->bCardDisableWOHSM = _TRUE;
rtw_hw_suspend(padapter );
}
else
@ -396,12 +396,10 @@ void rtw_ps_processor(_adapter*padapter)
DBG_871X("<==%s .pwrpriv->bInternalAutoSuspend)(%x)\n",__FUNCTION__,pwrpriv->bInternalAutoSuspend);
} else {
pwrpriv->change_rfpwrstate = rf_off;
padapter->bCardDisableWOHSM = _TRUE;
DBG_871X("<==%s .pwrpriv->bInternalAutoSuspend)(%x) call autosuspend_enter\n",__FUNCTION__,pwrpriv->bInternalAutoSuspend);
autosuspend_enter(padapter);
}
#else
padapter->bCardDisableWOHSM = _TRUE;
autosuspend_enter(padapter);
#endif //if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND)
}
@ -532,9 +530,7 @@ _func_enter_;
{
if ( (pwrpriv->rpwm == pslv)
#ifdef CONFIG_LPS_LCLK
#ifndef CONFIG_RTL8723A
|| ((pwrpriv->rpwm >= PS_STATE_S2)&&(pslv >= PS_STATE_S2))
#endif
#endif
)
{
@ -544,20 +540,21 @@ _func_enter_;
}
}
if ((padapter->bSurpriseRemoved == _TRUE) ||
(padapter->hw_init_completed == _FALSE))
if (rtw_is_surprise_removed(padapter) ||
(!rtw_is_hw_init_completed(padapter)))
{
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
("%s: SurpriseRemoved(%d) hw_init_completed(%d)\n",
__FUNCTION__, padapter->bSurpriseRemoved, padapter->hw_init_completed));
("%s: SurpriseRemoved(%s) hw_init_completed(%s)\n"
, __func__
, rtw_is_surprise_removed(padapter)?"True":"False"
, rtw_is_hw_init_completed(padapter)?"True":"False"));
pwrpriv->cpwm = PS_STATE_S4;
return;
}
if (padapter->bDriverStopped == _TRUE)
{
if (rtw_is_drv_stopped(padapter)) {
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
("%s: change power state(0x%02X) when DriverStopped\n", __FUNCTION__, pslv));
@ -610,14 +607,11 @@ _func_enter_;
do {
rtw_msleep_os(1);
poll_cnt++;
cpwm_now = 0;
rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
if ((cpwm_orig ^ cpwm_now) & 0x80)
{
#ifdef CONFIG_RTL8723A
pwrpriv->cpwm = PS_STATE(cpwm_now);
#else // !CONFIG_RTL8723A
pwrpriv->cpwm = PS_STATE_S4;
#endif // !CONFIG_RTL8723A
pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE;
#ifdef DBG_CHECK_FW_PS_STATE
DBG_871X("%s: polling cpwm OK! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n"
@ -695,7 +689,7 @@ u8 PS_RDY_CHECK(_adapter * padapter)
|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS)
|| check_fwstate(pmlmepriv, WIFI_AP_STATE)
|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE)
#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P_IPS)
#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
|| pcfg80211_wdinfo->is_ro_ch
#elif defined(CONFIG_P2P)
|| !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
@ -722,15 +716,14 @@ u8 PS_RDY_CHECK(_adapter * padapter)
return _TRUE;
}
#if defined(CONFIG_FWLPS_IN_IPS) && defined(CONFIG_PNO_SUPPORT)
#if defined(CONFIG_FWLPS_IN_IPS)
void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
{
struct hal_ops *pHalFunc = &padapter->HalFunc;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
int cnt=0;
u32 start_time;
u8 val8 = 0;
u8 cpwm_orig, cpwm_now;
u8 cpwm_orig = 0, cpwm_now = 0;
u8 parm[H2C_INACTIVE_PS_LEN]={0};
if (padapter->netif_up == _FALSE) {
@ -738,23 +731,25 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
return;
}
if (pHalFunc->fill_h2c_cmd == NULL) {
DBG_871X("%s: Please hook fill_h2c_cmd first!\n", __func__);
return;
}
//u8 cmd_param; //BIT0:enable, BIT1:NoConnect32k
if (enable) {
#ifdef CONFIG_BT_COEXIST
rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req);
#endif
//Enter IPS
DBG_871X("%s: issue H2C to FW when entering IPS\n", __func__);
#ifdef CONFIG_PNO_SUPPORT
parm[0] = 0x03;
parm[1] = 0x01;
parm[2] = 0x01;
pHalFunc->fill_h2c_cmd(padapter, //H2C_FWLPS_IN_IPS_,
parm[1] = pwrpriv->pnlo_info->fast_scan_iterations;
parm[2] = pwrpriv->pnlo_info->slow_scan_period;
#else
parm[0] = 0x03;
parm[1] = 0x0;
parm[2] = 0x0;
#endif//CONFIG_PNO_SUPPORT
rtw_hal_fill_h2c_cmd(padapter, //H2C_FWLPS_IN_IPS_,
H2C_INACTIVE_PS_,
H2C_INACTIVE_PS_LEN, parm);
//poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW.
@ -777,33 +772,18 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
DBG_871X("%s: write rpwm=%02x\n", __FUNCTION__, val8);
adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
cnt = val8 = 0;
do {
val8 = rtw_read8(padapter, REG_CR);
cnt++;
DBG_871X("%s polling 0x100=0x%x, cnt=%d \n",
__func__, val8, cnt);
DBG_871X("%s 0x08:%02x, 0x03:%02x\n",
__func__,
rtw_read8(padapter, 0x08),
rtw_read8(padapter, 0x03));
rtw_mdelay_os(10);
} while(cnt<20 && (val8!=0xEA));
#ifdef DBG_CHECK_FW_PS_STATE
if(val8 != 0xEA) {
DBG_871X("MAC_1B8=0x%08x\n",
rtw_read32(padapter, 0x1b8));
DBG_871X("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n",
rtw_read32(padapter, 0x1c0),
rtw_read32(padapter, 0x1c4),
rtw_read32(padapter, 0x1c8),
rtw_read32(padapter, 0x1cc));
#endif //DBG_CHECK_FW_PS_STATE
} else {
DBG_871X("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n",
rtw_read32(padapter, 0x1c0),
rtw_read32(padapter, 0x1c4),
rtw_read32(padapter, 0x1c8),
rtw_read32(padapter, 0x1cc));
if (parm[1] == 0 || parm[2] == 0) {
do {
val8 = rtw_read8(padapter, REG_CR);
cnt++;
DBG_871X("%s polling 0x100=0x%x, cnt=%d \n",
__func__, val8, cnt);
DBG_871X("%s 0x08:%02x, 0x03:%02x\n",
__func__,
rtw_read8(padapter, 0x08),
rtw_read8(padapter, 0x03));
rtw_mdelay_os(10);
} while(cnt<20 && (val8!=0xEA));
}
}
} else {
@ -831,10 +811,6 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
if ((cpwm_orig ^ cpwm_now) & 0x80) {
#ifdef DBG_CHECK_FW_PS_STATE
DBG_871X("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x \n"
, __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
#endif //DBG_CHECK_FW_PS_STATE
break;
}
@ -848,7 +824,7 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
parm[0] = 0x0;
parm[1] = 0x0;
parm[2] = 0x0;
pHalFunc->fill_h2c_cmd(padapter, H2C_INACTIVE_PS_,
rtw_hal_fill_h2c_cmd(padapter, H2C_INACTIVE_PS_,
H2C_INACTIVE_PS_LEN, parm);
#ifdef CONFIG_BT_COEXIST
rtw_btcoex_IpsNotify(padapter, IPS_NONE);
@ -924,9 +900,11 @@ _func_enter_;
DBG_871X(FUNC_ADPT_FMT" Leave 802.11 power save - %s\n",
FUNC_ADPT_ARG(padapter), msg);
if (pwrpriv->lps_leave_cnts < UINT_MAX)
pwrpriv->lps_leave_cnts++;
else
pwrpriv->lps_leave_cnts = 0;
#ifdef CONFIG_TDLS
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for(i=0; i< NUM_STA; i++)
{
phead = &(pstapriv->sta_hash[i]);
@ -941,8 +919,6 @@ _func_enter_;
plist = get_next(plist);
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
#endif //CONFIG_TDLS
pwrpriv->pwr_mode = ps_mode;
@ -999,9 +975,11 @@ _func_enter_;
DBG_871X(FUNC_ADPT_FMT" Enter 802.11 power save - %s\n",
FUNC_ADPT_ARG(padapter), msg);
if (pwrpriv->lps_enter_cnts < UINT_MAX)
pwrpriv->lps_enter_cnts++;
else
pwrpriv->lps_enter_cnts = 0;
#ifdef CONFIG_TDLS
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for(i=0; i< NUM_STA; i++)
{
phead = &(pstapriv->sta_hash[i]);
@ -1016,8 +994,6 @@ _func_enter_;
plist = get_next(plist);
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
#endif //CONFIG_TDLS
#ifdef CONFIG_BT_COEXIST
@ -1052,19 +1028,6 @@ _func_enter_;
if (val8 & BIT(4))
pslv = PS_STATE_S2;
#ifdef CONFIG_RTL8723A
val8 = rtw_btcoex_RpwmVal(padapter);
switch (val8)
{
case 0x4:
pslv = PS_STATE_S3;
break;
case 0xC:
pslv = PS_STATE_S4;
break;
}
#endif // CONFIG_RTL8723A
}
#endif // CONFIG_BT_COEXIST
@ -1099,8 +1062,7 @@ s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms)
if (_TRUE == bAwake)
break;
if (_TRUE == padapter->bSurpriseRemoved)
{
if (rtw_is_surprise_removed(padapter)) {
err = -2;
DBG_871X("%s: device surprise removed!!\n", __FUNCTION__);
break;
@ -1252,10 +1214,8 @@ _func_enter_;
DBG_871X("%s.....\n",__FUNCTION__);
if (_TRUE == Adapter->bSurpriseRemoved)
{
DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved=%d Skip!\n",
FUNC_ADPT_ARG(Adapter), Adapter->bSurpriseRemoved);
if (rtw_is_surprise_removed(Adapter)) {
DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter));
return;
}
@ -1291,11 +1251,7 @@ _func_enter_;
rtw_hal_get_hwreg(Adapter, HW_VAR_CPWM, &cpwm_now);
if ((cpwm_orig ^ cpwm_now) & 0x80)
{
#ifdef CONFIG_RTL8723A
pwrpriv->cpwm = PS_STATE(cpwm_now);
#else // !CONFIG_RTL8723A
pwrpriv->cpwm = PS_STATE_S4;
#endif // !CONFIG_RTL8723A
pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE;
#ifdef DBG_CHECK_FW_PS_STATE
DBG_871X("%s: polling cpwm OK! cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x \n"
@ -1389,10 +1345,8 @@ _func_enter_;
return;
}
if (_TRUE == Adapter->bSurpriseRemoved)
{
DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved=%d Skip!\n",
FUNC_ADPT_ARG(Adapter), Adapter->bSurpriseRemoved);
if (rtw_is_surprise_removed(Adapter)) {
DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter));
return;
}
@ -1471,10 +1425,10 @@ _func_enter_;
{
_enter_pwrlock(&pwrpriv->lock);
if ((padapter->bSurpriseRemoved == _TRUE)
|| (padapter->hw_init_completed == _FALSE)
if (rtw_is_surprise_removed(padapter)
|| (!rtw_is_hw_init_completed(padapter))
#ifdef CONFIG_USB_HCI
|| (padapter->bDriverStopped== _TRUE)
|| rtw_is_drv_stopped(padapter)
#endif
|| (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
)
@ -1559,7 +1513,7 @@ static void cpwm_event_callback(struct work_struct *work)
{
struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, cpwm_event);
struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
_adapter *adapter = dvobj->if1;
_adapter *adapter = dvobj->padapters[IFACE_ID0];
struct reportpwrstate_parm report;
//DBG_871X("%s\n",__FUNCTION__);
@ -1578,7 +1532,7 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work)
pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi);
dvobj = pwrctl_to_dvobj(pwrpriv);
padapter = dvobj->if1;
padapter = dvobj->padapters[IFACE_ID0];
// DBG_871X("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
_enter_pwrlock(&pwrpriv->lock);
@ -1680,24 +1634,6 @@ _func_enter_;
pwrctrl = adapter_to_pwrctl(padapter);
pslv = PS_STATE_S2;
#if defined(CONFIG_RTL8723A) && defined(CONFIG_BT_COEXIST)
if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
{
u8 btcoex_rpwm;
btcoex_rpwm = rtw_btcoex_RpwmVal(padapter);
switch (btcoex_rpwm)
{
case 0x4:
pslv = PS_STATE_S3;
break;
case 0xC:
pslv = PS_STATE_S4;
break;
}
}
#endif // CONFIG_RTL8723A & CONFIG_BT_COEXIST
_enter_pwrlock(&pwrctrl->lock);
register_task_alive(pwrctrl, task);
@ -1762,19 +1698,6 @@ _func_enter_;
if (val8 & BIT(4))
pslv = PS_STATE_S2;
#ifdef CONFIG_RTL8723A
val8 = rtw_btcoex_RpwmVal(padapter);
switch (val8)
{
case 0x4:
pslv = PS_STATE_S3;
break;
case 0xC:
pslv = PS_STATE_S4;
break;
}
#endif // CONFIG_RTL8723A
}
#endif // CONFIG_BT_COEXIST
@ -1826,24 +1749,6 @@ _func_enter_;
pwrctrl = adapter_to_pwrctl(padapter);
pslv = PS_STATE_S2;
#if defined(CONFIG_RTL8723A) && defined(CONFIG_BT_COEXIST)
if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
{
u8 btcoex_rpwm;
btcoex_rpwm = rtw_btcoex_RpwmVal(padapter);
switch (btcoex_rpwm)
{
case 0x4:
pslv = PS_STATE_S3;
break;
case 0xC:
pslv = PS_STATE_S4;
break;
}
}
#endif // CONFIG_RTL8723A & CONFIG_BT_COEXIST
_enter_pwrlock(&pwrctrl->lock);
register_task_alive(pwrctrl, XMIT_ALIVE);
@ -1903,24 +1808,6 @@ _func_enter_;
pwrctrl = adapter_to_pwrctl(padapter);
pslv = PS_STATE_S2;
#if defined(CONFIG_RTL8723A) && defined(CONFIG_BT_COEXIST)
if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
{
u8 btcoex_rpwm;
btcoex_rpwm = rtw_btcoex_RpwmVal(padapter);
switch (btcoex_rpwm)
{
case 0x4:
pslv = PS_STATE_S3;
break;
case 0xC:
pslv = PS_STATE_S4;
break;
}
}
#endif // CONFIG_RTL8723A & CONFIG_BT_COEXIST
_enter_pwrlock(&pwrctrl->lock);
register_task_alive(pwrctrl, CMD_ALIVE);
@ -2044,19 +1931,6 @@ _func_enter_;
if (val8 & BIT(4))
pslv = PS_STATE_S2;
#ifdef CONFIG_RTL8723A
val8 = rtw_btcoex_RpwmVal(padapter);
switch (val8)
{
case 0x4:
pslv = PS_STATE_S3;
break;
case 0xC:
pslv = PS_STATE_S4;
break;
}
#endif // CONFIG_RTL8723A
}
#endif // CONFIG_BT_COEXIST
@ -2124,19 +1998,6 @@ _func_enter_;
if (val8 & BIT(4))
pslv = PS_STATE_S2;
#ifdef CONFIG_RTL8723A
val8 = rtw_btcoex_RpwmVal(padapter);
switch (val8)
{
case 0x4:
pslv = PS_STATE_S3;
break;
case 0xC:
pslv = PS_STATE_S4;
break;
}
#endif // CONFIG_RTL8723A
}
#endif // CONFIG_BT_COEXIST
@ -2228,6 +2089,8 @@ static void resume_workitem_callback(struct work_struct *work);
void rtw_init_pwrctrl_priv(PADAPTER padapter)
{
struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
int i = 0;
u8 val8 = 0;
#if defined(CONFIG_CONCURRENT_MODE)
if (padapter->adapter_type != PRIMARY_ADAPTER)
@ -2245,6 +2108,8 @@ _func_enter_;
pwrctrlpriv->rf_pwrstate = rf_on;
pwrctrlpriv->ips_enter_cnts=0;
pwrctrlpriv->ips_leave_cnts=0;
pwrctrlpriv->lps_enter_cnts=0;
pwrctrlpriv->lps_leave_cnts=0;
pwrctrlpriv->bips_processing = _FALSE;
pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode;
@ -2310,16 +2175,34 @@ _func_enter_;
rtw_register_early_suspend(pwrctrlpriv);
#endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER
#ifdef CONFIG_GPIO_WAKEUP
/*default low active*/
pwrctrlpriv->is_high_active = HIGH_ACTIVE;
val8 = (pwrctrlpriv->is_high_active == 0) ? 1 : 0;
rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE);
rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);
DBG_871X("%s: set GPIO_%d %d as default.\n",
__func__, WAKEUP_GPIO_IDX, val8);
#endif /* CONFIG_GPIO_WAKEUP */
#ifdef CONFIG_WOWLAN
pwrctrlpriv->wowlan_from_cmd = _FALSE;
#endif
pwrctrlpriv->wowlan_pattern_idx = 0;
for (i = 0 ; i < MAX_WKFM_NUM; i++) {
_rtw_memset(pwrctrlpriv->patterns[i].content, '\0',
sizeof(pwrctrlpriv->patterns[i].content));
_rtw_memset(pwrctrlpriv->patterns[i].mask, '\0',
sizeof(pwrctrlpriv->patterns[i].mask));
pwrctrlpriv->patterns[i].len = 0;
}
#ifdef CONFIG_PNO_SUPPORT
pwrctrlpriv->pno_inited = _FALSE;
pwrctrlpriv->pnlo_info = NULL;
pwrctrlpriv->pscan_info = NULL;
pwrctrlpriv->pno_ssid_list = NULL;
pwrctrlpriv->pno_in_resume = _TRUE;
#endif
#endif /* CONFIG_PNO_SUPPORT */
#endif /* CONFIG_WOWLAN */
_func_exit_;
@ -2347,6 +2230,7 @@ _func_enter_;
}
#endif
#ifdef CONFIG_WOWLAN
#ifdef CONFIG_PNO_SUPPORT
if (pwrctrlpriv->pnlo_info != NULL)
printk("****** pnlo_info memory leak********\n");
@ -2357,6 +2241,7 @@ _func_enter_;
if (pwrctrlpriv->pno_ssid_list != NULL)
printk("****** pno_ssid_list memory leak********\n");
#endif
#endif /* CONFIG_WOWLAN */
#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
rtw_unregister_early_suspend(pwrctrlpriv);
@ -2375,7 +2260,7 @@ static void resume_workitem_callback(struct work_struct *work)
{
struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work);
struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
_adapter *adapter = dvobj->if1;
_adapter *adapter = dvobj->padapters[IFACE_ID0];
DBG_871X("%s\n",__FUNCTION__);
@ -2430,7 +2315,7 @@ static void rtw_late_resume(struct early_suspend *h)
{
struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
_adapter *adapter = dvobj->if1;
_adapter *adapter = dvobj->padapters[IFACE_ID0];
DBG_871X("%s\n",__FUNCTION__);
@ -2483,7 +2368,7 @@ static void rtw_late_resume(android_early_suspend_t *h)
{
struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
_adapter *adapter = dvobj->if1;
_adapter *adapter = dvobj->padapters[IFACE_ID0];
DBG_871X("%s\n",__FUNCTION__);
if(pwrpriv->do_late_resume) {
@ -2672,15 +2557,15 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
}
//TODO: the following checking need to be merged...
if(padapter->bDriverStopped
if (rtw_is_drv_stopped(padapter)
|| !padapter->bup
|| !padapter->hw_init_completed
){
DBG_8192C("%s: bDriverStopped=%d, bup=%d, hw_init_completed=%u\n"
|| !rtw_is_hw_init_completed(padapter)
) {
DBG_8192C("%s: bDriverStopped=%s, bup=%d, hw_init_completed=%u\n"
, caller
, padapter->bDriverStopped
, padapter->bup
, padapter->hw_init_completed);
, rtw_is_drv_stopped(padapter)?"True":"False"
, padapter->bup
, rtw_get_hw_init_completed(padapter));
ret= _FALSE;
goto exit;
}
@ -2733,7 +2618,7 @@ int rtw_pm_set_ips(_adapter *padapter, u8 mode)
else if(mode ==IPS_NONE){
rtw_ips_mode_req(pwrctrlpriv, mode);
DBG_871X("%s %s\n", __FUNCTION__, "IPS_NONE");
if((padapter->bSurpriseRemoved ==0)&&(_FAIL == rtw_pwr_wakeup(padapter)) )
if (!rtw_is_surprise_removed(padapter) && (_FAIL == rtw_pwr_wakeup(padapter)))
return -EFAULT;
}
else {

1165
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_recv.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

760
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_rf.c Executable file → Normal file
View File

@ -20,72 +20,722 @@
#define _RTW_RF_C_
#include <drv_types.h>
#include <hal_data.h>
u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = {
36, 38, 40, 42, 44, 46, 48, /* Band 1 */
52, 54, 56, 58, 60, 62, 64, /* Band 2 */
100, 102, 104, 106, 108, 110, 112, /* Band 3 */
116, 118, 120, 122, 124, 126, 128, /* Band 3 */
132, 134, 136, 138, 140, 142, 144, /* Band 3 */
149, 151, 153, 155, 157, 159, 161, /* Band 4 */
165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
struct ch_freq {
u32 channel;
u32 frequency;
u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = {
36, 40, 44, 48,
52, 56, 60, 64,
100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
149, 153, 157, 161, 165, 169, 173, 177
};
struct ch_freq ch_freq_map[] = {
{1, 2412},{2, 2417},{3, 2422},{4, 2427},{5, 2432},
{6, 2437},{7, 2442},{8, 2447},{9, 2452},{10, 2457},
{11, 2462},{12, 2467},{13, 2472},{14, 2484},
/* UNII */
{36, 5180},{40, 5200},{44, 5220},{48, 5240},{52, 5260},
{56, 5280},{60, 5300},{64, 5320},{149, 5745},{153, 5765},
{157, 5785},{161, 5805},{165, 5825},{167, 5835},{169, 5845},
{171, 5855},{173, 5865},
/* HiperLAN2 */
{100, 5500},{104, 5520},{108, 5540},{112, 5560},{116, 5580},
{120, 5600},{124, 5620},{128, 5640},{132, 5660},{136, 5680},
{140, 5700},
/* Japan MMAC */
{34, 5170},{38, 5190},{42, 5210},{46, 5230},
/* Japan */
{184, 4920},{188, 4940},{192, 4960},{196, 4980},
{208, 5040},/* Japan, means J08 */
{212, 5060},/* Japan, means J12 */
{216, 5080},/* Japan, means J16 */
u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM] = {38, 46, 54, 62, 102, 110, 118, 126, 134, 142, 151, 159, 167, 175};
u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM] = {42, 58, 106, 122, 138, 155, 171};
struct center_chs_ent {
u8 ch_num;
u8 *chs;
};
int ch_freq_map_num = (sizeof(ch_freq_map) / sizeof(struct ch_freq));
struct center_chs_ent center_chs_5g_by_bw[] = {
{CENTER_CH_5G_20M_NUM, center_ch_5g_20m},
{CENTER_CH_5G_40M_NUM, center_ch_5g_40m},
{CENTER_CH_5G_80M_NUM, center_ch_5g_80m},
};
u32 rtw_ch2freq(u32 channel)
inline u8 center_chs_5g_num(u8 bw)
{
u8 i;
u32 freq = 0;
for (i = 0; i < ch_freq_map_num; i++)
{
if (channel == ch_freq_map[i].channel)
{
freq = ch_freq_map[i].frequency;
break;
}
}
if (i == ch_freq_map_num)
freq = 2412;
return freq;
if (bw >= CHANNEL_WIDTH_160)
return 0;
return center_chs_5g_by_bw[bw].ch_num;
}
u32 rtw_freq2ch(u32 freq)
inline u8 center_chs_5g(u8 bw, u8 id)
{
u8 i;
u32 ch = 0;
if (bw >= CHANNEL_WIDTH_160)
return 0;
for (i = 0; i < ch_freq_map_num; i++)
{
if (freq == ch_freq_map[i].frequency)
{
ch = ch_freq_map[i].channel;
break;
}
}
if (i == ch_freq_map_num)
ch = 1;
return ch;
if (id >= center_chs_5g_num(bw))
return 0;
return center_chs_5g_by_bw[bw].chs[id];
}
int rtw_ch2freq(int chan)
{
/* see 802.11 17.3.8.3.2 and Annex J
* there are overlapping channel numbers in 5GHz and 2GHz bands */
/*
* RTK: don't consider the overlapping channel numbers: 5G channel <= 14,
* because we don't support it. simply judge from channel number
*/
if (chan >= 1 && chan <= 14) {
if (chan == 14)
return 2484;
else if (chan < 14)
return 2407 + chan * 5;
} else if (chan >= 36 && chan <= 177) {
return 5000 + chan * 5;
}
return 0; /* not supported */
}
int rtw_freq2ch(int freq)
{
/* see 802.11 17.3.8.3.2 and Annex J */
if (freq == 2484)
return 14;
else if (freq < 2484)
return (freq - 2407) / 5;
else if (freq >= 4910 && freq <= 4980)
return (freq - 4000) / 5;
else if (freq <= 45000) /* DMG band lower limit */
return (freq - 5000) / 5;
else if (freq >= 58320 && freq <= 64800)
return (freq - 56160) / 2160;
else
return 0;
}
bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo)
{
u8 c_ch;
u32 freq;
u32 hi_ret = 0, lo_ret = 0;
int i;
bool valid = _FALSE;
if (hi)
*hi = 0;
if (lo)
*lo = 0;
c_ch = rtw_get_center_ch(ch, bw, offset);
freq = rtw_ch2freq(c_ch);
if (!freq) {
rtw_warn_on(1);
goto exit;
}
if (bw == CHANNEL_WIDTH_80) {
hi_ret = freq + 40;
lo_ret = freq - 40;
} else if (bw == CHANNEL_WIDTH_40) {
hi_ret = freq + 20;
lo_ret = freq - 20;
} else if (bw == CHANNEL_WIDTH_20) {
hi_ret = freq + 10;
lo_ret = freq - 10;
} else {
rtw_warn_on(1);
}
if (hi)
*hi = hi_ret;
if (lo)
*lo = lo_ret;
valid = _TRUE;
exit:
return valid;
}
const char * const _ch_width_str[] = {
"20MHz",
"40MHz",
"80MHz",
"160MHz",
"80_80MHz",
"CHANNEL_WIDTH_MAX",
};
const u8 _ch_width_to_bw_cap[] = {
BW_CAP_20M,
BW_CAP_40M,
BW_CAP_80M,
BW_CAP_160M,
BW_CAP_80_80M,
0,
};
const char * const _band_str[] = {
"2.4G",
"5G",
"BOTH",
"BAND_MAX",
};
const u8 _band_to_band_cap[] = {
BAND_CAP_2G,
BAND_CAP_5G,
0,
0,
};
#ifdef CONFIG_80211AC_VHT
#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val)
#else
#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val)
#endif
#if RTW_DEF_MODULE_REGULATORY_CERT
#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) , .def_module_flags = (_val)
#else
#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val)
#endif
/* has def_module_flags specified, used by common map and HAL dfference map */
#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac, _def_module_flags) \
{.alpha2 = (_alpha2), .chplan = (_chplan) \
COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \
COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \
}
#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
#include "../platform/custom_country_chplan.h"
#elif RTW_DEF_MODULE_REGULATORY_CERT
#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2)
static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_map[] = {
COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0xFB), /* China */
COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0xFB), /* Russia(fac/gost), Kaliningrad */
COUNTRY_CHPLAN_ENT("UA", 0x26, 0, 0xFB), /* Ukraine */
};
static const u16 RTL8821AE_HMC_M2_country_chplan_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_map)/sizeof(struct country_chplan);
#endif
#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU)
static const struct country_chplan RTL8821AU_country_chplan_map[] = {
COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0xFB), /* Russia(fac/gost), Kaliningrad */
COUNTRY_CHPLAN_ENT("UA", 0x26, 0, 0xFB), /* Ukraine */
};
static const u16 RTL8821AU_country_chplan_map_sz = sizeof(RTL8821AU_country_chplan_map)/sizeof(struct country_chplan);
#endif
#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF)
static const struct country_chplan RTL8812AENF_NGFF_country_chplan_map[] = {
};
static const u16 RTL8812AENF_NGFF_country_chplan_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_map)/sizeof(struct country_chplan);
#endif
#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC)
static const struct country_chplan RTL8812AEBT_HMC_country_chplan_map[] = {
};
static const u16 RTL8812AEBT_HMC_country_chplan_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_map)/sizeof(struct country_chplan);
#endif
#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2)
static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_map[] = {
};
static const u16 RTL8188EE_HMC_M2_country_chplan_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_map)/sizeof(struct country_chplan);
#endif
#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2)
static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_map[] = {
};
static const u16 RTL8723BE_HMC_M2_country_chplan_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_map)/sizeof(struct country_chplan);
#endif
#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216)
static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_map[] = {
};
static const u16 RTL8723BS_NGFF1216_country_chplan_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_map)/sizeof(struct country_chplan);
#endif
#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2)
static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_map[] = {
};
static const u16 RTL8192EEBT_HMC_M2_country_chplan_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_map)/sizeof(struct country_chplan);
#endif
/**
* rtw_def_module_get_chplan_from_country -
* @country_code: string of country code
* @return:
* Return NULL for case referring to common map
*/
static const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code)
{
const struct country_chplan *ent = NULL;
const struct country_chplan *hal_map = NULL;
u16 hal_map_sz = 0;
int i;
/* TODO: runtime selection for multi driver */
#if (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AE_HMC_M2)
hal_map = RTL8821AE_HMC_M2_country_chplan_map;
hal_map_sz = RTL8821AE_HMC_M2_country_chplan_map_sz;
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AU)
hal_map = RTL8821AU_country_chplan_map;
hal_map_sz = RTL8821AU_country_chplan_map_sz;
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AENF_NGFF)
hal_map = RTL8812AENF_NGFF_country_chplan_map;
hal_map_sz = RTL8812AENF_NGFF_country_chplan_map_sz;
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AEBT_HMC)
hal_map = RTL8812AEBT_HMC_country_chplan_map;
hal_map_sz = RTL8812AEBT_HMC_country_chplan_map_sz;
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8188EE_HMC_M2)
hal_map = RTL8188EE_HMC_M2_country_chplan_map;
hal_map_sz = RTL8188EE_HMC_M2_country_chplan_map_sz;
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BE_HMC_M2)
hal_map = RTL8723BE_HMC_M2_country_chplan_map;
hal_map_sz = RTL8723BE_HMC_M2_country_chplan_map_sz;
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BS_NGFF1216)
hal_map = RTL8723BS_NGFF1216_country_chplan_map;
hal_map_sz = RTL8723BS_NGFF1216_country_chplan_map_sz;
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8192EEBT_HMC_M2)
hal_map = RTL8192EEBT_HMC_M2_country_chplan_map;
hal_map_sz = RTL8192EEBT_HMC_M2_country_chplan_map_sz;
#endif
if (hal_map == NULL || hal_map_sz == 0)
goto exit;
for (i = 0; i < hal_map_sz; i++) {
if (strncmp(country_code, hal_map[i].alpha2, 2) == 0) {
ent = &hal_map[i];
break;
}
}
exit:
return ent;
}
#endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT */
static const struct country_chplan country_chplan_map[] = {
COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x00), /* Andorra */
COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0xFB), /* United Arab Emirates */
COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x00), /* Afghanistan */
COUNTRY_CHPLAN_ENT("AG", 0x30, 1, 0x00), /* Antigua & Barbuda */
COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x00), /* Anguilla(UK) */
COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0xF1), /* Albania */
COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0xB0), /* Armenia */
COUNTRY_CHPLAN_ENT("AO", 0x26, 1, 0xE0), /* Angola */
COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x00), /* Antarctica */
COUNTRY_CHPLAN_ENT("AR", 0x57, 1, 0xF3), /* Argentina */
COUNTRY_CHPLAN_ENT("AS", 0x34, 1, 0x00), /* American Samoa */
COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0xFB), /* Austria */
COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0xFB), /* Australia */
COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0xB0), /* Aruba */
COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0xF1), /* Azerbaijan */
COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0xF1), /* Bosnia & Herzegovina */
COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0x50), /* Barbados */
COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0xF1), /* Bangladesh */
COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0xFB), /* Belgium */
COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0xB0), /* Burkina Faso */
COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0xF1), /* Bulgaria */
COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0xF1), /* Bahrain */
COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0xB0), /* Burundi */
COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0xB0), /* Benin */
COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x10), /* Brunei */
COUNTRY_CHPLAN_ENT("BO", 0x30, 1, 0xF1), /* Bolivia */
COUNTRY_CHPLAN_ENT("BR", 0x34, 1, 0xF1), /* Brazil */
COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0x20), /* Bahamas */
COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0xF1), /* Botswana */
COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0xF1), /* Belarus */
COUNTRY_CHPLAN_ENT("BZ", 0x34, 1, 0x00), /* Belize */
COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0xFB), /* Canada */
COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x00), /* Cocos (Keeling) Islands (Australia) */
COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0xB0), /* Congo, Republic of the */
COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0xB0), /* Central African Republic */
COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0xB0), /* Congo, Democratic Republic of the. Zaire */
COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0xFB), /* Switzerland */
COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0xF1), /* Cote d'Ivoire */
COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x00), /* Cook Islands */
COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0xF1), /* Chile */
COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0xB0), /* Cameroon */
COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0xFB), /* China */
COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0xF1), /* Colombia */
COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0xF1), /* Costa Rica */
COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0xB0), /* Cape Verde */
COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x00), /* Christmas Island (Australia) */
COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0xFB), /* Cyprus */
COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0xFB), /* Czech Republic */
COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0xFB), /* Germany */
COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x80), /* Djibouti */
COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0xFB), /* Denmark */
COUNTRY_CHPLAN_ENT("DM", 0x34, 1, 0x00), /* Dominica */
COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0xF1), /* Dominican Republic */
COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0xF1), /* Algeria */
COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0xF1), /* Ecuador */
COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0xFB), /* Estonia */
COUNTRY_CHPLAN_ENT("EG", 0x47, 0, 0xF1), /* Egypt */
COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x80), /* Western Sahara */
COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x00), /* Eritrea */
COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0xFB), /* Spain, Canary Islands, Ceuta, Melilla */
COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0xB0), /* Ethiopia */
COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0xFB), /* Finland */
COUNTRY_CHPLAN_ENT("FJ", 0x34, 1, 0x00), /* Fiji */
COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x00), /* Falkland Islands (Islas Malvinas) (UK) */
COUNTRY_CHPLAN_ENT("FM", 0x34, 1, 0x00), /* Micronesia, Federated States of (USA) */
COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x00), /* Faroe Islands (Denmark) */
COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0xFB), /* France */
COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0xB0), /* Gabon */
COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0xFB), /* Great Britain (United Kingdom; England) */
COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0xB0), /* Grenada */
COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x00), /* Georgia */
COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x80), /* French Guiana */
COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x00), /* Guernsey (UK) */
COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0xF1), /* Ghana */
COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x00), /* Gibraltar (UK) */
COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x00), /* Greenland (Denmark) */
COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0xB0), /* Gambia */
COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x10), /* Guinea */
COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x00), /* Guadeloupe (France) */
COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0xB0), /* Equatorial Guinea */
COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0xFB), /* Greece */
COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x00), /* South Georgia and the Sandwich Islands (UK) */
COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0xF1), /* Guatemala */
COUNTRY_CHPLAN_ENT("GU", 0x34, 1, 0x00), /* Guam (USA) */
COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0xB0), /* Guinea-Bissau */
COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x00), /* Guyana */
COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0xFB), /* Hong Kong */
COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x00), /* Heard and McDonald Islands (Australia) */
COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0xF1), /* Honduras */
COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0xF9), /* Croatia */
COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0x50), /* Haiti */
COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0xFB), /* Hungary */
COUNTRY_CHPLAN_ENT("ID", 0x54, 0, 0xF3), /* Indonesia */
COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0xFB), /* Ireland */
COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0xF1), /* Israel */
COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x00), /* Isle of Man (UK) */
COUNTRY_CHPLAN_ENT("IN", 0x47, 1, 0xF1), /* India */
COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x00), /* Iraq */
COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x00), /* Iran */
COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0xFB), /* Iceland */
COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0xFB), /* Italy */
COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x00), /* Jersey (UK) */
COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0xF1), /* Jamaica */
COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0xFB), /* Jordan */
COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0xFF), /* Japan- Telec */
COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0xF9), /* Kenya */
COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0xF1), /* Kyrgyzstan */
COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0xF1), /* Cambodia */
COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x00), /* Kiribati */
COUNTRY_CHPLAN_ENT("KN", 0x34, 1, 0x00), /* Saint Kitts and Nevis */
COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0xFB), /* South Korea */
COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0xFB), /* Kuwait */
COUNTRY_CHPLAN_ENT("KY", 0x34, 1, 0x00), /* Cayman Islands (UK) */
COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x00), /* Kazakhstan */
COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x00), /* Laos */
COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0xF1), /* Lebanon */
COUNTRY_CHPLAN_ENT("LC", 0x34, 1, 0x00), /* Saint Lucia */
COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0xFB), /* Liechtenstein */
COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0xF1), /* Sri Lanka */
COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0xB0), /* Liberia */
COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0xF1), /* Lesotho */
COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0xFB), /* Lithuania */
COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0xFB), /* Luxembourg */
COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0xFB), /* Latvia */
COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x00), /* Libya */
COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0xF1), /* Morocco */
COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0xFB), /* Monaco */
COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0xF1), /* Moldova */
COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0xF1), /* Montenegro */
COUNTRY_CHPLAN_ENT("MF", 0x34, 1, 0x00), /* Saint Martin */
COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x20), /* Madagascar */
COUNTRY_CHPLAN_ENT("MH", 0x34, 1, 0x00), /* Marshall Islands (USA) */
COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0xF1), /* Republic of Macedonia (FYROM) */
COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0xB0), /* Mali */
COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x00), /* Burma (Myanmar) */
COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x00), /* Mongolia */
COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x00), /* Macau */
COUNTRY_CHPLAN_ENT("MP", 0x34, 1, 0x00), /* Northern Mariana Islands (USA) */
COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x40), /* Martinique (France) */
COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0xA0), /* Mauritania */
COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x00), /* Montserrat (UK) */
COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0xFB), /* Malta */
COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0xB0), /* Mauritius */
COUNTRY_CHPLAN_ENT("MV", 0x26, 1, 0x00), /* Maldives */
COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0xB0), /* Malawi */
COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0xF1), /* Mexico */
COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0xF1), /* Malaysia */
COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0xF1), /* Mozambique */
COUNTRY_CHPLAN_ENT("NA", 0x26, 0, 0x00), /* Namibia */
COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x00), /* New Caledonia */
COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0xB0), /* Niger */
COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x00), /* Norfolk Island (Australia) */
COUNTRY_CHPLAN_ENT("NG", 0x50, 1, 0xF9), /* Nigeria */
COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0xF1), /* Nicaragua */
COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0xFB), /* Netherlands */
COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0xFB), /* Norway */
COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0xF0), /* Nepal */
COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x00), /* Nauru */
COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x00), /* Niue */
COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0xFB), /* New Zealand */
COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0xF9), /* Oman */
COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0xF1), /* Panama */
COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0xF1), /* Peru */
COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x00), /* French Polynesia (France) */
COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0xF1), /* Papua New Guinea */
COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0xF1), /* Philippines */
COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0xF1), /* Pakistan */
COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0xFB), /* Poland */
COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x00), /* Saint Pierre and Miquelon (France) */
COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0xF1), /* Puerto Rico */
COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0xFB), /* Portugal */
COUNTRY_CHPLAN_ENT("PW", 0x34, 1, 0x00), /* Palau */
COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0xF1), /* Paraguay */
COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0xF9), /* Qatar */
COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x00), /* Reunion (France) */
COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0xF1), /* Romania */
COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0xF1), /* Serbia, Kosovo */
COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0xFB), /* Russia(fac/gost), Kaliningrad */
COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0xB0), /* Rwanda */
COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0xFB), /* Saudi Arabia */
COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x00), /* Solomon Islands */
COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0x90), /* Seychelles */
COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0xFB), /* Sweden */
COUNTRY_CHPLAN_ENT("SG", 0x47, 1, 0xFB), /* Singapore */
COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x00), /* Saint Helena (UK) */
COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0xFB), /* Slovenia */
COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x00), /* Svalbard (Norway) */
COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0xFB), /* Slovakia */
COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0xB0), /* Sierra Leone */
COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x00), /* San Marino */
COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0xF1), /* Senegal */
COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x00), /* Somalia */
COUNTRY_CHPLAN_ENT("SR", 0x34, 1, 0x00), /* Suriname */
COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0x80), /* Sao Tome and Principe */
COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0xF1), /* El Salvador */
COUNTRY_CHPLAN_ENT("SX", 0x34, 1, 0x00), /* Sint Marteen */
COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x20), /* Swaziland */
COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x00), /* Turks and Caicos Islands (UK) */
COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0xB0), /* Chad */
COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x80), /* French Southern and Antarctic Lands (FR Southern Territories) */
COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0xB0), /* Togo */
COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0xF1), /* Thailand */
COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x40), /* Tajikistan */
COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x00), /* Tokelau */
COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x00), /* Turkmenistan */
COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0xF1), /* Tunisia */
COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x00), /* Tonga */
COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0xF1), /* Turkey, Northern Cyprus */
COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0xF1), /* Trinidad & Tobago */
COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0xFF), /* Taiwan */
COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0xF0), /* Tanzania */
COUNTRY_CHPLAN_ENT("UA", 0x26, 1, 0xFB), /* Ukraine */
COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0xF1), /* Uganda */
COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0xFF), /* United States of America (USA) */
COUNTRY_CHPLAN_ENT("UY", 0x34, 1, 0xF1), /* Uruguay */
COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0xF0), /* Uzbekistan */
COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x00), /* Holy See (Vatican City) */
COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0x10), /* Saint Vincent and the Grenadines */
COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0xF1), /* Venezuela */
COUNTRY_CHPLAN_ENT("VI", 0x34, 1, 0x00), /* United States Virgin Islands (USA) */
COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0xF1), /* Vietnam */
COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x00), /* Vanuatu */
COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x00), /* Wallis and Futuna (France) */
COUNTRY_CHPLAN_ENT("WS", 0x34, 1, 0x00), /* Samoa */
COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x40), /* Yemen */
COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x80), /* Mayotte (France) */
COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0xF1), /* South Africa */
COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0xB0), /* Zambia */
COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0xF1), /* Zimbabwe */
};
u16 const country_chplan_map_sz = sizeof(country_chplan_map)/sizeof(struct country_chplan);
/*
* rtw_get_chplan_from_country -
* @country_code: string of country code
*
* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given
*/
const struct country_chplan *rtw_get_chplan_from_country(const char *country_code)
{
const struct country_chplan *ent = NULL;
const struct country_chplan *map = NULL;
u16 map_sz = 0;
char code[2];
int i;
code[0] = alpha_to_upper(country_code[0]);
code[1] = alpha_to_upper(country_code[1]);
#if !defined(CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP) && RTW_DEF_MODULE_REGULATORY_CERT
ent = rtw_def_module_get_chplan_from_country(code);
if (ent != NULL)
goto exit;
#endif
#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
map = CUSTOMIZED_country_chplan_map;
map_sz = CUSTOMIZED_country_chplan_map_sz;
#else
map = country_chplan_map;
map_sz = country_chplan_map_sz;
#endif
for (i = 0; i < map_sz; i++) {
if (strncmp(code, map[i].alpha2, 2) == 0) {
ent = &map[i];
break;
}
}
exit:
#if RTW_DEF_MODULE_REGULATORY_CERT
if (ent && !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT))
ent = NULL;
#endif
return ent;
}
int rtw_ch_to_bb_gain_sel(int ch)
{
int sel = -1;
if (ch >= 1 && ch <= 14)
sel = BB_GAIN_2G;
#ifdef CONFIG_IEEE80211_BAND_5GHZ
else if (ch >= 36 && ch < 48)
sel = BB_GAIN_5GLB1;
else if (ch >= 52 && ch <= 64)
sel = BB_GAIN_5GLB2;
else if (ch >= 100 && ch <= 120)
sel = BB_GAIN_5GMB1;
else if (ch >= 124 && ch <= 144)
sel = BB_GAIN_5GMB2;
else if (ch >= 149 && ch <= 177)
sel = BB_GAIN_5GHB;
#endif
return sel;
}
s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch)
{
s8 kfree_offset = 0;
#ifdef CONFIG_RF_GAIN_OFFSET
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
struct kfree_data_t *kfree_data = GET_KFREE_DATA(padapter);
s8 bb_gain_sel = rtw_ch_to_bb_gain_sel(ch);
if (bb_gain_sel < BB_GAIN_2G || bb_gain_sel >= BB_GAIN_NUM) {
rtw_warn_on(1);
goto exit;
}
if (kfree_data->flag & KFREE_FLAG_ON) {
kfree_offset = kfree_data->bb_gain[bb_gain_sel][path];
if (1)
DBG_871X("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
, __func__, path, ch, bb_gain_sel, kfree_offset);
}
exit:
#endif /* CONFIG_RF_GAIN_OFFSET */
return kfree_offset;
}
void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
{
u8 write_value;
DBG_871X("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, path, 0x55, 0xffffffff));
switch (rtw_get_chip_type(adapter)) {
#ifdef CONFIG_RTL8703B
case RTL8703B:
write_value = RF_TX_GAIN_OFFSET_8703B(offset);
rtw_hal_write_rfreg(adapter, path, 0x55, 0x0fc000, write_value);
break;
#endif /* CONFIG_RTL8703B */
#ifdef CONFIG_RTL8188F
case RTL8188F:
write_value = RF_TX_GAIN_OFFSET_8188F(offset);
rtw_hal_write_rfreg(adapter, path, 0x55, 0x0fc000, write_value);
break;
#endif /* CONFIG_RTL8188F */
#ifdef CONFIG_RTL8192E
case RTL8192E:
write_value = RF_TX_GAIN_OFFSET_8192E(offset);
rtw_hal_write_rfreg(adapter, path, 0x55, 0x0f8000, write_value);
break;
#endif /* CONFIG_RTL8188F */
#ifdef CONFIG_RTL8821A
case RTL8821:
write_value = RF_TX_GAIN_OFFSET_8821A(offset);
rtw_hal_write_rfreg(adapter, path, 0x55, 0x0f8000, write_value);
break;
#endif /* CONFIG_RTL8821A */
#ifdef CONFIG_RTL8814A
case RTL8814A:
DBG_871X("\nkfree by PhyDM on the sw CH. path %d\n", path);
break;
#endif /* CONFIG_RTL8821A */
default:
rtw_warn_on(1);
break;
}
DBG_871X(" after :0x%x\n", rtw_hal_read_rfreg(adapter, path, 0x55, 0xffffffff));
}
void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
s8 kfree_offset = 0;
s8 tx_pwr_track_offset = 0; /* TODO: 8814A should consider tx pwr track when setting tx gain offset */
s8 total_offset;
int i;
for (i = 0; i < hal_data->NumTotalRFPath; i++) {
kfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch);
total_offset = kfree_offset + tx_pwr_track_offset;
rtw_rf_set_tx_gain_offset(adapter, i, total_offset);
}
}
bool rtw_is_dfs_range(u32 hi, u32 lo)
{
return rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10)?_TRUE:_FALSE;
}
bool rtw_is_dfs_ch(u8 ch, u8 bw, u8 offset)
{
u32 hi, lo;
if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
return _FALSE;
return rtw_is_dfs_range(hi, lo)?_TRUE:_FALSE;
}
bool rtw_is_long_cac_range(u32 hi, u32 lo)
{
return rtw_is_range_overlap(hi, lo, 5660 + 10, 5600 - 10)?_TRUE:_FALSE;
}
bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset)
{
u32 hi, lo;
if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
return _FALSE;
return rtw_is_long_cac_range(hi, lo)?_TRUE:_FALSE;
}

142
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_security.c Executable file → Normal file
View File

@ -1733,8 +1733,9 @@ _func_enter_;
prwskey=pattrib->dot118021x_UncstKey.skey;
}
#ifdef CONFIG_TDLS //swencryption
#ifdef CONFIG_TDLS
{
/* Swencryption */
struct sta_info *ptdls_sta;
ptdls_sta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->dst[0] );
if((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) )
@ -2213,8 +2214,7 @@ u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe)
_rtw_memcpy(&temp_ipn, p+4, 6);
temp_ipn = le64_to_cpu(temp_ipn);
//BIP packet number should bigger than previous BIP packet
if(temp_ipn <= pmlmeext->mgnt_80211w_IPN_rx)
{
if (temp_ipn < pmlmeext->mgnt_80211w_IPN_rx) {
DBG_871X("replay BIP packet\n");
goto BIP_exit;
}
@ -3029,12 +3029,12 @@ void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta)
* added by the KDF anyway..
*/
if (os_memcmp(myid(&(padapter->eeprompriv)), psta->hwaddr, ETH_ALEN) < 0) {
_rtw_memcpy(data, myid(&(padapter->eeprompriv)), ETH_ALEN);
if (os_memcmp(adapter_mac_addr(padapter), psta->hwaddr, ETH_ALEN) < 0) {
_rtw_memcpy(data, adapter_mac_addr(padapter), ETH_ALEN);
_rtw_memcpy(data + ETH_ALEN, psta->hwaddr, ETH_ALEN);
} else {
_rtw_memcpy(data, psta->hwaddr, ETH_ALEN);
_rtw_memcpy(data + ETH_ALEN, myid(&(padapter->eeprompriv)), ETH_ALEN);
_rtw_memcpy(data + ETH_ALEN, adapter_mac_addr(padapter), ETH_ALEN);
}
_rtw_memcpy(data + 2 * ETH_ALEN, get_bssid(pmlmepriv), ETH_ALEN);
@ -3101,6 +3101,55 @@ int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,
}
/**
* wpa_tdls_teardown_ftie_mic - Calculate TDLS TEARDOWN FTIE MIC
* @kck: TPK-KCK
* @lnkid: Pointer to the beginning of Link Identifier IE
* @reason: Reason code of TDLS Teardown
* @dialog_token: Dialog token that was used in the MIC calculation for TPK Handshake Message 3
* @trans_seq: Transaction Sequence number (1 octet) which shall be set to the value 4
* @ftie: Pointer to the beginning of FT IE
* @mic: Pointer for writing MIC
*
* Calculate MIC for TDLS TEARDOWN frame according to Section 10.22.5 in IEEE 802.11 - 2012.
*/
int wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason,
u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic)
{
u8 *buf, *pos;
struct wpa_tdls_ftie *_ftie;
int ret;
int len = 2 + lnkid[1] + 2 + 1 + 1 + 2 + ftie[1];
buf = rtw_zmalloc(len);
if (!buf) {
DBG_871X("TDLS: No memory for MIC calculation\n");
return -1;
}
pos = buf;
/* 1) Link Identifier IE */
_rtw_memcpy(pos, lnkid, 2 + lnkid[1]);
pos += 2 + lnkid[1];
/* 2) Reason Code */
_rtw_memcpy(pos, (u8 *)&reason, 2);
pos += 2;
/* 3) Dialog Token */
*pos++ = dialog_token;
/* 4) Transaction Sequence number */
*pos++ = trans_seq;
/* 5) FTIE, with the MIC field of the FTIE set to 0 */
_rtw_memcpy(pos, ftie, 2 + ftie[1]);
_ftie = (struct wpa_tdls_ftie *) pos;
_rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN);
pos += 2 + ftie[1];
ret = omac1_aes_128(kck, buf, pos - buf, mic);
rtw_mfree(buf, len);
return ret;
}
int tdls_verify_mic(u8 *kck, u8 trans_seq,
u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie)
{
@ -3112,14 +3161,14 @@ int tdls_verify_mic(u8 *kck, u8 trans_seq,
if (lnkid == NULL || rsnie == NULL ||
timeoutie == NULL || ftie == NULL){
return 0;
return _FAIL;
}
len = 2 * ETH_ALEN + 1 + 2 + 18 + 2 + *(rsnie+1) + 2 + *(timeoutie+1) + 2 + *(ftie+1);
buf = rtw_zmalloc(len);
if (buf == NULL)
return 0;
return _FAIL;
pos = buf;
/* 1) TDLS initiator STA MAC address */
@ -3149,17 +3198,17 @@ int tdls_verify_mic(u8 *kck, u8 trans_seq,
ret = omac1_aes_128(kck, buf, pos - buf, mic);
rtw_mfree(buf, len);
if (ret)
return 0;
return _FAIL;
rx_ftie = ftie+4;
if (os_memcmp(mic, rx_ftie, 16) == 0) {
//Valid MIC
return 1;
return _SUCCESS;
}
//Invalid MIC
DBG_871X( "[%s] Invalid MIC\n", __FUNCTION__);
return 0;
return _FAIL;
}
#endif //CONFIG_TDLS
@ -3173,8 +3222,10 @@ _func_enter_;
RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler ^^^\n"));
/*
if(padapter->bDriverStopped ||padapter->bSurpriseRemoved){
RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler (padapter->bDriverStopped %d)(padapter->bSurpriseRemoved %d)^^^\n",padapter->bDriverStopped,padapter->bSurpriseRemoved));
if (RTW_CANNOT_RUN(padapter)) {
RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler (padapter->bDriverStopped %s)(padapter->bSurpriseRemoved %s)^^^\n"
, rtw_is_drv_stopped(padapter)?"True":"False"
, rtw_is_surprise_removed(padapter)?"True":"False"));
return;
}
@ -3228,3 +3279,68 @@ u8 rtw_handle_tkip_countermeasure(_adapter* adapter, const char *caller)
return status;
}
#ifdef CONFIG_WOWLAN
u16 rtw_cal_crc16(u8 data, u16 crc)
{
u8 shift_in, data_bit;
u8 crc_bit4, crc_bit11, crc_bit15;
u16 crc_result;
int index;
for (index = 0; index < 8; index++) {
crc_bit15 = ((crc & BIT15) ? 1 : 0);
data_bit = (data & (BIT0 << index) ? 1 : 0);
shift_in = crc_bit15 ^ data_bit;
/*printf("crc_bit15=%d, DataBit=%d, shift_in=%d\n",
* crc_bit15, data_bit, shift_in);*/
crc_result = crc << 1;
if (shift_in == 0)
crc_result &= (~BIT0);
else
crc_result |= BIT0;
/*printf("CRC =%x\n",CRC_Result);*/
crc_bit11 = ((crc & BIT11) ? 1 : 0) ^ shift_in;
if (crc_bit11 == 0)
crc_result &= (~BIT12);
else
crc_result |= BIT12;
/*printf("bit12 CRC =%x\n",CRC_Result);*/
crc_bit4 = ((crc & BIT4) ? 1 : 0) ^ shift_in;
if (crc_bit4 == 0)
crc_result &= (~BIT5);
else
crc_result |= BIT5;
/* printf("bit5 CRC =%x\n",CRC_Result); */
/* repeat using the last result*/
crc = crc_result;
}
return crc;
}
/*
* function name :rtw_calc_crc
*
* input: char* pattern , pattern size
*
*/
u16 rtw_calc_crc(u8 *pdata, int length)
{
u16 crc = 0xffff;
int i;
for (i = 0; i < length; i++)
crc = rtw_cal_crc16(pdata[i], crc);
/* get 1' complement */
crc = ~crc;
return crc;
}
#endif /*CONFIG_WOWLAN*/

12
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_sreset.c Executable file → Normal file
View File

@ -162,7 +162,7 @@ void sreset_restore_security_station(_adapter *padapter)
else
{
//pairwise key
rtw_setstakey_cmd(padapter, psta, _TRUE,_FALSE);
rtw_setstakey_cmd(padapter, psta, UNICAST_KEY,_FALSE);
//group key
rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0,_FALSE);
}
@ -174,6 +174,7 @@ void sreset_restore_network_station(_adapter *padapter)
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 doiqk = _FALSE;
#if 0
{
@ -214,12 +215,15 @@ void sreset_restore_network_station(_adapter *padapter)
#endif
}
rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, NULL);
doiqk = _TRUE;
rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK , &doiqk);
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
doiqk = _FALSE;
rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
//disable dynamic functions, such as high power, DIG
//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
/*rtw_phydm_func_disable_all(padapter);*/
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
@ -232,7 +236,7 @@ void sreset_restore_network_station(_adapter *padapter)
mlmeext_joinbss_event_callback(padapter, 1);
//restore Sequence No.
rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
rtw_hal_set_hwreg(padapter, HW_VAR_RESTORE_HW_SEQ, 0);
sreset_restore_security_station(padapter);
}

169
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_sta_mgt.c Executable file → Normal file
View File

@ -28,6 +28,140 @@
#endif
bool test_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
{
if (ntohs(*((u16 *)local_port)) == 5001 || ntohs(*((u16 *)remote_port)) == 5001)
return _TRUE;
return _FALSE;
}
struct st_register test_st_reg = {
.s_proto = 0x06,
.rule = test_st_match_rule,
};
inline void rtw_st_ctl_init(struct st_ctl_t *st_ctl)
{
_rtw_memset(st_ctl->reg, 0 , sizeof(struct st_register) * SESSION_TRACKER_REG_ID_NUM);
_rtw_init_queue(&st_ctl->tracker_q);
}
inline void rtw_st_ctl_clear_tracker_q(struct st_ctl_t *st_ctl)
{
_irqL irqL;
_list *plist, *phead;
struct session_tracker *st;
_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
phead = &st_ctl->tracker_q.queue;
plist = get_next(phead);
while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
st = LIST_CONTAINOR(plist, struct session_tracker, list);
plist = get_next(plist);
rtw_list_delete(&st->list);
rtw_mfree((u8 *)st, sizeof(struct session_tracker));
}
_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
}
inline void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl)
{
rtw_st_ctl_clear_tracker_q(st_ctl);
_rtw_deinit_queue(&st_ctl->tracker_q);
}
inline void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg)
{
if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) {
rtw_warn_on(1);
return;
}
st_ctl->reg[st_reg_id].s_proto = reg->s_proto;
st_ctl->reg[st_reg_id].rule = reg->rule;
}
inline void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id)
{
int i;
if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) {
rtw_warn_on(1);
return;
}
st_ctl->reg[st_reg_id].s_proto = 0;
st_ctl->reg[st_reg_id].rule = NULL;
/* clear tracker queue if no session trecker registered */
for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++)
if (st_ctl->reg[i].s_proto != 0)
break;
if (i >= SESSION_TRACKER_REG_ID_NUM)
rtw_st_ctl_clear_tracker_q(st_ctl);
}
inline bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto)
{
bool ret = _FALSE;
int i;
for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
if (st_ctl->reg[i].s_proto == s_proto) {
ret = _TRUE;
break;
}
}
return ret;
}
inline bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
{
bool ret = _FALSE;
int i;
st_match_rule rule;
for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
rule = st_ctl->reg[i].rule;
if (rule && rule(adapter, local_naddr, local_port, remote_naddr, remote_port) == _TRUE) {
ret = _TRUE;
break;
}
}
return ret;
}
#define SESSION_TRACKER_FMT IP_FMT":"PORT_FMT" "IP_FMT":"PORT_FMT" %u %d"
#define SESSION_TRACKER_ARG(st) IP_ARG(&(st)->local_naddr), PORT_ARG(&(st)->local_port), IP_ARG(&(st)->remote_naddr), PORT_ARG(&(st)->remote_port), (st)->status, rtw_get_passing_time_ms((st)->set_time)
void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl)
{
int i;
_irqL irqL;
_list *plist, *phead;
struct session_tracker *st;
if (!DBG_SESSION_TRACKER)
return;
for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++)
DBG_871X_SEL_NL(sel, "reg%d: %u %p\n", i, st_ctl->reg[i].s_proto, st_ctl->reg[i].rule);
_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
phead = &st_ctl->tracker_q.queue;
plist = get_next(phead);
while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
st = LIST_CONTAINOR(plist, struct session_tracker, list);
plist = get_next(plist);
DBG_871X_SEL_NL(sel, SESSION_TRACKER_FMT"\n", SESSION_TRACKER_ARG(st));
}
_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
}
void _rtw_init_stainfo(struct sta_info *psta);
void _rtw_init_stainfo(struct sta_info *psta)
{
@ -71,6 +205,7 @@ _func_enter_;
psta->no_ht_gf_set = 0;
psta->no_ht_set = 0;
psta->ht_20mhz_set = 0;
psta->ht_40mhz_intolerant = 0;
#endif
#ifdef CONFIG_TX_MCAST2UNI
@ -80,7 +215,9 @@ _func_enter_;
psta->keep_alive_trycnt = 0;
#endif // CONFIG_AP_MODE
rtw_st_ctl_init(&psta->st_ctl);
_func_exit_;
}
@ -123,7 +260,7 @@ _func_enter_;
psta++;
}
pstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */
#ifdef CONFIG_AP_MODE
@ -317,7 +454,7 @@ _func_exit_;
//struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr)
struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr)
{
_irqL irqL, irqL2;
uint tmp_aid;
@ -390,7 +527,9 @@ _func_enter_;
pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2],hwaddr[3],hwaddr[4],hwaddr[5]));
init_addba_retry_timer(pstapriv->padapter, psta);
#ifdef CONFIG_IEEE80211W
init_dot11w_expire_timer(pstapriv->padapter, psta);
#endif /* CONFIG_IEEE80211W */
#ifdef CONFIG_TDLS
rtw_init_tdls_timer(pstapriv->padapter, psta);
#endif //CONFIG_TDLS
@ -412,6 +551,7 @@ _func_enter_;
preorder_ctrl->wend_b= 0xffff;
//preorder_ctrl->wsize_b = (NR_RECVBUFF-2);
preorder_ctrl->wsize_b = 64;//64;
preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
_rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);
@ -427,6 +567,7 @@ _func_enter_;
#endif
/* init for the sequence number of received management frame */
psta->RxMgmtFrameSeqNum = 0xffff;
psta->ra_rpt_linked = _FALSE;
//alloc mac id for non-bc/mc station,
rtw_alloc_macid(pstapriv->padapter, psta);
@ -536,10 +677,13 @@ _func_enter_;
// re-init sta_info; 20061114 // will be init in alloc_stainfo
//_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
//_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
#ifdef CONFIG_IEEE80211W
_cancel_timer_ex(&psta->dot11w_expire_timer);
#endif /* CONFIG_IEEE80211W */
_cancel_timer_ex(&psta->addba_retry_timer);
#ifdef CONFIG_TDLS
psta->tdls_sta_state = TDLS_STATE_NONE;
rtw_free_tdls_timer(psta);
#endif //CONFIG_TDLS
@ -636,6 +780,8 @@ _func_enter_;
#endif // CONFIG_AP_MODE
rtw_st_ctl_deinit(&psta->st_ctl);
_rtw_spinlock_free(&psta->lock);
//_enter_critical_bh(&(pfree_sta_queue->lock), &irqL0);
@ -712,7 +858,7 @@ _func_exit_;
}
/* any station allocated can be searched by hash list */
struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr)
{
_irqL irqL;
@ -723,16 +869,16 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
u32 index;
u8 *addr;
const u8 *addr;
u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
const u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
_func_enter_;
if(hwaddr==NULL)
return NULL;
if(IS_MCAST(hwaddr))
if(IS_MCAST((unsigned char *)hwaddr))
{
addr = bc_addr;
}
@ -788,7 +934,10 @@ _func_enter_;
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("rtw_alloc_stainfo fail"));
goto exit;
}
#ifdef CONFIG_BEAMFORMING
psta->txbf_gid = 63;
psta->txbf_paid = 0;
#endif
ptxservq= &(psta->sta_xmitpriv.be_q);
/*

3118
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_tdls.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

183
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_vht.c Executable file → Normal file
View File

@ -38,10 +38,10 @@ const u16 VHT_MCS_DATA_RATE[3][2][30] =
90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200}}, // Short GI, 40MHz
{ {59, 117, 176, 234, 351, 468, 527, 585, 702, 780,
117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560,
176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2106}, // Long GI, 80MHz
176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340}, /* Long GI, 80MHz */
{65, 130, 195, 260, 390, 520, 585, 650, 780, 867,
130, 260, 390, 520, 780, 1040, 1170, 1300, 1560,1734,
195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2340} } // Short GI, 80MHz
195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600} } /* Short GI, 80MHz */
};
u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map)
@ -64,7 +64,7 @@ u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map)
}
}
//DBG_871X("HighestVHTMCSRate is %x\n", vht_mcs_rate);
/* DBG_871X("HighestVHTMCSRate is %x\n", vht_mcs_rate); */
return vht_mcs_rate;
}
@ -88,7 +88,7 @@ u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map)
}
}
//DBG_871X("%s : %dSS\n", __FUNCTION__, nss);
/* DBG_871X("%s : %dSS\n", __FUNCTION__, nss); */
return nss;
}
@ -119,9 +119,9 @@ void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)
u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate)
{
if(vht_mcs_rate > MGN_VHT2SS_MCS9)
vht_mcs_rate = MGN_VHT2SS_MCS9;
if(vht_mcs_rate > MGN_VHT3SS_MCS9)
vht_mcs_rate = MGN_VHT3SS_MCS9;
/* DBG_871X("bw=%d, short_GI=%d, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)=%d\n", bw, short_GI, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)); */
return VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)];
}
@ -133,7 +133,8 @@ void rtw_vht_use_default_setting(_adapter *padapter)
BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;
BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;
u8 rf_type = 0;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE;
// LDPC support
@ -174,10 +175,17 @@ void rtw_vht_use_default_setting(_adapter *padapter)
rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer);
rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee);
CLEAR_FLAGS(pvhtpriv->beamform_cap);
if(TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer)
{
SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
DBG_871X("[VHT] Support Beamformer\n");
if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) {
#ifdef CONFIG_CONCURRENT_MODE
if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
DBG_871X("[VHT] CONCURRENT AP Support Beamformer\n");
} else
DBG_871X("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n");
#else
SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
DBG_871X("[VHT] Support Beamformer\n");
#endif
}
if(TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee)
{
@ -189,10 +197,12 @@ void rtw_vht_use_default_setting(_adapter *padapter)
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
if (rf_type == RF_1T1R)
pvhtpriv->vht_mcs_map[0] = 0xfe; // Only support 1SS MCS 0~9;
if (rf_type == RF_3T3R)
pvhtpriv->vht_mcs_map[0] = 0xea; /* support 1SS MCS 0~9 2SS MCS 0~9 3SS MCS 0~9 */
else if(rf_type == RF_2T2R)
pvhtpriv->vht_mcs_map[0] = 0xfa; /* support 1SS MCS 0~9 2SS MCS 0~9 */
else
pvhtpriv->vht_mcs_map[0] = 0xfa; //support 1SS MCS 0~9 2SS MCS 0~9
pvhtpriv->vht_mcs_map[0] = 0xfe; /* Only support 1SS MCS 0~9; */
pvhtpriv->vht_mcs_map[1] = 0xff;
if(pregistrypriv->vht_rate_sel == 1)
@ -235,19 +245,21 @@ void rtw_vht_use_default_setting(_adapter *padapter)
pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
}
u32 rtw_vht_rate_to_bitmap(u8 *pVHTRate)
u64 rtw_vht_rate_to_bitmap(u8 *pVHTRate)
{
u8 i,j , tmpRate;
u32 RateBitmap = 0;
u64 RateBitmap = 0;
u8 Bits_3ss = 6;
for(i = j= 0; i < 4; i+=2, j+=10)
for(i = j= 0; i < Bits_3ss; i+=2, j+=10)
{
/* every two bits means single sptial stream */
tmpRate = (pVHTRate[0] >> i) & 3;
switch(tmpRate){
case 2:
RateBitmap = RateBitmap | (0x03ff << j);
RateBitmap = RateBitmap | (0x03ff << j);
break;
case 1:
RateBitmap = RateBitmap | (0x01ff << j);
@ -261,7 +273,7 @@ u32 rtw_vht_rate_to_bitmap(u8 *pVHTRate)
break;
}
}
DBG_871X("RateBitmap=%016llx , pVHTRate[0]=%02x, pVHTRate[1]=%02x\n", RateBitmap, pVHTRate[0], pVHTRate[1]);
return RateBitmap;
}
@ -273,7 +285,8 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv;
struct vht_priv *pvhtpriv_sta = &psta->vhtpriv;
struct ht_priv *phtpriv_sta = &psta->htpriv;
u8 cur_ldpc_cap=0, cur_stbc_cap=0, cur_beamform_cap=0, bw_mode = 0;
u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, bw_mode = 0;
u16 cur_beamform_cap = 0;
u8 *pcap_mcs;
if (pvhtpriv_sta->vht_option == _FALSE) {
@ -316,11 +329,14 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
}
pvhtpriv_sta->stbc_cap = cur_stbc_cap;
#ifdef CONFIG_BEAMFORMING
// B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee
if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap))
{
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
/*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap)<<8);
}
// B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer
@ -328,11 +344,14 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap))
{
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
/*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap)<<12);
}
pvhtpriv_sta->beamform_cap = cur_beamform_cap;
if (cur_beamform_cap) {
DBG_871X("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->aid, cur_beamform_cap);
}
#endif
// B23 B24 B25 Maximum A-MPDU Length Exponent
pvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap);
@ -364,7 +383,8 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 cur_ldpc_cap=0, cur_stbc_cap=0, cur_beamform_cap=0, rf_type = RF_1T1R;
u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R;
u16 cur_beamform_cap = 0;
u8 *pcap_mcs;
u8 vht_mcs[2];
@ -395,12 +415,14 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
DBG_871X("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
}
pvhtpriv->stbc_cap = cur_stbc_cap;
#ifdef CONFIG_BEAMFORMING
// B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data))
{
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
/*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data)<<8);
}
// B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer
@ -408,12 +430,15 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data))
{
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
/*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data)<<12);
}
pvhtpriv->beamform_cap = cur_beamform_cap;
if (cur_beamform_cap) {
DBG_871X("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
}
#endif
// B23 B24 B25 Maximum A-MPDU Length Exponent
pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data);
@ -425,6 +450,8 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
vht_mcs[0] |= 0xfc;
else if (rf_type == RF_2T2R)
vht_mcs[0] |= 0xf0;
else if (rf_type == RF_3T3R)
vht_mcs[0] |= 0xc0;
_rtw_memcpy(pvhtpriv->vht_mcs_map, vht_mcs, 2);
@ -447,6 +474,7 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct registry_priv *regsty = adapter_to_regsty(padapter);
u8 target_bw;
u8 target_rxss, current_rxss;
u8 update_ra = _FALSE;
@ -459,7 +487,9 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe)+1);
if (target_bw != psta->bw_mode) {
if (target_bw <= (padapter->registrypriv.bw_mode >> 4)) {
if (hal_is_bw_support(padapter, target_bw)
&& REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
) {
update_ra = _TRUE;
psta->bw_mode = target_bw;
}
@ -486,21 +516,22 @@ u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
//struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
u8 ChnlWidth, center_freq, bw_mode;
u8 ChnlWidth, center_freq, bw_mode, rf_type = 0;
u32 len = 0;
u8 operation[5];
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
_rtw_memset(operation, 0, 5);
bw_mode = pregistrypriv->bw_mode >> 4;
bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */
if (bw_mode >= CHANNEL_WIDTH_80)
{
if (hal_chk_bw_cap(padapter, BW_CAP_80M | BW_CAP_160M)
&& REGSTY_BW_5G(pregistrypriv) >= CHANNEL_WIDTH_80
) {
center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER);
ChnlWidth = 1;
}
else
{
} else {
center_freq = 0;
ChnlWidth = 0;
}
@ -510,8 +541,35 @@ u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
//center frequency
SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);//Todo: need to set correct center channel
SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation,0);
operation[3] = 0xff;
if (padapter->registrypriv.rf_config != RF_MAX_TYPE)
rf_type = padapter->registrypriv.rf_config;
switch (rf_type) {
case RF_1T1R:
operation[3] = 0xfe;
operation[4] = 0xff;
break;
case RF_1T2R:
case RF_2T2R:
case RF_2T2R_GREEN:
operation[3] = 0xfa;
operation[4] = 0xff;
break;
case RF_2T3R:
case RF_2T4R:
case RF_3T3R:
case RF_3T4R:
operation[3] = 0xea;
operation[4] = 0xff;
break;
case RF_4T4R:
operation[3] = 0xaa;
operation[4] = 0xff;
break;
default:
DBG_871X("%s, %d, unknown rf type\n", __func__, __LINE__);
}
rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);
@ -530,10 +588,12 @@ u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw)
chnl_width = bw;
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
if(rf_type == RF_1T1R)
rx_nss = 1;
else
if(rf_type == RF_3T3R)
rx_nss = 3;
else if(rf_type == RF_2T2R)
rx_nss = 2;
else
rx_nss = 1;
SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width);
SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss-1));
@ -548,7 +608,7 @@ u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw)
u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
{
u8 bw, rf_type;
u8 bw, rf_type, rf_num, rx_stbc_nss = 0;
u16 HighestRate;
u8 *pcap, *pcap_mcs;
u32 len = 0;
@ -558,9 +618,19 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
pcap = pvhtpriv->vht_cap;
_rtw_memset(pcap, 0, 32);
// B2 B3 Supported Channel Width Set
SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0); //indicate we don't support neither 160M nor 80+80M bandwidth.
/* B0 B1 Maximum MPDU Length */
SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2);
/* B2 B3 Supported Channel Width Set */
if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) {
if (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80))
SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 2);
else
SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 1);
} else {
SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0);
}
// B4 Rx LDPC
if(TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX))
@ -583,29 +653,25 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
// B8 B9 B10 Rx STBC
if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX))
{
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
if ((rf_type == RF_2T2R) || (rf_type == RF_1T2R)) {
SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, 2);
}
else if (rf_type == RF_1T1R) {
SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, 1);
}
rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss);
}
// B11 SU Beamformer Capable
if(TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))
{
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1);
// B16 17 18 Number of Sounding Dimensions
SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, 1);
rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num);
}
// B12 SU Beamformee Capable
if(TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
{
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1);
// B13 14 15 Compressed Steering Number of Beamformer Antennas Supported
SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, 1);
rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num);
}
// B19 MU Beamformer Capable
@ -634,9 +700,11 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
pcap_mcs = GET_VHT_CAPABILITY_ELE_TX_MCS(pcap);
_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
bw = (pregistrypriv->bw_mode >> 4);
/* find the largest bw supported by both registry and hal */
bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0)&0x3f)];
HighestRate = (HighestRate+1) >> 1;
HighestRate = (HighestRate+1) >> 1;
SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); //indicate we support highest rx rate is 600Mbps.
SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); //indicate we support highest tx rate is 600Mbps.
@ -690,7 +758,8 @@ u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_le
pframe = rtw_set_ie(out_ie+out_len, EID_VHTOperation, ielen, p+2 , pout_len);
}
notify_bw = pregistrypriv->bw_mode >> 4;
/* find the largest bw supported by both registry and hal */
notify_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
if (notify_bw > operation_bw)
notify_bw = operation_bw;

0
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_wapi.c Executable file → Normal file
View File

0
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_wapi_sms4.c Executable file → Normal file
View File

1479
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_wlan_util.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

566
drivers/net/wireless/rockchip_wlan/rtl8723bs/core/rtw_xmit.c Executable file → Normal file
View File

@ -658,6 +658,19 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri
// pattrib->ampdu_en = _TRUE;
//}
#ifdef CONFIG_TDLS
if (pattrib->direct_link==_TRUE) {
psta = pattrib->ptdls_sta;
pattrib->raid = psta->raid;
#ifdef CONFIG_80211N_HT
pattrib->bwmode = psta->bw_mode;
pattrib->ht_en = psta->htpriv.ht_option;
pattrib->ch_offset = psta->htpriv.ch_offset;
pattrib->sgi= query_ra_short_GI(psta);
#endif /* CONFIG_80211N_HT */
}
#endif /* CONFIG_TDLS */
pattrib->retry_ctrl = _FALSE;
@ -727,6 +740,13 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib
pattrib->encrypt=_NO_PRIVACY_;
}
#ifdef CONFIG_TDLS
if (pattrib->direct_link == _TRUE) {
if (pattrib->encrypt > 0)
pattrib->encrypt = _AES_;
}
#endif
switch (pattrib->encrypt)
{
@ -810,25 +830,16 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib
pattrib->bswenc = _TRUE;//force using sw enc.
}
#endif
#ifdef DYNAMIC_CAMID_ALLOC
if (pattrib->encrypt && bmcast && _rtw_camctl_chk_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))
pattrib->bswenc = _TRUE;
#endif
#ifdef CONFIG_WAPI_SUPPORT
if(pattrib->encrypt == _SMS4_)
pattrib->bswenc = _FALSE;
#endif
#ifdef CONFIG_TDLS
if(pattrib->direct_link == _TRUE)
{
pattrib->mac_id = pattrib->ptdls_sta->mac_id;
if(pattrib->encrypt>0)
{
pattrib->encrypt= _AES_;
pattrib->iv_len=8;
pattrib->icv_len=8;
pattrib->bswenc = _FALSE;
}
}
#endif //CONFIG_TDLS
exit:
return res;
@ -896,20 +907,37 @@ static void set_qos(struct pkt_file *ppktfile, struct pkt_attrib *pattrib)
}
#ifdef CONFIG_TDLS
void rtw_check_tdls_established(_adapter *padapter, struct pkt_attrib *pattrib)
u8 rtw_check_tdls_established(_adapter *padapter, struct pkt_attrib *pattrib)
{
pattrib->ptdls_sta = NULL;
pattrib->direct_link = _FALSE;
if((padapter->tdlsinfo.link_established == _TRUE)){
if (padapter->tdlsinfo.link_established == _TRUE) {
pattrib->ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);
#if 1
if((pattrib->ptdls_sta!=NULL)&&
(pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)&&
(pattrib->ether_type!=0x0806)){
pattrib->direct_link = _TRUE;
//DBG_871X("send ptk to "MAC_FMT" using direct link\n", MAC_ARG(pattrib->dst));
}
#else
if (pattrib->ptdls_sta != NULL &&
pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
pattrib->direct_link = _TRUE;
#if 0
DBG_871X("send ptk to "MAC_FMT" using direct link\n", MAC_ARG(pattrib->dst));
#endif
}
/* ARP frame may be helped by AP*/
if (pattrib->ether_type != 0x0806) {
pattrib->direct_link = _FALSE;
}
#endif
}
return pattrib->direct_link;
}
s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
@ -933,7 +961,7 @@ s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
pattrib->psta = psta;
pattrib->ack_policy = 0;
// get ether_hdr_len
pattrib->pkt_hdrlen = ETH_HLEN;//(pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; //vlan tag
pattrib->pkt_hdrlen = ETH_HLEN;
// [TDLS] TODO: setup req/rsp should be AC_BK
if (pqospriv->qos_option && psta->qos_option) {
@ -1007,12 +1035,17 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
_rtw_memcpy(pattrib->ta, myid(&padapter->eeprompriv), ETH_ALEN);
_rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN);
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_adhoc);
}
else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
#ifdef CONFIG_TDLS
if (rtw_check_tdls_established(padapter, pattrib) == _TRUE)
_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); /* For TDLS direct link Tx, set ra to be same to dst */
else
#endif
_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
_rtw_memcpy(pattrib->ta, myid(&padapter->eeprompriv), ETH_ALEN);
_rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN);
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_sta);
}
else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
@ -1023,65 +1056,116 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
else
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown);
#ifdef CONFIG_TDLS
rtw_check_tdls_established(padapter, pattrib);
#endif //CONFIG_TDLS
bmcast = IS_MCAST(pattrib->ra);
if (bmcast) {
psta = rtw_get_bcmc_stainfo(padapter);
if (psta == NULL) { /* if we cannot get psta => drop the pkt */
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta);
RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT "\n", MAC_ARG(pattrib->ra)));
#ifdef DBG_TX_DROP_FRAME
DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra));
#endif
res = _FAIL;
goto exit;
}
} else {
psta = rtw_get_stainfo(pstapriv, pattrib->ra);
if (psta == NULL) { /* if we cannot get psta => drop the pkt */
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta);
RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT"\n", MAC_ARG(pattrib->ra)));
#ifdef DBG_TX_DROP_FRAME
DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra));
#endif
res = _FAIL;
goto exit;
} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & _FW_LINKED)) {
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_ap_link);
res = _FAIL;
goto exit;
}
}
if (!(psta->state & _FW_LINKED)) {
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link);
DBG_871X("%s, psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n", __func__, MAC_ARG(psta->hwaddr), psta->state);
res = _FAIL;
goto exit;
}
pattrib->pktlen = pktfile.pkt_len;
if (ETH_P_IP == pattrib->ether_type)
{
// The following is for DHCP and ARP packet, we use cck1M to tx these packets and let LPS awake some time
// to prevent DHCP protocol fail
/* TODO: 802.1Q VLAN header */
/* TODO: IPV6 */
u8 tmp[24];
_rtw_pktfile_read(&pktfile, &tmp[0], 24);
if (ETH_P_IP == pattrib->ether_type) {
u8 ip[20];
_rtw_pktfile_read(&pktfile, ip, 20);
if (GET_IPV4_IHL(ip) * 4 > 20)
_rtw_pktfile_read(&pktfile, NULL, GET_IPV4_IHL(ip) - 20);
pattrib->icmp_pkt = 0;
pattrib->dhcp_pkt = 0;
if (pktfile.pkt_len > 282) {//MINIMUM_DHCP_PACKET_SIZE) {
if (ETH_P_IP == pattrib->ether_type) {// IP header
if (((tmp[21] == 68) && (tmp[23] == 67)) ||
((tmp[21] == 67) && (tmp[23] == 68))) {
// 68 : UDP BOOTP client
// 67 : UDP BOOTP server
RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("======================update_attrib: get DHCP Packet \n"));
// Use low rate to send DHCP packet.
//if(pMgntInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom)
//{
// tcb_desc->DataRate = MgntQuery_TxRateExcludeCCKRates(ieee);//0xc;//ofdm 6m
// tcb_desc->bTxDisableRateFallBack = false;
//}
//else
// pTcb->DataRate = Adapter->MgntInfo.LowestBasicRate;
//RTPRINT(FDM, WA_IOT, ("DHCP TranslateHeader(), pTcb->DataRate = 0x%x\n", pTcb->DataRate));
if (GET_IPV4_PROTOCOL(ip) == 0x01) { /* ICMP */
pattrib->icmp_pkt = 1;
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_icmp);
} else if (GET_IPV4_PROTOCOL(ip) == 0x11) { /* UDP */
u8 udp[8];
_rtw_pktfile_read(&pktfile, udp, 8);
if ((GET_UDP_SRC(udp) == 68 && GET_UDP_DST(udp) == 67)
|| (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68)
) {
/* 67 : UDP BOOTP server, 68 : UDP BOOTP client */
if (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */
pattrib->dhcp_pkt = 1;
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_dhcp);
if (0)
DBG_871X("send DHCP packet\n");
}
}
} else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */
&& rtw_st_ctl_chk_reg_s_proto(&psta->st_ctl, 0x06) == _TRUE
) {
u8 tcp[20];
_rtw_pktfile_read(&pktfile, tcp, 20);
if (rtw_st_ctl_chk_reg_rule(&psta->st_ctl, padapter, IPV4_SRC(ip), TCP_SRC(tcp), IPV4_DST(ip), TCP_DST(tcp)) == _TRUE) {
if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) {
session_tracker_add_cmd(padapter, psta
, IPV4_SRC(ip), TCP_SRC(tcp)
, IPV4_SRC(ip), TCP_DST(tcp));
if (DBG_SESSION_TRACKER)
DBG_871X(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n"
, FUNC_ADPT_ARG(padapter)
, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))
, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)));
}
if (GET_TCP_FIN(tcp)) {
session_tracker_del_cmd(padapter, psta
, IPV4_SRC(ip), TCP_SRC(tcp)
, IPV4_SRC(ip), TCP_DST(tcp));
if (DBG_SESSION_TRACKER)
DBG_871X(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n"
, FUNC_ADPT_ARG(padapter)
, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))
, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)));
}
}
}
//for parsing ICMP pakcets
{
struct iphdr *piphdr = (struct iphdr *)tmp;
pattrib->icmp_pkt = 0;
if(piphdr->protocol == 0x1) // protocol type in ip header 0x1 is ICMP
{
pattrib->icmp_pkt = 1;
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_icmp);
}
}
} else if (0x888e == pattrib->ether_type) {
DBG_871X_LEVEL(_drv_always_, "send eapol packet\n");
}
if ( (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) )
{
if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1))
rtw_set_scan_deny(padapter, 3000);
}
#ifdef CONFIG_LPS
// If EAPOL , ARP , OR DHCP packet, driver must be in active mode.
@ -1105,49 +1189,9 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
}
#endif //CONFIG_LPS
bmcast = IS_MCAST(pattrib->ra);
// get sta_info
if (bmcast) {
psta = rtw_get_bcmc_stainfo(padapter);
} else {
psta = rtw_get_stainfo(pstapriv, pattrib->ra);
if (psta == NULL) { // if we cannot get psta => drop the pkt
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta);
RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT"\n", MAC_ARG(pattrib->ra)));
#ifdef DBG_TX_DROP_FRAME
DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __FUNCTION__, MAC_ARG(pattrib->ra));
#endif
res =_FAIL;
goto exit;
}
else if((check_fwstate(pmlmepriv, WIFI_AP_STATE)==_TRUE)&&(!(psta->state & _FW_LINKED)))
{
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_ap_link);
res =_FAIL;
goto exit;
}
}
if(psta == NULL)
{ // if we cannot get psta => drop the pkt
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta);
RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT "\n", MAC_ARG(pattrib->ra)));
#ifdef DBG_TX_DROP_FRAME
DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __FUNCTION__, MAC_ARG(pattrib->ra));
#endif
res = _FAIL;
goto exit;
}
if(!(psta->state &_FW_LINKED))
{
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link);
DBG_871X("%s, psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n", __func__, MAC_ARG(psta->hwaddr), psta->state);
return _FAIL;
}
#ifdef CONFIG_BEAMFORMING
update_attrib_txbf_info(padapter, pattrib, psta);
#endif
//TODO:_lock
if(update_attrib_sec_info(padapter, pattrib, psta) == _FAIL)
@ -1181,13 +1225,18 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
}
else
{
if(pqospriv->qos_option)
#ifdef CONFIG_TDLS
if (pattrib->direct_link == _TRUE) {
if (pattrib->qos_en)
set_qos(&pktfile, pattrib);
} else
#endif
{
set_qos(&pktfile, pattrib);
if (pqospriv->qos_option) {
set_qos(&pktfile, pattrib);
if(pmlmepriv->acm_mask != 0)
{
pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority);
if (pmlmepriv->acm_mask != 0)
pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority);
}
}
}
@ -1404,11 +1453,6 @@ s32 rtw_make_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct qos_priv *pqospriv = &pmlmepriv->qospriv;
u8 qos_option = _FALSE;
#ifdef CONFIG_TDLS
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
struct sta_priv *pstapriv = &padapter->stapriv;
#endif //CONFIG_TDLS
sint res = _SUCCESS;
u16 *fctrl = &pwlanhdr->frame_ctl;
@ -1452,6 +1496,9 @@ _func_enter_;
_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
if (pattrib->qos_en)
qos_option = _TRUE;
}
else
#endif //CONFIG_TDLS
@ -1463,11 +1510,10 @@ _func_enter_;
_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
if (pqospriv->qos_option)
qos_option = _TRUE;
}
if (pqospriv->qos_option)
qos_option = _TRUE;
}
else if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ) {
//to_ds = 0, fr_ds = 1;
@ -1539,25 +1585,6 @@ _func_enter_;
if(psta)
{
#ifdef CONFIG_TDLS
if(pattrib->direct_link==_TRUE)
{
psta = pattrib->ptdls_sta;
//qos_en, ht_en, init rate, ,bw, ch_offset, sgi
//pattrib->qos_en = ptdls_sta->qos_option;
pattrib->raid = psta->raid;
#ifdef CONFIG_80211N_HT
pattrib->bwmode = psta->bw_mode;
pattrib->ht_en = psta->htpriv.ht_option;
pattrib->ch_offset = psta->htpriv.ch_offset;
pattrib->sgi= query_ra_short_GI(psta);
#endif //CONFIG_80211N_HT
}
#endif //CONFIG_TDLS
psta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];
@ -1709,16 +1736,18 @@ int rtw_build_tdls_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *
rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt);
break;
case TDLS_PEER_TRAFFIC_INDICATION:
rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe);
rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt);
break;
#ifdef CONFIG_TDLS_CH_SW
case TDLS_CHANNEL_SWITCH_REQUEST:
rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe);
rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt);
break;
case TDLS_CHANNEL_SWITCH_RESPONSE:
rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe);
rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt);
break;
#endif
case TDLS_PEER_TRAFFIC_RESPONSE:
rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe);
rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt);
break;
#ifdef CONFIG_WFD
case TUNNELED_PROBE_REQ:
@ -1760,7 +1789,7 @@ _func_enter_;
case TDLS_SETUP_RESPONSE:
case TDLS_SETUP_CONFIRM:
case TDLS_PEER_TRAFFIC_INDICATION:
case TDLS_PEER_PSM_REQUEST: //directly to peer STA or via AP
case TDLS_PEER_PSM_REQUEST:
case TUNNELED_PROBE_REQ:
case TUNNELED_PROBE_RSP:
case TDLS_DISCOVERY_REQUEST:
@ -1876,11 +1905,15 @@ _func_enter_;
}
}
if(psta==NULL)
return _FAIL;
if (psta==NULL) {
res = _FAIL;
goto exit;
}
if (pxmitframe->buf_addr == NULL)
return _FAIL;
if (pxmitframe->buf_addr == NULL) {
res = _FAIL;
goto exit;
}
pbuf_start = pxmitframe->buf_addr;
mem_start = pbuf_start + TXDESC_OFFSET;
@ -1944,6 +1977,7 @@ _func_enter_;
if (xmitframe_addmic(padapter, pxmitframe) == _FAIL)
{
res = _FAIL;
goto exit;
}
@ -2238,9 +2272,6 @@ _func_enter_;
_enter_critical_bh(&padapter->security_key_mutex, &irqL);
//only support station mode
if(!check_fwstate(pmlmepriv, WIFI_STATION_STATE) || !check_fwstate(pmlmepriv, _FW_LINKED))
goto xmitframe_coalesce_success;
//IGTK key is not install, it may not support 802.11w
if(padapter->securitypriv.binstallBIPkey != _TRUE)
@ -2337,9 +2368,8 @@ _func_enter_;
goto xmitframe_coalesce_fail;
}
if(!(psta->state & _FW_LINKED) || pxmitframe->buf_addr==NULL)
{
DBG_871X("%s, not _FW_LINKED or addr null\n", __func__);
if (pxmitframe->buf_addr == NULL) {
DBG_871X("%s, pxmitframe->buf_addr\n", __func__);
goto xmitframe_coalesce_fail;
}
@ -2362,6 +2392,13 @@ _func_enter_;
}*/
if(pattrib->encrypt>0)
_rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16);
/* To use wrong key */
if (pattrib->key_type == IEEE80211W_WRONG_KEY) {
DBG_871X("use wrong key\n");
pattrib->dot118021x_UncstKey.skey[0] = 0xff;
}
//bakeup original management packet
_rtw_memcpy(tmp_buf, pframe, pattrib->pktlen);
//move to data portion
@ -3096,7 +3133,7 @@ static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, str
{
pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
xmitframe_plist = get_next(xmitframe_plist);
/* xmitframe_plist = get_next(xmitframe_plist); */
/*#ifdef RTK_DMP_PLATFORM
#ifdef CONFIG_USB_TX_AGGREGATION
@ -3730,6 +3767,147 @@ static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib)
pattrib->qsel = qsel;
}
/*
* The main transmit(tx) entry
*
* Return
* 1 enqueue
* 0 success, hardware will handle this xmit frame(packet)
* <0 fail
*/
s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
{
int ret = 0;
int rtap_len;
int qos_len = 0;
int dot11_hdr_len = 24;
int snap_len = 6;
unsigned char *pdata;
u16 frame_ctl;
unsigned char src_mac_addr[6];
unsigned char dst_mac_addr[6];
struct rtw_ieee80211_hdr *dot11_hdr;
struct ieee80211_radiotap_header *rtap_hdr;
_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
if (skb)
rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
goto fail;
rtap_hdr = (struct ieee80211_radiotap_header *)skb->data;
if (unlikely(rtap_hdr->it_version))
goto fail;
rtap_len = ieee80211_get_radiotap_len(skb->data);
if (unlikely(skb->len < rtap_len))
goto fail;
if (rtap_len != 12) {
DBG_8192C("radiotap len (should be 14): %d\n", rtap_len);
goto fail;
}
/* Skip the ratio tap header */
skb_pull(skb, rtap_len);
dot11_hdr = (struct rtw_ieee80211_hdr *)skb->data;
frame_ctl = le16_to_cpu(dot11_hdr->frame_ctl);
/* Check if the QoS bit is set */
if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
unsigned char *pframe;
struct rtw_ieee80211_hdr *pwlanhdr;
struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
u8 *buf = skb->data;
u32 len = skb->len;
u8 category, action;
int type = -1;
pmgntframe = alloc_mgtxmitframe(pxmitpriv);
if (pmgntframe == NULL) {
rtw_udelay_os(500);
goto fail;
}
pattrib = &pmgntframe->attrib;
update_monitor_frame_attrib(padapter, pattrib);
pattrib->retry_ctrl = _FALSE;
_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
_rtw_memcpy(pframe, (void *)buf, len);
pattrib->pktlen = len;
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1))
pattrib->rate = MGN_24M;
pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
pattrib->seqnum = pmlmeext->mgnt_seq;
pmlmeext->mgnt_seq++;
pattrib->last_txcmdsz = pattrib->pktlen;
dump_mgntframe(padapter, pmgntframe);
} else {
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
unsigned char *pframe;
struct rtw_ieee80211_hdr *pwlanhdr;
struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
u8 *buf = skb->data;
u32 len = skb->len;
u8 category, action;
int type = -1;
pmgntframe = alloc_mgtxmitframe(pxmitpriv);
if (pmgntframe == NULL)
goto fail;
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(padapter, pattrib);
pattrib->retry_ctrl = _FALSE;
_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
_rtw_memcpy(pframe, (void *)buf, len);
pattrib->pktlen = len;
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
pattrib->seqnum = pmlmeext->mgnt_seq;
pmlmeext->mgnt_seq++;
pattrib->last_txcmdsz = pattrib->pktlen;
dump_mgntframe(padapter, pmgntframe);
}
fail:
rtw_skb_free(skb);
return 0;
}
/*
* The main transmit(tx) entry
*
@ -3900,13 +4078,11 @@ sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_fra
break;
}
/* Transmit TDLS PTI via AP */
if(ptdls_sta->sleepq_len==1)
{
//transmit TDLS PTI via AP
rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_SD_PTI);
}
ret = _TRUE;
rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ISSUE_PTI);
ret = _TRUE;
}
_exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
@ -3927,9 +4103,11 @@ inline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe)
_adapter *adapter = xmitframe->padapter;
struct registry_priv *registry = &adapter->registrypriv;
if (adapter->interface_type != RTW_PCIE) {
if (rtw_get_intf_type(adapter) != RTW_PCIE) {
if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) {
if (adapter->registrypriv.wifi_spec == 1) {
allow = _TRUE;
} else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) {
struct pkt_attrib *attrib = &xmitframe->attrib;
@ -3941,8 +4119,8 @@ if (adapter->interface_type != RTW_PCIE) {
|| attrib->dhcp_pkt
) {
if (0)
DBG_871X(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter)
, attrib->ether_type, attrib->dhcp_pkt?" DHCP":"");
DBG_871X(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter)
, attrib->ether_type, attrib->dhcp_pkt?" DHCP":"");
allow = _TRUE;
}
}
@ -4052,14 +4230,21 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p
pstapriv->sta_dz_bitmap |= BIT(0);
//DBG_871X("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap);
if (update_tim == _TRUE) {
if (is_broadcast_mac_addr(pattrib->ra))
_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer BC");
else
_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer MC");
if (padapter->registrypriv.wifi_spec == 1) {
/*
*if (update_tim == _TRUE)
* rtw_chk_hi_queue_cmd(padapter);
*/
} else {
chk_bmc_sleepq_cmd(padapter);
if (update_tim == _TRUE) {
if (is_broadcast_mac_addr(pattrib->ra))
_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer BC");
else
_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer MC");
} else {
chk_bmc_sleepq_cmd(padapter);
}
}
//_exit_critical_bh(&psta->sleep_q.lock, &irqL);
@ -4236,10 +4421,7 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta)
rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
#ifdef CONFIG_TDLS
if( !(psta->tdls_sta_state & TDLS_LINKED_STATE) )
{
if( psta_bmc != NULL )
{
if (!(psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta_bmc != NULL)) {
#endif //CONFIG_TDLS
@ -4251,7 +4433,6 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta)
#ifdef CONFIG_TDLS
}
}
#endif //CONFIG_TDLS
_exit_critical_bh(&pxmitpriv->lock, &irqL0);
@ -4539,7 +4720,7 @@ void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta)
return;
}
#endif
#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) */
#ifdef CONFIG_XMIT_THREAD_MODE
void enqueue_pending_xmitbuf(
@ -4711,6 +4892,39 @@ thread_return rtw_xmit_thread(thread_context context)
}
#endif
bool rtw_xmit_ac_blocked(_adapter *adapter)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
_adapter *iface;
struct mlme_ext_priv *mlmeext;
struct mlme_ext_info *mlmeextinfo;
bool blocked = _FALSE;
int i;
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
mlmeext = &iface->mlmeextpriv;
/* check scan state */
if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE
&& mlmeext_scan_state(mlmeext) != SCAN_BACK_OP
) {
blocked = _TRUE;
goto exit;
}
if (mlmeext_scan_state(mlmeext) == SCAN_BACK_OP
&& !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)
) {
blocked = _TRUE;
goto exit;
}
}
exit:
return blocked;
}
void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms)
{
sctx->timeout_ms = timeout_ms;
@ -4807,11 +5021,11 @@ int rtw_ack_tx_polling(struct xmit_priv *pxmitpriv, u32 timeout_ms)
if (pack_tx_ops->status != RTW_SCTX_SUBMITTED)
break;
if (adapter->bDriverStopped) {
if (rtw_is_drv_stopped(adapter)) {
pack_tx_ops->status = RTW_SCTX_DONE_DRV_STOP;
break;
}
if (adapter->bSurpriseRemoved) {
if (rtw_is_surprise_removed(adapter)) {
pack_tx_ops->status = RTW_SCTX_DONE_DEV_REMOVE;
break;
}

2
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/HalPwrSeqCmd.c Executable file → Normal file
View File

@ -147,7 +147,7 @@ u8 HalPwrSeqCmdParsing(
rtw_udelay_os(10);
if (pollingCount++ > maxPollingCnt) {
DBG_871X_LEVEL(_drv_always_, "HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
DBG_871X_LEVEL(_drv_err_, "HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
return _FALSE;
}
} while (!bPollingBit);

3241
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8192e1Ant.c
View File

File diff suppressed because it is too large Load Diff

214
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8192e1Ant.h
View File

@ -1,214 +0,0 @@
//===========================================
// The following is for 8192E_1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8192E_1ANT 0
#define BT_INFO_8192E_1ANT_B_FTP BIT7
#define BT_INFO_8192E_1ANT_B_A2DP BIT6
#define BT_INFO_8192E_1ANT_B_HID BIT5
#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8192E_1ANT_B_CONNECTION BIT0
#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2
typedef enum _BT_INFO_SRC_8192E_1ANT{
BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_1ANT_MAX
}BT_INFO_SRC_8192E_1ANT,*PBT_INFO_SRC_8192E_1ANT;
typedef enum _BT_8192E_1ANT_BT_STATUS{
BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_1ANT_BT_STATUS_MAX
}BT_8192E_1ANT_BT_STATUS,*PBT_8192E_1ANT_BT_STATUS;
typedef enum _BT_8192E_1ANT_WIFI_STATUS{
BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8192E_1ANT_WIFI_STATUS_MAX
}BT_8192E_1ANT_WIFI_STATUS,*PBT_8192E_1ANT_WIFI_STATUS;
typedef enum _BT_8192E_1ANT_COEX_ALGO{
BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_1ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_1ANT_COEX_ALGO_HID = 0x2,
BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8192E_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8192E_1ANT_COEX_ALGO,*PBT_8192E_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8192E_1ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u1Byte preSsType;
u1Byte curSsType;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte errorCondition;
} COEX_DM_8192E_1ANT, *PCOEX_DM_8192E_1ANT;
typedef struct _COEX_STA_8192E_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8192E_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8192E_1ANT, *PCOEX_STA_8192E_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192e1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8192e1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192e1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8192e1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);

4369
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8192e2Ant.c
View File

File diff suppressed because it is too large Load Diff

206
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8192e2Ant.h
View File

@ -1,206 +0,0 @@
//===========================================
// The following is for 8192E 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0
#define BT_INFO_8192E_2ANT_B_FTP BIT7
#define BT_INFO_8192E_2ANT_B_A2DP BIT6
#define BT_INFO_8192E_2ANT_B_HID BIT5
#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2
typedef enum _BT_INFO_SRC_8192E_2ANT{
BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_2ANT_MAX
}BT_INFO_SRC_8192E_2ANT,*PBT_INFO_SRC_8192E_2ANT;
typedef enum _BT_8192E_2ANT_BT_STATUS{
BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_2ANT_BT_STATUS_MAX
}BT_8192E_2ANT_BT_STATUS,*PBT_8192E_2ANT_BT_STATUS;
typedef enum _BT_8192E_2ANT_COEX_ALGO{
BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_2ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2,
BT_8192E_2ANT_COEX_ALGO_HID = 0x3,
BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4,
BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6,
BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7,
BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb,
BT_8192E_2ANT_COEX_ALGO_MAX = 0xc
}BT_8192E_2ANT_COEX_ALGO,*PBT_8192E_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8192E_2ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u1Byte preSsType;
u1Byte curSsType;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curRaMaskType;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
} COEX_DM_8192E_2ANT, *PCOEX_DM_8192E_2ANT;
typedef struct _COEX_STA_8192E_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8192E_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8192E_2ANT, *PCOEX_STA_8192E_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192e2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8192e2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192e2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

4823
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8723b1Ant.c
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315
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8723b1Ant.h
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@ -1,315 +0,0 @@
//===========================================
// The following is for 8723B 1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1
#define BT_INFO_8723B_1ANT_B_FTP BIT7
#define BT_INFO_8723B_1ANT_B_A2DP BIT6
#define BT_INFO_8723B_1ANT_B_HID BIT5
#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2
#define BT_8723B_1ANT_WIFI_NOISY_THRESH 30 //max: 255
typedef enum _BT_INFO_SRC_8723B_1ANT{
BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_1ANT_MAX
}BT_INFO_SRC_8723B_1ANT,*PBT_INFO_SRC_8723B_1ANT;
typedef enum _BT_8723B_1ANT_BT_STATUS{
BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_1ANT_BT_STATUS_MAX
}BT_8723B_1ANT_BT_STATUS,*PBT_8723B_1ANT_BT_STATUS;
typedef enum _BT_8723B_1ANT_WIFI_STATUS{
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8723B_1ANT_WIFI_STATUS_MAX
}BT_8723B_1ANT_WIFI_STATUS,*PBT_8723B_1ANT_WIFI_STATUS;
typedef enum _BT_8723B_1ANT_COEX_ALGO{
BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_1ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_1ANT_COEX_ALGO_HID = 0x2,
BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8723B_1ANT_COEX_ALGO,*PBT_8723B_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8723B_1ANT{
// hw setting
u1Byte preAntPosType;
u1Byte curAntPosType;
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
u4Byte nArpCnt;
u1Byte errorCondition;
} COEX_DM_8723B_1ANT, *PCOEX_DM_8723B_1ANT;
typedef struct _COEX_STA_8723B_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bBtHiPriLinkExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte specialPktPeriodCnt;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
s1Byte btRssi;
BOOLEAN bBtTxRxMask;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723B_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723B_1ANT_MAX];
BOOLEAN bBtWhckTest;
BOOLEAN bC2hBtInquiryPage;
BOOLEAN bC2hBtPage; //Add for win8.1 page out issue
BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue
u1Byte btRetryCnt;
u1Byte btInfoExt;
u4Byte popEventCnt;
u1Byte nScanAPNum;
u4Byte nCRCOK_CCK;
u4Byte nCRCOK_11g;
u4Byte nCRCOK_11n;
u4Byte nCRCOK_11nAgg;
u4Byte nCRCErr_CCK;
u4Byte nCRCErr_11g;
u4Byte nCRCErr_11n;
u4Byte nCRCErr_11nAgg;
BOOLEAN bCCKLock;
BOOLEAN bPreCCKLock;
BOOLEAN bCCKEverLock;
u1Byte nCoexTableType;
BOOLEAN bForceLpsOn;
}COEX_STA_8723B_1ANT, *PCOEX_STA_8723B_1ANT;
#define BT_8723B_1ANT_ANTDET_PSD_POINTS 256 //MAX:1024
#define BT_8723B_1ANT_ANTDET_PSD_AVGNUM 1 //MAX:3
typedef struct _PSDSCAN_STA_8723B_1ANT{
BOOLEAN bIsAntDetEnable;
BOOLEAN bIsAntIsoEnable;
BOOLEAN bIsPSDScanEnable;
u4Byte realcentFreq; //ex:2412
s4Byte realoffset;
u4Byte realspan;
u4Byte realseconds;
BOOLEAN bAntDetFinish;
u1Byte nAntIsolation;
u4Byte nPSDBandWidth; //unit: Hz
u4Byte nPSDPoint; //128/256/512/1024
u4Byte nPSDReport[1024]; //unit:dB (20logx), 0~255
u4Byte nPSDReport_MaxHold[1024]; //unit:dB (20logx), 0~255
u4Byte nPSDStartPoint;
u4Byte nPSDStopPoint;
u4Byte nPSDMaxValuePoint;
u4Byte nPSDMaxValue;
u4Byte nPSDStartBase;
u4Byte nPSDAvgNum; // 1/8/16/32
u4Byte nPSDGenCount;
u4Byte nPSDGenTotalCount;
BOOLEAN bIsSetupFinish;
BOOLEAN bIsPSDRunning;
BOOLEAN bIsPSDShowMaxOnly;
} PSDSCAN_STA_8723B_1ANT, *PPSDSCAN_STA_8723B_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723b1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_PreLoadFirmware(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8723b1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723b1ant_RfStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8723b1ant_CoexDmReset(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_AntennaDetection(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte centFreq,
IN u4Byte offset,
IN u4Byte span,
IN u4Byte seconds
);
VOID
EXhalbtc8723b1ant_AntennaIsolation(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte centFreq,
IN u4Byte offset,
IN u4Byte span,
IN u4Byte seconds
);
VOID
EXhalbtc8723b1ant_PSDScan(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte centFreq,
IN u4Byte offset,
IN u4Byte span,
IN u4Byte seconds
);
VOID
EXhalbtc8723b1ant_DisplayAntIsolation(
IN PBTC_COEXIST pBtCoexist
);

2941
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8812a1Ant.c
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drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8812a1Ant.h
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@ -1,206 +0,0 @@
//===========================================
// The following is for 8812A_1ANT BT Co-exist definition
//===========================================
#define BT_INFO_8812A_1ANT_B_FTP BIT7
#define BT_INFO_8812A_1ANT_B_A2DP BIT6
#define BT_INFO_8812A_1ANT_B_HID BIT5
#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8812A_1ANT_B_CONNECTION BIT0
#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2
#define BTC_8812A_1ANT_SWITCH_TO_WIFI 0
#define BTC_8812A_1ANT_SWITCH_TO_BT 1
typedef enum _BT_INFO_SRC_8812A_1ANT{
BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8812A_1ANT_MAX
}BT_INFO_SRC_8812A_1ANT,*PBT_INFO_SRC_8812A_1ANT;
typedef enum _BT_8812A_1ANT_BT_STATUS{
BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8812A_1ANT_BT_STATUS_MAX
}BT_8812A_1ANT_BT_STATUS,*PBT_8812A_1ANT_BT_STATUS;
typedef enum _BT_8812A_1ANT_WIFI_STATUS{
BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8812A_1ANT_WIFI_STATUS_MAX
}BT_8812A_1ANT_WIFI_STATUS,*PBT_8812A_1ANT_WIFI_STATUS;
typedef enum _BT_8812A_1ANT_COEX_ALGO{
BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8812A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8812A_1ANT_COEX_ALGO_HID = 0x2,
BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8812A_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8812A_1ANT_COEX_ALGO,*PBT_8812A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8812A_1ANT{
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte errorCondition;
} COEX_DM_8812A_1ANT, *PCOEX_DM_8812A_1ANT;
typedef struct _COEX_STA_8812A_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8812A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8812A_1ANT_MAX];
u4Byte btInfoQueryCnt;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8812A_1ANT, *PCOEX_STA_8812A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8812a1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8812a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8812a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8812a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);

4790
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8812a2Ant.c
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drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8812a2Ant.h
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//===========================================
// The following is for 8812A 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8812A_2ANT 0
#define BT_INFO_8812A_2ANT_B_FTP BIT7
#define BT_INFO_8812A_2ANT_B_A2DP BIT6
#define BT_INFO_8812A_2ANT_B_HID BIT5
#define BT_INFO_8812A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8812A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8812A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8812A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8812A_2ANT_B_CONNECTION BIT0
#define BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT 2
typedef enum _BT_INFO_SRC_8812A_2ANT{
BT_INFO_SRC_8812A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8812A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8812A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8812A_2ANT_MAX
}BT_INFO_SRC_8812A_2ANT,*PBT_INFO_SRC_8812A_2ANT;
typedef enum _BT_8812A_2ANT_BT_STATUS{
BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8812A_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8812A_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8812A_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8812A_2ANT_BT_STATUS_MAX
}BT_8812A_2ANT_BT_STATUS,*PBT_8812A_2ANT_BT_STATUS;
typedef enum _BT_8812A_2ANT_COEX_ALGO{
BT_8812A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8812A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8812A_2ANT_COEX_ALGO_SCO_HID = 0x2,
BT_8812A_2ANT_COEX_ALGO_HID = 0x3,
BT_8812A_2ANT_COEX_ALGO_A2DP = 0x4,
BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
BT_8812A_2ANT_COEX_ALGO_PANEDR = 0x6,
BT_8812A_2ANT_COEX_ALGO_PANHS = 0x7,
BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
BT_8812A_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xb,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP = 0xc,
BT_8812A_2ANT_COEX_ALGO_MAX = 0xd
}BT_8812A_2ANT_COEX_ALGO,*PBT_8812A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8812A_2ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bAutoTdmaAdjustLowRssi;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curRaMaskType;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
} COEX_DM_8812A_2ANT, *PCOEX_DM_8812A_2ANT;
typedef struct _COEX_STA_8812A_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8812A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8812A_2ANT_MAX];
u4Byte btInfoQueryCnt;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8812A_2ANT, *PCOEX_STA_8812A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8812a2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8812a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8812a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);

3468
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8821a1Ant.c
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drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8821a1Ant.h
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//===========================================
// The following is for 8821A 1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8821A_1ANT 1
#define BT_INFO_8821A_1ANT_B_FTP BIT7
#define BT_INFO_8821A_1ANT_B_A2DP BIT6
#define BT_INFO_8821A_1ANT_B_HID BIT5
#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
#define BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT 2
typedef enum _BT_INFO_SRC_8821A_1ANT{
BT_INFO_SRC_8821A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_1ANT_MAX
}BT_INFO_SRC_8821A_1ANT,*PBT_INFO_SRC_8821A_1ANT;
typedef enum _BT_8821A_1ANT_BT_STATUS{
BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8821A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8821A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8821A_1ANT_BT_STATUS_MAX
}BT_8821A_1ANT_BT_STATUS,*PBT_8821A_1ANT_BT_STATUS;
typedef enum _BT_8821A_1ANT_WIFI_STATUS{
BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8821A_1ANT_WIFI_STATUS_MAX
}BT_8821A_1ANT_WIFI_STATUS,*PBT_8821A_1ANT_WIFI_STATUS;
typedef enum _BT_8821A_1ANT_COEX_ALGO{
BT_8821A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_1ANT_COEX_ALGO_HID = 0x2,
BT_8821A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8821A_1ANT_COEX_ALGO,*PBT_8821A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_1ANT{
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
u4Byte nArpCnt;
u1Byte errorCondition;
} COEX_DM_8821A_1ANT, *PCOEX_DM_8821A_1ANT;
typedef struct _COEX_STA_8821A_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte specialPktPeriodCnt;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
BOOLEAN bBtTxRxMask;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
BOOLEAN bC2hBtPage; //Add for win8.1 page out issue
BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8821A_1ANT, *PCOEX_STA_8821A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821a1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8821a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8821a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

4101
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8821a2Ant.c
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drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8821a2Ant.h
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//===========================================
// The following is for 8821A 2Ant BT Co-exist definition
//===========================================
#define BT_INFO_8821A_2ANT_B_FTP BIT7
#define BT_INFO_8821A_2ANT_B_A2DP BIT6
#define BT_INFO_8821A_2ANT_B_HID BIT5
#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT 2
typedef enum _BT_INFO_SRC_8821A_2ANT{
BT_INFO_SRC_8821A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_2ANT_MAX
}BT_INFO_SRC_8821A_2ANT,*PBT_INFO_SRC_8821A_2ANT;
typedef enum _BT_8821A_2ANT_BT_STATUS{
BT_8821A_2ANT_BT_STATUS_IDLE = 0x0,
BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8821A_2ANT_BT_STATUS_MAX
}BT_8821A_2ANT_BT_STATUS,*PBT_8821A_2ANT_BT_STATUS;
typedef enum _BT_8821A_2ANT_COEX_ALGO{
BT_8821A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_2ANT_COEX_ALGO_HID = 0x2,
BT_8821A_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_2ANT_COEX_ALGO_MAX = 0xb,
}BT_8821A_2ANT_COEX_ALGO,*PBT_8821A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_2ANT{
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8821A_2ANT, *PCOEX_DM_8821A_2ANT;
typedef struct _COEX_STA_8821A_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8821A_2ANT, *PCOEX_STA_8821A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821a2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8821a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8821a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

4398
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8821aCsr2Ant.c
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File diff suppressed because it is too large Load Diff

207
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC-BTCoexist/HalBtc8821aCsr2Ant.h
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@ -1,207 +0,0 @@
//===========================================
// The following is for 8821A_CSR 2Ant BT Co-exist definition
//===========================================
#define BT_INFO_8821A_CSR_2ANT_B_FTP BIT7
#define BT_INFO_8821A_CSR_2ANT_B_A2DP BIT6
#define BT_INFO_8821A_CSR_2ANT_B_HID BIT5
#define BT_INFO_8821A_CSR_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_CSR_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_CSR_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_CSR_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_CSR_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT 2
typedef enum _BT_INFO_SRC_8821A_CSR_2ANT{
BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_CSR_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_CSR_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_CSR_2ANT_MAX
}BT_INFO_SRC_8821A_CSR_2ANT,*PBT_INFO_SRC_8821A_CSR_2ANT;
typedef enum _BT_8821A_CSR_2ANT_BT_STATUS{
BT_8821A_CSR_2ANT_BT_STATUS_IDLE = 0x0,
BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8821A_CSR_2ANT_BT_STATUS_MAX
}BT_8821A_CSR_2ANT_BT_STATUS,*PBT_8821A_CSR_2ANT_BT_STATUS;
typedef enum _BT_8821A_CSR_2ANT_COEX_ALGO{
BT_8821A_CSR_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_CSR_2ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_CSR_2ANT_COEX_ALGO_HID = 0x2,
BT_8821A_CSR_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_CSR_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_CSR_2ANT_COEX_ALGO_MAX = 0xb,
}BT_8821A_CSR_2ANT_COEX_ALGO,*PBT_8821A_CSR_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_CSR_2ANT{
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[6];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curAmpduNumType;
u1Byte preAmpduNumType;
u2Byte backupAmpduMaxNum;
u1Byte curAmpduTimeType;
u1Byte preAmpduTimeType;
u1Byte backupAmpduMaxTime;
u1Byte curArfrType;
u1Byte preArfrType;
u4Byte backupArfrCnt1;
u4Byte backupArfrCnt2;
u1Byte curRetryLimitType;
u1Byte preRetryLimitType;
u2Byte backupRetryLimit;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8821A_CSR_2ANT, *PCOEX_DM_8821A_CSR_2ANT;
typedef struct _COEX_STA_8821A_CSR_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bSlave;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_CSR_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_CSR_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8821A_CSR_2ANT, *PCOEX_STA_8821A_CSR_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821aCsr2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8821aCsr2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821aCsr2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8821aCsr2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

530
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/HalPhyRf.c
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@ -1,530 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
do {\
for(_offset = 0; _offset < _size; _offset++)\
{\
if(_deltaThermal < thermalThreshold[_direction][_offset])\
{\
if(_offset != 0)\
_offset--;\
break;\
}\
} \
if(_offset >= _size)\
_offset = _size-1;\
} while(0)
void ConfigureTxpowerTrack(
IN PDM_ODM_T pDM_Odm,
OUT PTXPWRTRACK_CFG pConfig
)
{
#if RTL8192E_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8192E)
ConfigureTxpowerTrack_8192E(pConfig);
#endif
#if RTL8821A_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8821)
ConfigureTxpowerTrack_8821A(pConfig);
#endif
#if RTL8812A_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8812)
ConfigureTxpowerTrack_8812A(pConfig);
#endif
#if RTL8188E_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8188E)
ConfigureTxpowerTrack_8188E(pConfig);
#endif
#if RTL8723B_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8723B)
ConfigureTxpowerTrack_8723B(pConfig);
#endif
}
//======================================================================
// <20121113, Kordan> This function should be called when TxAGC changed.
// Otherwise the previous compensation is gone, because we record the
// delta of temperature between two TxPowerTracking watch dogs.
//
// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
// need to call this function.
//======================================================================
VOID
ODM_ClearTxPowerTrackingState(
IN PDM_ODM_T pDM_Odm
)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
u1Byte p = 0;
pDM_Odm->BbSwingIdxCckBase = pDM_Odm->DefaultCckIndex;
pDM_Odm->BbSwingIdxCck = pDM_Odm->DefaultCckIndex;
pDM_Odm->RFCalibrateInfo.CCK_index = 0;
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
{
pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->BbSwingIdxOfdm[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = 0;
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p] = 0;
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
pDM_Odm->Absolute_OFDMSwingIdx[p] = 0; // Initial Mix mode power tracking
pDM_Odm->Remnant_OFDMSwingIdx[p] = 0;
}
pDM_Odm->Modify_TxAGC_Flag_PathA= FALSE; //Initial at Modify Tx Scaling Mode
pDM_Odm->Modify_TxAGC_Flag_PathB= FALSE; //Initial at Modify Tx Scaling Mode
pDM_Odm->Remnant_CCKSwingIdx= 0;
pDM_Odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter;
pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = pHalData->EEPROMThermalMeter;
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = pHalData->EEPROMThermalMeter;
}
VOID
ODM_TXPowerTrackingCallback_ThermalMeter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER Adapter
#endif
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
#endif
#endif
u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
u1Byte ThermalValue_AVG_count = 0;
u4Byte ThermalValue_AVG = 0;
u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur
u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel)
TXPWRTRACK_CFG c;
//4 1. The following TWO tables decide the final index of OFDM/CCK swing table.
pu1Byte deltaSwingTableIdx_TUP_A;
pu1Byte deltaSwingTableIdx_TDOWN_A;
pu1Byte deltaSwingTableIdx_TUP_B;
pu1Byte deltaSwingTableIdx_TDOWN_B;
//4 2. Initilization ( 7 steps in total )
ConfigureTxpowerTrack(pDM_Odm, &c);
(*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_A, (pu1Byte*)&deltaSwingTableIdx_TDOWN_A,
(pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B);
pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug
pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE;
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // <Kordan> We should keep updating the control variable according to HalData.
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
if (pDM_Odm->mp_mode == TRUE)
#endif
// <Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files.
pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317;
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("===>ODM_TXPowerTrackingCallback_ThermalMeter, \
\n pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase[A]: %d, pDM_Odm->DefaultOfdmIndex: %d\n",
pDM_Odm->BbSwingIdxCckBase, pDM_Odm->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pDM_Odm->DefaultOfdmIndex));
ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E
if( ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl || pHalData->EEPROMThermalMeter == 0 ||
pHalData->EEPROMThermalMeter == 0xFF)
return;
//4 3. Initialize ThermalValues of RFCalibrateInfo
if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
}
//4 4. Calculate average thermal meter
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue;
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++;
if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) //Average times = c.AverageThermalNum
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
for(i = 0; i < c.AverageThermalNum; i++)
{
if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i])
{
ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i];
ThermalValue_AVG_count++;
}
}
if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times
{
ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter));
}
//4 5. Calculate delta, delta_LCK, delta_IQK.
//"delta" here is used to determine whether thermal value changes or not.
delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue);
delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue);
delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
//4 6. If necessary, do LCK.
if ((delta_LCK >= c.Threshold_IQK)) // Delta temperature is equal to or larger than 20 centigrade.
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK));
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
if(c.PHY_LCCalibrate)
(*c.PHY_LCCalibrate)(pDM_Odm);
}
//3 7. If necessary, move the index of swing table to adjust Tx power.
if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
{
//"delta" here is used to record the absolute value of differrence.
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
#else
delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
#endif
if (delta >= TXPWR_TRACK_TABLE_SIZE)
delta = TXPWR_TRACK_TABLE_SIZE - 1;
//4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(ThermalValue > pHalData->EEPROMThermalMeter) {
#else
if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_A] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A] = deltaSwingTableIdx_TUP_A[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = deltaSwingTableIdx_TUP_A[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A]));
if(c.RfPathCount > 1)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] = deltaSwingTableIdx_TUP_B[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = deltaSwingTableIdx_TUP_B[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B]));
}
}
else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_A] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A] = -1 * deltaSwingTableIdx_TDOWN_A[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A]));
if(c.RfPathCount > 1)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] = -1 * deltaSwingTableIdx_TDOWN_B[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B]));
}
}
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("\n\n================================ [Path-%c] Calculating PowerIndexOffset ================================\n", (p == ODM_RF_PATH_A ? 'A' : 'B')));
if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]) // If Thermal value changes but lookup table value still the same
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
else
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]; // Power Index Diff between 2 times Power Tracking
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("[Path-%c] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n",
(p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p], pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p],
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]));
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->BbSwingIdxOfdmBase[p] + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p];
pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p];
pDM_Odm->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index;
pDM_Odm->BbSwingIdxOfdm[p] = pDM_Odm->RFCalibrateInfo.OFDM_index[p];
// *************Print BB Swing Base and Index Offset*************
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n",
pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex[%c](%d) + PowerIndexOffset(%d)\n",
pDM_Odm->BbSwingIdxOfdm[p], (p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->BbSwingIdxOfdmBase[p], pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]));
//4 7.1 Handle boundary conditions of index.
if(pDM_Odm->RFCalibrateInfo.OFDM_index[p] > c.SwingTableSize_OFDM-1)
{
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = c.SwingTableSize_OFDM-1;
}
else if (pDM_Odm->RFCalibrateInfo.OFDM_index[p] < OFDM_min_index)
{
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = OFDM_min_index;
}
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("\n\n========================================================================================================\n"));
if(pDM_Odm->RFCalibrateInfo.CCK_index > c.SwingTableSize_CCK-1)
pDM_Odm->RFCalibrateInfo.CCK_index = c.SwingTableSize_CCK-1;
//else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0)
//pDM_Odm->RFCalibrateInfo.CCK_index = 0;
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d\n",
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl, ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
pDM_Odm->RFCalibrateInfo.CCK_index, pDM_Odm->BbSwingIdxCckBase)); //Print Swing base & current
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%c]: %d\n",
pDM_Odm->RFCalibrateInfo.OFDM_index[p], (p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->BbSwingIdxOfdmBase[p]));
}
if ((pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A] != 0 ||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B] != 0 ) &&
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
{
//4 7.2 Configure the Swing Table to adjust Tx Power.
pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking.
//
// 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
// to increase TX power. Otherwise, EVM will be bad.
//
// 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Increasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
if(c.RfPathCount > 1)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Increasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
}
else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Decreasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
if(c.RfPathCount > 1)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Decreasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
if (ThermalValue > pHalData->EEPROMThermalMeter)
#else
if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)
#endif
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E ||
pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking MIX_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking BBSWING_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
}
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E ||
pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking MIX_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel);
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking BBSWING_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
}
}
pDM_Odm->BbSwingIdxCckBase = pDM_Odm->BbSwingIdxCck; // Record last time Power Tracking result as base.
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->BbSwingIdxOfdm[p];
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("pDM_Odm->RFCalibrateInfo.ThermalValue = %d ThermalValue= %d\n", pDM_Odm->RFCalibrateInfo.ThermalValue, ThermalValue));
pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; //Record last Power Tracking Thermal Value
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (RTL8723B_SUPPORT == 0)
// Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).
if ((delta_IQK >= c.Threshold_IQK)) {
if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress)
(*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8);
}
#endif
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("<===ODM_TXPowerTrackingCallback_ThermalMeter\n"));
pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
}
//3============================================================
//3 IQ Calibration
//3============================================================
VOID
ODM_ResetIQKResult(
IN PDM_ODM_T pDM_Odm
)
{
u1Byte i;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
if (!IS_HARDWARE_TYPE_8192D(Adapter))
return;
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u4Byte)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING)), IQK_Matrix_Settings_NUM));
//0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc
for(i = 0; i < IQK_Matrix_Settings_NUM; i++)
{
{
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][0] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][2] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][4] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][6] = 0x100;
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][1] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][3] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][5] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][7] = 0x0;
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].bIQKDone = FALSE;
}
}
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl)
{
u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165};
u1Byte place = chnl;
if(chnl > 14)
{
for(place = 14; place<sizeof(channel_all); place++)
{
if(channel_all[place] == chnl)
{
return place-13;
}
}
}
return 0;
}
#endif

24
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/Mp_Precomp.h
View File

@ -1,24 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//#include <Precomp.h>
//#include "phydm_precomp.h"
//#include "../phydm_precomp.h"

880
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/PhyDM_Adaptivity.c
View File

@ -1,880 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
Phydm_CheckAdaptivity(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)
{
if(pDM_Odm->bAdaOn == TRUE)
{
if(pDM_Odm->DynamicLinkAdaptivity == TRUE)
{
if(pDM_Odm->bLinked && pDM_Odm->bCheck == FALSE)
{
Phydm_NHMCounterStatistics(pDM_Odm);
Phydm_CheckEnvironment(pDM_Odm);
}
else if(!pDM_Odm->bLinked)
{
pDM_Odm->bCheck = FALSE;
}
}
else
{
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
pDM_Odm->adaptivity_flag = TRUE;
}
}
else
{
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
pDM_Odm->adaptivity_flag = FALSE;
}
}
}
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
//PHY parameters initialize for ac series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, 0xC350); //0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); //0x994[31:16]=0xffff th_9, th_10
//ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff5c); //0x998=0xffffff5c th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); //0x998=0xffffff52 th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); //0x99c=0xffffffff th_7, th_6, th_5, th_4
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); //0x9a0[7:0]=0xff th_8
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x7); //0x994[9:8]=3 enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x1); //0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); //0x9e8[7]=1 max power among all RX ants
}
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
//PHY parameters initialize for n series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0xC350); //0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms
//ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x4e20); //0x894[31:16]=0x4e20 Time duration for NHM unit: 4us, 0x4e20=80ms
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); //0x890[31:16]=0xffff th_9, th_10
//ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff5c); //0x898=0xffffff5c th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); //0x898=0xffffff52 th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); //0x89c=0xffffffff th_7, th_6, th_5, th_4
ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); //0xe28[7:0]=0xff th_8
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); //0x890[9:8]=3 enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x1); //0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); //0xc0c[7]=1 max power among all RX ants
}
}
VOID
Phydm_NHMCounterStatistics(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
// Get NHM report
Phydm_GetNHMCounterStatistics(pDM_Odm);
// Reset NHM counter
Phydm_NHMCounterStatisticsReset(pDM_Odm);
}
VOID
Phydm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte value32 = 0;
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);
pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);
pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1)>>8);
}
VOID
Phydm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);
}
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
}
}
VOID
Phydm_NHMBBInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pDM_Odm->adaptivity_flag = FALSE;
pDM_Odm->tolerance_cnt = 3;
pDM_Odm->NHMLastTxOkcnt = 0;
pDM_Odm->NHMLastRxOkcnt = 0;
pDM_Odm->NHMCurTxOkcnt = 0;
pDM_Odm->NHMCurRxOkcnt = 0;
}
VOID
Phydm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)L2H);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)H2L);
}
else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte0, (u1Byte)L2H);
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte1, (u1Byte)H2L);
}
}
VOID
Phydm_SetTRxMux(
IN PVOID pDM_VOID,
IN PhyDM_Trx_MUX_Type txMode,
IN PhyDM_Trx_MUX_Type rxMode
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3|BIT2|BIT1, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect
if(pDM_Odm->RFType > ODM_1T1R)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3|BIT2|BIT1, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect
}
}
else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11|BIT10|BIT9|BIT8, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect
if(pDM_Odm->RFType > ODM_1T1R)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11|BIT10|BIT9|BIT8, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect
}
}
}
VOID
Phydm_MACEDCCAState(
IN PVOID pDM_VOID,
IN PhyDM_MACEDCCA_Type State
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(State == PhyDM_IGNORE_EDCCA)
{
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); //ignore EDCCA reg520[15]=1
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); //reg524[11]=0
}
else // don't set MAC ignore EDCCA signal
{
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); //don't ignore EDCCA reg520[15]=0
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); //reg524[11]=1
}
pDM_Odm->EDCCA_enable_state = State;
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d \n", State));
}
BOOLEAN
Phydm_CalNHMcnt(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u2Byte Base = 0;
Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;
if(Base != 0)
{
pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;
pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;
}
if((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)
return TRUE; // clean environment
else
return FALSE; //noisy environment
}
VOID
Phydm_CheckEnvironment(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
BOOLEAN isCleanEnvironment = FALSE;
u1Byte i, clean = 0;
if(pDM_Odm->bFirstLink == TRUE)
{
pDM_Odm->adaptivity_flag = TRUE;
pDM_Odm->bFirstLink = FALSE;
return;
}
else
{
if(pDM_Odm->NHMWait < 3) // Start enter NHM after 4 NHMWait
{
pDM_Odm->NHMWait ++;
Phydm_NHMCounterStatistics(pDM_Odm);
return;
}
else
{
Phydm_NHMCounterStatistics(pDM_Odm);
isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
if(isCleanEnvironment == TRUE)
{
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; //mode 1
pDM_Odm->TH_EDCCA_HL_diff= pDM_Odm->TH_EDCCA_HL_diff_backup;
#endif
pDM_Odm->adaptivity_flag = TRUE;
}
else
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
#else
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; // for AP mode 2
pDM_Odm->TH_EDCCA_HL_diff= pDM_Odm->TH_EDCCA_HL_diff_mode2;
#endif
pDM_Odm->adaptivity_flag = FALSE;
}
pDM_Odm->bFirstLink = TRUE;
pDM_Odm->bCheck = TRUE;
}
}
}
VOID
Phydm_NHMBB(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
BOOLEAN bCleanEnvironment;
bCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
pDM_Odm->NHMCurTxOkcnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_Odm->NHMLastTxOkcnt;
pDM_Odm->NHMCurRxOkcnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_Odm->NHMLastRxOkcnt;
pDM_Odm->NHMLastTxOkcnt = *(pDM_Odm->pNumTxBytesUnicast);
pDM_Odm->NHMLastRxOkcnt = *(pDM_Odm->pNumRxBytesUnicast);
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("cnt_0=%d, cnt_1=%d, bCleanEnvironment = %d, NHMCurTxOkcnt = %llu, NHMCurRxOkcnt = %llu\n",
pDM_Odm->NHM_cnt_0, pDM_Odm->NHM_cnt_1, bCleanEnvironment, pDM_Odm->NHMCurTxOkcnt, pDM_Odm->NHMCurRxOkcnt));
if(pDM_Odm->NHMWait < 4) // Start enter NHM after 4 NHMWait
{
pDM_Odm->NHMWait ++;
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
}
else if ( ((pDM_Odm->NHMCurTxOkcnt>>10) > 2) && ((pDM_Odm->NHMCurTxOkcnt) + 1 > (u8Byte)(pDM_Odm->NHMCurRxOkcnt<<2) + 1)) //Tx > 4*Rx and Tx > 2Mb possible for adaptivity test
{
if(bCleanEnvironment == TRUE || pDM_Odm->adaptivity_flag == TRUE)
{
//Enable EDCCA since it is possible running Adaptivity testing
pDM_Odm->adaptivity_flag = TRUE;
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
pDM_Odm->tolerance_cnt = 0;
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
#endif
}
else
{
if(pDM_Odm->tolerance_cnt < 3)
pDM_Odm->tolerance_cnt ++;
else
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2 ;
#else
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
#endif
pDM_Odm->adaptivity_flag = FALSE;
}
}
}
else // TX<RX
{
if(pDM_Odm->adaptivity_flag == TRUE && bCleanEnvironment == FALSE)
{
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
pDM_Odm->tolerance_cnt = 0;
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
#endif
}
#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23
#ifdef UNIVERSAL_REPEATER
else if((bCleanEnvironment == TRUE) && (pDM_Odm->VXD_bLinked) && ((pDM_Odm->NHMCurTxOkcnt>>10) > 1)) // clean environment and VXD linked and Tx TP>1Mb
{
pDM_Odm->adaptivity_flag = TRUE;
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
pDM_Odm->tolerance_cnt = 0;
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
}
#endif
#endif // for repeater mode add by YuChen 2014.06.23
else
{
if(pDM_Odm->tolerance_cnt < 3)
pDM_Odm->tolerance_cnt ++;
else
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2 ;
#else
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
#endif
pDM_Odm->adaptivity_flag = FALSE;
}
}
}
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity_flag = %d\n ", pDM_Odm->adaptivity_flag));
}
VOID
Phydm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte value32 =0;
u1Byte cnt, IGI_Pause = 0x7f, IGI_Resume = 0x20, IGI = 0x50; //IGI = 0x50 for cal EDCCA lower bound
u1Byte txEdcca1 = 0, txEdcca0 = 0;
BOOLEAN bAdjust=TRUE;
s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;
s1Byte Diff;
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
ODM_Write_DIG(pDM_Odm, IGI_Pause);
Diff = IGI_target -(s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if(TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
ODM_delay_ms(5);
while(bAdjust)
{
for(cnt=0; cnt<20; cnt ++)
{
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11N, bMaskDWord);
else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11AC, bMaskDWord);
if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8723B|ODM_RTL8188E)))
txEdcca1 = txEdcca1 + 1;
else if(value32 & BIT29)
txEdcca1 = txEdcca1 + 1;
else
txEdcca0 = txEdcca0 + 1;
}
if(txEdcca1 > 9 )
{
IGI = IGI -1;
TH_L2H_dmc = TH_L2H_dmc + 1;
if(TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
txEdcca1 = 0;
txEdcca0 = 0;
if(TH_L2H_dmc == 10)
{
bAdjust = FALSE;
pDM_Odm->H2L_lb = TH_H2L_dmc;
pDM_Odm->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
}
}
else
{
bAdjust = FALSE;
pDM_Odm->H2L_lb = TH_H2L_dmc;
pDM_Odm->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
}
}
Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
ODM_Write_DIG(pDM_Odm, IGI_Resume);
Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); // resume to no link state
}
VOID
Phydm_AdaptivityInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER pAdapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense;
pDM_Odm->NHM_enable = (BOOLEAN)pMgntInfo->RegNHMEnable;
pDM_Odm->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity;
#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode!=0)?TRUE:FALSE;
pDM_Odm->NHM_enable = (BOOLEAN)pDM_Odm->Adapter->registrypriv.nhm_en;
pDM_Odm->DynamicLinkAdaptivity = FALSE; // Jeff please add this
#endif
#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
if(pDM_Odm->Carrier_Sense_enable == FALSE)
{
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
if( pMgntInfo->RegL2HForAdaptivity != 0 )
pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;
else
#endif
pDM_Odm->TH_L2H_ini = 0xf5; // -7
}
else
{
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
if( pMgntInfo->RegL2HForAdaptivity != 0 )
pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;
else
#endif
pDM_Odm->TH_L2H_ini = 0xa;
}
pDM_Odm->AdapEn_RSSI = 20;
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
if( pMgntInfo->RegHLDiffForAdaptivity != 0 )
pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity;
else
#endif
pDM_Odm->TH_EDCCA_HL_diff = 7;
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
if(pDM_Odm->Carrier_Sense_enable){
pDM_Odm->TH_L2H_ini = 10;
pDM_Odm->TH_EDCCA_HL_diff = 7;
pDM_Odm->AdapEn_RSSI = 30;
}
else
{
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; //set by mib
pDM_Odm->TH_EDCCA_HL_diff = 7;
pDM_Odm->AdapEn_RSSI = 20;
}
pDM_Odm->TH_L2H_ini_mode2 = 20;
pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;
//pDM_Odm->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;
pDM_Odm->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff ;
if(priv->pshare->rf_ft_var.adaptivity_enable == 2)
pDM_Odm->DynamicLinkAdaptivity = TRUE;
else
pDM_Odm->DynamicLinkAdaptivity = FALSE;
// pDM_Odm->NHM_enable = FALSE;
#endif
pDM_Odm->IGI_Base = 0x32;
pDM_Odm->IGI_target = 0x1c;
pDM_Odm->ForceEDCCA = 0;
pDM_Odm->H2L_lb= 0;
pDM_Odm->L2H_lb= 0;
pDM_Odm->Adaptivity_IGI_upper = 0;
pDM_Odm->NHMWait = 0;
Phydm_NHMBBInit(pDM_Odm);
pDM_Odm->bCheck = FALSE;
pDM_Odm->bFirstLink = TRUE;
pDM_Odm->bAdaOn = TRUE;
ODM_SetBBReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); // stop counting if EDCCA is asserted
//Search pwdB lower bound
{
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);
Phydm_SearchPwdBLowerBound(pDM_Odm);
}
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
}
BOOLEAN
Phydm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
s1Byte TH_L2H_dmc, TH_H2L_dmc, L2H_nolink_Band4 = 0x7f, H2L_nolink_Band4 = 0x7f;
s1Byte Diff, IGI_target;
BOOLEAN EDCCA_State = FALSE;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
BOOLEAN bFwCurrentInPSMode=FALSE;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
// Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
if(bFwCurrentInPSMode)
return FALSE;
#endif
if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));
// Add by Neil Chen to enable edcca to MP Platform
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
// Adjust EDCCA.
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
Phydm_DynamicEDCCA(pDM_Odm);
#endif
return FALSE;
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if(pMgntInfo->RegEnableAdaptivity== 2)
#else
if (pDM_Odm->Adapter->registrypriv.adaptivity_en == 2)
#endif
{
if(pDM_Odm->Carrier_Sense_enable == FALSE) // check domain Code for Adaptivity or CarrierSense
{
if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
!(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d \n", pDM_Odm->odm_Regulation5G));
return FALSE;
}
else if((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
!(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d \n", pDM_Odm->odm_Regulation2_4G));
return FALSE;
}
else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));
return FALSE;
}
}
else
{
if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
!(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
return FALSE;
}
else if((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
!(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
return FALSE;
}
else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));
return FALSE;
}
}
}
#endif
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n",
pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI));
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable
if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20
IGI_target = pDM_Odm->IGI_Base;
else if(*pDM_Odm->pBandWidth == ODM_BW40M)
IGI_target = pDM_Odm->IGI_Base + 2;
else if(*pDM_Odm->pBandWidth == ODM_BW80M)
IGI_target = pDM_Odm->IGI_Base + 2;
else
IGI_target = pDM_Odm->IGI_Base;
pDM_Odm->IGI_target = (u1Byte) IGI_target;
if(*pDM_Odm->pChannel >= 149) // Band4 -> for AP : mode2, for sd4 and sd7 : turnoff adaptivity
{
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
if(pDM_Odm->bLinked)
{
Diff = IGI_target -(s1Byte)IGI;
L2H_nolink_Band4 = pDM_Odm->TH_L2H_ini_mode2 + Diff;
if(L2H_nolink_Band4 > 10)
L2H_nolink_Band4 = 10;
H2L_nolink_Band4 = L2H_nolink_Band4 - pDM_Odm->TH_EDCCA_HL_diff_mode2;
}
#endif
Phydm_SetEDCCAThreshold(pDM_Odm, H2L_nolink_Band4, L2H_nolink_Band4);
return FALSE;
}
if(!pDM_Odm->ForceEDCCA)
{
if(pDM_Odm->RSSI_Min > pDM_Odm->AdapEn_RSSI)
EDCCA_State = 1;
else if(pDM_Odm->RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5))
EDCCA_State = 0;
}
else
EDCCA_State = 1;
if(pDM_Odm->Carrier_Sense_enable == FALSE && pDM_Odm->NHM_enable == TRUE)
Phydm_NHMBB(pDM_Odm);
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d, EDCCA_enable_state = %d\n",
(*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, EDCCA_State, pDM_Odm->EDCCA_enable_state));
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, AdapIGIUpper= 0x %x\n", pDM_Odm->RSSI_Min, pDM_Odm->Adaptivity_IGI_upper));
if(EDCCA_State == 1)
{
Diff = IGI_target -(s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if(TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
//replace lower bound to prevent EDCCA always equal 1
if(TH_H2L_dmc < pDM_Odm->H2L_lb)
TH_H2L_dmc = pDM_Odm->H2L_lb;
if(TH_L2H_dmc < pDM_Odm->L2H_lb)
TH_L2H_dmc = pDM_Odm->L2H_lb;
}
else
{
TH_L2H_dmc = 0x7f;
TH_H2L_dmc = 0x7f;
}
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d, adaptivity_flg = %d, bAdaOn = %d, DynamicLinkAdaptivity = %d, NHM_enable = %d\n",
IGI, TH_L2H_dmc, TH_H2L_dmc, pDM_Odm->adaptivity_flag, pDM_Odm->bAdaOn, pDM_Odm->DynamicLinkAdaptivity, pDM_Odm->NHM_enable));
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
return TRUE;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
Phydm_EnableEDCCA(
IN PVOID pDM_VOID
)
{
// This should be moved out of OUTSRC
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
// Enable EDCCA. The value is suggested by SD3 Wilson.
//
// Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.
//
if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter)))
{
//PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD);
}
else
{
//PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00);
}
//PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00);
}
VOID
Phydm_DisableEDCCA(
IN PVOID pDM_VOID
)
{
// Disable EDCCA..
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);
ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f);
}
//
// Description: According to initial gain value to determine to enable or disable EDCCA.
//
// Suggested by SD3 Wilson. Added by tynli. 2011.11.25.
//
VOID
Phydm_DynamicEDCCA(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u1Byte RegC50, RegC58;
BOOLEAN bEDCCAenable = FALSE;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
BOOLEAN bFwCurrentInPSMode=FALSE;
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
// Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
if(bFwCurrentInPSMode)
return;
#endif
//
// 2013/11/14 Ken According to BB team Jame's suggestion, we need to disable soft AP mode EDCCA.
// 2014/01/08 MH For Miracst AP mode test. We need to disable EDCCA. Otherwise, we may stop
// to send beacon in noisy environment or platform.
//
if(ACTING_AS_AP(pAdapter) || ACTING_AS_AP(GetFirstAPAdapter(pAdapter)))
//if(ACTING_AS_AP(pAdapter))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("At least One Port as AP disable EDCCA\n"));
Phydm_DisableEDCCA(pDM_Odm);
if(pHalData->bPreEdccaEnable)
Phydm_DisableEDCCA(pDM_Odm);
pHalData->bPreEdccaEnable = FALSE;
return;
}
RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);
if((RegC50 > 0x28 && RegC58 > 0x28) ||
((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) ||
(pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28))
{
if(!pHalData->bPreEdccaEnable)
{
Phydm_EnableEDCCA(pDM_Odm);
pHalData->bPreEdccaEnable = TRUE;
}
}
else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25))
{
if(pHalData->bPreEdccaEnable)
{
Phydm_DisableEDCCA(pDM_Odm);
pHalData->bPreEdccaEnable = FALSE;
}
}
}
#endif

7883
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm.c
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2100
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm.h
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File diff suppressed because it is too large Load Diff

2273
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_AntDiv.c
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136
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_AntDiv.h
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@ -1,136 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODMANTDIV_H__
#define __ODMANTDIV_H__
#define ANT1_2G 0 // = ANT2_5G
#define ANT2_2G 1 // = ANT1_5G
//Antenna Diversty Control Type
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define TX_BY_REG 0
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#define ODM_RTL8881A 0 //Just for windows driver to jointly use ODM-driver
#endif
#define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_ANTDIV_2G BIT0
#define ODM_ANTDIV_5G BIT1
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
VOID
ODM_AntDivInit(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_AntDiv(
IN PDM_ODM_T pDM_Odm
);
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_UpdateRxIdleAnt(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant
);
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
ODM_SW_AntDiv_Callback(
IN PRT_TIMER pTimer
);
VOID
ODM_SW_AntDiv_WorkitemCallback(
IN PVOID pContext
);
#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
VOID
ODM_SW_AntDiv_Callback(void *FunctionContext);
#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#endif
#if(RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
VOID
odm_FastAntTraining(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingCallback(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingWorkItemCallback(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif
VOID
ODM_Process_RSSIForAntDiv(
IN OUT PDM_ODM_T pDM_Odm,
IN PODM_PHY_INFO_T pPhyInfo,
IN PODM_PACKET_INFO_T pPktinfo
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
ODM_SetTxAntByTxInfo(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
);
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo(
//IN PDM_ODM_T pDM_Odm,
struct rtl8192cd_priv *priv,
struct tx_desc *pdesc,
struct tx_insn *txcfg,
unsigned short aid
);
#endif
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
#endif //#ifndef __ODMANTDIV_H__

363
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_CfoTracking.c
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@ -1,363 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "odm_precomp.h"
VOID
odm_SetCrystalCap(
IN PVOID pDM_VOID,
IN u1Byte CrystalCap
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
BOOLEAN bEEPROMCheck;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
bEEPROMCheck = (pHalData->EEPROMVersion >= 0x01)?TRUE:FALSE;
#else
bEEPROMCheck = TRUE;
#endif
if(pCfoTrack->CrystalCap == CrystalCap)
return;
pCfoTrack->CrystalCap = CrystalCap;
if(pDM_Odm->SupportICType & ODM_RTL8192D)
{
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x000000F0, CrystalCap & 0x0F);
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0xF0000000, ((CrystalCap & 0xF0) >> 4));
}
else if(pDM_Odm->SupportICType & ODM_RTL8188E)
{
// write 0x24[22:17] = 0x24[16:11] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap | (CrystalCap << 6)));
}
else if(pDM_Odm->SupportICType & ODM_RTL8812)
{
// write 0x2C[30:25] = 0x2C[24:19] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap | (CrystalCap << 6)));
}
else if (((pDM_Odm->SupportICType & ODM_RTL8723A) && bEEPROMCheck) ||
(pDM_Odm->SupportICType & ODM_RTL8723B) ||(pDM_Odm->SupportICType & ODM_RTL8192E) ||
(pDM_Odm->SupportICType & ODM_RTL8821))
{
// 0x2C[23:18] = 0x2C[17:12] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap | (CrystalCap << 6)));
}
else if(pDM_Odm->SupportICType & ODM_RTL8821B)
{
// write 0x28[6:1] = 0x24[30:25] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7E000000, CrystalCap);
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7E, CrystalCap);
}
else if(pDM_Odm->SupportICType & ODM_RTL8814A)
{
// write 0x2C[26:21] = 0x2C[20:15] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap | (CrystalCap << 6)));
}
else
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n"));
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap));
}
u1Byte
odm_GetDefaultCrytaltalCap(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte CrystalCap = 0x20;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
CrystalCap = pHalData->CrystalCap;
#else
prtl8192cd_priv priv = pDM_Odm->priv;
if(priv->pmib->dot11RFEntry.xcap > 0)
CrystalCap = priv->pmib->dot11RFEntry.xcap;
#endif
CrystalCap = CrystalCap & 0x3f;
return CrystalCap;
}
VOID
odm_SetATCStatus(
IN PVOID pDM_VOID,
IN BOOLEAN ATCStatus
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
if(pCfoTrack->bATCStatus == ATCStatus)
return;
ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus);
pCfoTrack->bATCStatus = ATCStatus;
}
BOOLEAN
odm_GetATCStatus(
IN PVOID pDM_VOID
)
{
BOOLEAN ATCStatus;
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
ATCStatus = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm));
return ATCStatus;
}
VOID
ODM_CfoTrackingReset(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
u1Byte CrystalCap;
pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
pCfoTrack->bAdjust = TRUE;
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
odm_SetATCStatus(pDM_Odm, TRUE);
#else
if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap)
{
for(CrystalCap = pCfoTrack->CrystalCap; CrystalCap >= pCfoTrack->DefXCap; CrystalCap--)
odm_SetCrystalCap(pDM_Odm, CrystalCap);
}
else
{
for(CrystalCap = pCfoTrack->CrystalCap; CrystalCap <= pCfoTrack->DefXCap; CrystalCap++)
odm_SetCrystalCap(pDM_Odm, CrystalCap);
}
#endif
}
VOID
ODM_CfoTrackingInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm);
pCfoTrack->bAdjust = TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========> \n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x \n",pCfoTrack->bATCStatus, pCfoTrack->DefXCap));
}
VOID
ODM_CfoTracking(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
int CFO_kHz_A, CFO_kHz_B, CFO_ave = 0;
int CFO_ave_diff;
int CrystalCap = (int)pCfoTrack->CrystalCap;
u1Byte Adjust_Xtal = 1;
//4 Support ability
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n"));
return;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking()=========> \n"));
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN && MP_DRIVER == 1)
if(0)
#else
if(!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly)
#endif
{
//4 No link or more than one entry
ODM_CfoTrackingReset(pDM_Odm);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n",
pDM_Odm->bLinked, pDM_Odm->bOneEntryOnly));
}
else
{
//3 1. CFO Tracking
//4 1.1 No new packet
if(pCfoTrack->packetCount == pCfoTrack->packetCount_pre)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): packet counter doesn't change\n"));
return;
}
pCfoTrack->packetCount_pre = pCfoTrack->packetCount;
//4 1.2 Calculate CFO
CFO_kHz_A = (int)(pCfoTrack->CFO_tail[0] * 3125) / 1280;
CFO_kHz_B = (int)(pCfoTrack->CFO_tail[1] * 3125) / 1280;
if(pDM_Odm->RFType < ODM_2T2R)
CFO_ave = CFO_kHz_A;
else
CFO_ave = (int)(CFO_kHz_A + CFO_kHz_B) >> 1;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): CFO_kHz_A = %dkHz, CFO_kHz_B = %dkHz, CFO_ave = %dkHz\n",
CFO_kHz_A, CFO_kHz_B, CFO_ave));
//4 1.3 Avoid abnormal large CFO
CFO_ave_diff = (pCfoTrack->CFO_ave_pre >= CFO_ave)?(pCfoTrack->CFO_ave_pre - CFO_ave):(CFO_ave - pCfoTrack->CFO_ave_pre);
if(CFO_ave_diff > 20 && pCfoTrack->largeCFOHit == 0 && !pCfoTrack->bAdjust)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n"));
pCfoTrack->largeCFOHit = 1;
return;
}
else
pCfoTrack->largeCFOHit = 0;
pCfoTrack->CFO_ave_pre = CFO_ave;
//4 1.4 Dynamic Xtal threshold
if(pCfoTrack->bAdjust == FALSE)
{
if(CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH))
pCfoTrack->bAdjust = TRUE;
}
else
{
if(CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW))
pCfoTrack->bAdjust = FALSE;
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
//4 1.5 BT case: Disable CFO tracking
if(pDM_Odm->bBtEnabled)
{
pCfoTrack->bAdjust = FALSE;
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable CFO tracking for BT!!\n"));
}
//4 1.6 Big jump
if(pCfoTrack->bAdjust)
{
if(CFO_ave > CFO_TH_XTAL_LOW)
Adjust_Xtal = Adjust_Xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2);
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
Adjust_Xtal = Adjust_Xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap offset = %d\n", Adjust_Xtal));
}
#endif
//4 1.7 Adjust Crystal Cap.
if(pCfoTrack->bAdjust)
{
if(CFO_ave > CFO_TH_XTAL_LOW)
CrystalCap = CrystalCap + Adjust_Xtal;
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
CrystalCap = CrystalCap - Adjust_Xtal;
if(CrystalCap > 0x3f)
CrystalCap = 0x3f;
else if (CrystalCap < 0)
CrystalCap = 0;
odm_SetCrystalCap(pDM_Odm, (u1Byte)CrystalCap);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
pCfoTrack->CrystalCap, pCfoTrack->DefXCap));
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
return;
//3 2. Dynamic ATC switch
if(CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC)
{
odm_SetATCStatus(pDM_Odm, FALSE);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable ATC!!\n"));
}
else
{
odm_SetATCStatus(pDM_Odm, TRUE);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Enable ATC!!\n"));
}
#endif
}
}
VOID
ODM_ParsingCFO(
IN PVOID pDM_VOID,
IN PVOID pPktinfo_VOID,
IN s1Byte* pcfotail
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID;
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
u1Byte i;
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
return;
#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && (MP_DRIVER == 1))
if(1)
#elif(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pPktinfo->bPacketMatchBSSID)
#else
if(pPktinfo->StationID != 0)
#endif
{
//3 Update CFO report for path-A & path-B
// Only paht-A and path-B have CFO tail and short CFO
for(i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++)
{
pCfoTrack->CFO_tail[i] = (int)pcfotail[i];
}
//3 Update packet counter
if(pCfoTrack->packetCount == 0xffffffff)
pCfoTrack->packetCount = 0;
else
pCfoTrack->packetCount++;
}
}

66
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_CfoTracking.h
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@ -1,66 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODMCFOTRACK_H__
#define __ODMCFOTRACK_H__
#define CFO_TH_XTAL_HIGH 20 // kHz
#define CFO_TH_XTAL_LOW 10 // kHz
#define CFO_TH_ATC 80 // kHz
typedef struct _CFO_TRACKING_
{
BOOLEAN bATCStatus;
BOOLEAN largeCFOHit;
BOOLEAN bAdjust;
u1Byte CrystalCap;
u1Byte DefXCap;
int CFO_tail[2];
int CFO_ave_pre;
u4Byte packetCount;
u4Byte packetCount_pre;
BOOLEAN bForceXtalCap;
BOOLEAN bReset;
}CFO_TRACKING, *PCFO_TRACKING;
VOID
ODM_CfoTrackingReset(
IN PVOID pDM_VOID
);
VOID
ODM_CfoTrackingInit(
IN PVOID pDM_VOID
);
VOID
ODM_CfoTracking(
IN PVOID pDM_VOID
);
VOID
ODM_ParsingCFO(
IN PVOID pDM_VOID,
IN PVOID pPktinfo_VOID,
IN s1Byte* pcfotail
);
#endif

2591
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_DIG.c
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395
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_DIG.h
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@ -1,395 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODMDIG_H__
#define __ODMDIG_H__
typedef struct _Dynamic_Initial_Gain_Threshold_
{
BOOLEAN bStopDIG;
BOOLEAN bPSDInProgress;
u1Byte Dig_Enable_Flag;
u1Byte Dig_Ext_Port_Stage;
int RssiLowThresh;
int RssiHighThresh;
u4Byte FALowThresh;
u4Byte FAHighThresh;
u1Byte CurSTAConnectState;
u1Byte PreSTAConnectState;
u1Byte CurMultiSTAConnectState;
u1Byte PreIGValue;
u1Byte CurIGValue;
u1Byte BackupIGValue; //MP DIG
u1Byte BT30_CurIGI;
u1Byte IGIBackup;
s1Byte BackoffVal;
s1Byte BackoffVal_range_max;
s1Byte BackoffVal_range_min;
u1Byte rx_gain_range_max;
u1Byte rx_gain_range_min;
u1Byte Rssi_val_min;
u1Byte PreCCK_CCAThres;
u1Byte CurCCK_CCAThres;
u1Byte PreCCKPDState;
u1Byte CurCCKPDState;
u1Byte CCKPDBackup;
u1Byte LargeFAHit;
u1Byte ForbiddenIGI;
u4Byte Recover_cnt;
u1Byte DIG_Dynamic_MIN_0;
u1Byte DIG_Dynamic_MIN_1;
BOOLEAN bMediaConnect_0;
BOOLEAN bMediaConnect_1;
u4Byte AntDiv_RSSI_max;
u4Byte RSSI_max;
u1Byte *pbP2pLinkInProgress;
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
BOOLEAN bTpTarget;
BOOLEAN bNoiseEst;
u4Byte TpTrainTH_min;
u1Byte IGIOffset_A;
u1Byte IGIOffset_B;
#endif
}DIG_T,*pDIG_T;
typedef struct _FALSE_ALARM_STATISTICS{
u4Byte Cnt_Parity_Fail;
u4Byte Cnt_Rate_Illegal;
u4Byte Cnt_Crc8_fail;
u4Byte Cnt_Mcs_fail;
u4Byte Cnt_Ofdm_fail;
u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A
u4Byte Cnt_Cck_fail;
u4Byte Cnt_all;
u4Byte Cnt_Fast_Fsync;
u4Byte Cnt_SB_Search_fail;
u4Byte Cnt_OFDM_CCA;
u4Byte Cnt_CCK_CCA;
u4Byte Cnt_CCA_all;
u4Byte Cnt_BW_USC; //Gary
u4Byte Cnt_BW_LSC; //Gary
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_BACKOFF = 2,
DIG_TYPE_RX_GAIN_MIN = 3,
DIG_TYPE_RX_GAIN_MAX = 4,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
}DM_DIG_OP_E;
typedef enum tag_ODM_PauseDIG_Type {
ODM_PAUSE_DIG = BIT0,
ODM_RESUME_DIG = BIT1
} ODM_Pause_DIG_TYPE;
typedef enum tag_ODM_PauseCCKPD_Type {
ODM_PAUSE_CCKPD = BIT0,
ODM_RESUME_CCKPD = BIT1
} ODM_Pause_CCKPD_TYPE;
/*
typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
{
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_PD_STAGE_MAX = 3,
}DM_CCK_PDTH_E;
typedef enum tag_DIG_EXT_PORT_ALGO_Definition
{
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
}DM_DIG_EXT_PORT_ALG_E;
typedef enum tag_DIG_Connect_Definition
{
DIG_STA_DISCONNECT = 0,
DIG_STA_CONNECT = 1,
DIG_STA_BEFORE_CONNECT = 2,
DIG_MultiSTA_DISCONNECT = 3,
DIG_MultiSTA_CONNECT = 4,
DIG_CONNECT_MAX
}DM_DIG_CONNECT_E;
#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)
#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)
*/
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_FALSEALARM_THRESH_LOW 400
#define DM_FALSEALARM_THRESH_HIGH 1000
#define DM_DIG_MAX_NIC 0x3e
#define DM_DIG_MIN_NIC 0x1e //0x22//0x1c
#define DM_DIG_MAX_OF_MIN_NIC 0x3e
#define DM_DIG_MAX_AP 0x3e
#define DM_DIG_MIN_AP 0x1c
#define DM_DIG_MAX_OF_MIN 0x2A //0x32
#define DM_DIG_MIN_AP_DFS 0x20
#define DM_DIG_MAX_NIC_HP 0x46
#define DM_DIG_MIN_NIC_HP 0x2e
#define DM_DIG_MAX_AP_HP 0x42
#define DM_DIG_MIN_AP_HP 0x30
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#define DM_DIG_MAX_AP_COVERAGR 0x26
#define DM_DIG_MIN_AP_COVERAGE 0x1c
#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22
#define DM_DIG_TP_Target_TH0 500
#define DM_DIG_TP_Target_TH1 1000
#define DM_DIG_TP_Training_Period 10
#endif
//vivi 92c&92d has different definition, 20110504
//this is for 92c
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
#define DM_DIG_FA_TH0 0x80//0x20
#else
#define DM_DIG_FA_TH0 0x200//0x20
#endif
#else
#define DM_DIG_FA_TH0 0x200//0x20
#endif
#define DM_DIG_FA_TH1 0x300
#define DM_DIG_FA_TH2 0x400
//this is for 92d
#define DM_DIG_FA_TH0_92D 0x100
#define DM_DIG_FA_TH1_92D 0x400
#define DM_DIG_FA_TH2_92D 0x600
#define DM_DIG_BACKOFF_MAX 12
#define DM_DIG_BACKOFF_MIN -4
#define DM_DIG_BACKOFF_DEFAULT 10
#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps
#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps
#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps
#define RSSI_OFFSET_DIG 0x05
VOID
ODM_ChangeDynamicInitGainThresh(
IN PVOID pDM_VOID,
IN u4Byte DM_Type,
IN u4Byte DM_Value
);
VOID
odm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
);
VOID
odm_NHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
odm_NHMBBInit(
IN PVOID pDM_VOID
);
VOID
odm_NHMBB(
IN PVOID pDM_VOID
);
VOID
odm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
);
VOID
odm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
odm_SearchPwdBLowerBound(
IN PVOID pDM_VOID,
IN u1Byte IGI_target
);
VOID
odm_AdaptivityInit(
IN PVOID pDM_VOID
);
VOID
odm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
);
VOID
ODM_Write_DIG(
IN PVOID pDM_VOID,
IN u1Byte CurrentIGI
);
VOID
odm_PauseDIG(
IN PVOID pDM_VOID,
IN ODM_Pause_DIG_TYPE PauseType,
IN u1Byte IGIValue
);
VOID
odm_DIGInit(
IN PVOID pDM_VOID
);
VOID
odm_DIG(
IN PVOID pDM_VOID
);
VOID
odm_DIGbyRSSI_LPS(
IN PVOID pDM_VOID
);
VOID
odm_DigForBtHsMode(
IN PVOID pDM_VOID
);
VOID
odm_FalseAlarmCounterStatistics(
IN PVOID pDM_VOID
);
VOID
odm_FAThresholdCheck(
IN PVOID pDM_VOID,
IN BOOLEAN bDFSBand,
IN BOOLEAN bPerformance,
IN u4Byte RxTp,
IN u4Byte TxTp,
OUT u4Byte* dm_FA_thres
);
u1Byte
odm_ForbiddenIGICheck(
IN PVOID pDM_VOID,
IN u1Byte DIG_Dynamic_MIN,
IN u1Byte CurrentIGI
);
VOID
odm_InbandNoiseCalculate (
IN PVOID pDM_VOID
);
BOOLEAN
odm_DigAbort(
IN PVOID pDM_VOID
);
VOID
odm_PauseCCKPacketDetection(
IN PVOID pDM_VOID,
IN ODM_Pause_CCKPD_TYPE PauseType,
IN u1Byte CCKPDThreshold
);
VOID
odm_CCKPacketDetectionThresh(
IN PVOID pDM_VOID
);
VOID
ODM_Write_CCK_CCA_Thres(
IN PVOID pDM_VOID,
IN u1Byte CurCCK_CCAThres
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_DisableEDCCA(
IN PVOID pDM_VOID
);
VOID
odm_DynamicEDCCA(
IN PVOID pDM_VOID
);
VOID
odm_MPT_DIGCallback(
PRT_TIMER pTimer
);
VOID
odm_MPT_DIGWorkItemCallback(
IN PVOID pContext
);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
VOID
odm_MPT_DIGCallback(
IN PVOID pDM_VOID
);
#endif
#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
VOID
ODM_MPT_DIG(
IN PVOID pDM_VOID
);
#endif
#endif

218
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_DynamicBBPowerSaving.c
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@ -1,218 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "odm_precomp.h"
VOID
odm_DynamicBBPowerSavingInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
pDM_PSTable->PreCCAState = CCA_MAX;
pDM_PSTable->CurCCAState = CCA_MAX;
pDM_PSTable->PreRFState = RF_MAX;
pDM_PSTable->CurRFState = RF_MAX;
pDM_PSTable->Rssi_val_min = 0;
pDM_PSTable->initialize = 0;
}
VOID
odm_DynamicBBPowerSaving(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if (pDM_Odm->SupportICType != ODM_RTL8723A)
return;
if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE))
return;
if(!(pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE)))
return;
//1 2.Power Saving for 92C
if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R))
{
odm_1R_CCA(pDM_Odm);
}
// 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable.
// 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns.
//1 3.Power Saving for 88C
else
{
ODM_RF_Saving(pDM_Odm, FALSE);
}
#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
}
VOID
odm_1R_CCA(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
if(pDM_Odm->RSSI_Min!= 0xFF)
{
if(pDM_PSTable->PreCCAState == CCA_2R)
{
if(pDM_Odm->RSSI_Min >= 35)
pDM_PSTable->CurCCAState = CCA_1R;
else
pDM_PSTable->CurCCAState = CCA_2R;
}
else{
if(pDM_Odm->RSSI_Min <= 30)
pDM_PSTable->CurCCAState = CCA_2R;
else
pDM_PSTable->CurCCAState = CCA_1R;
}
}
else{
pDM_PSTable->CurCCAState=CCA_MAX;
}
if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState)
{
if(pDM_PSTable->CurCCAState == CCA_1R)
{
if( pDM_Odm->RFType ==ODM_2T2R )
{
ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x13);
//PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20);
}
else
{
ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x23);
//PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100
}
}
else
{
ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x33);
//PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63);
}
pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
}
}
void
ODM_RF_Saving(
IN PVOID pDM_VOID,
IN u1Byte bForceInNormal
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
u1Byte Rssi_Up_bound = 30 ;
u1Byte Rssi_Low_bound = 25;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
{
Rssi_Up_bound = 50 ;
Rssi_Low_bound = 45;
}
#endif
if(pDM_PSTable->initialize == 0){
pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
//Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord);
pDM_PSTable->initialize = 1;
}
if(!bForceInNormal)
{
if(pDM_Odm->RSSI_Min != 0xFF)
{
if(pDM_PSTable->PreRFState == RF_Normal)
{
if(pDM_Odm->RSSI_Min >= Rssi_Up_bound)
pDM_PSTable->CurRFState = RF_Save;
else
pDM_PSTable->CurRFState = RF_Normal;
}
else{
if(pDM_Odm->RSSI_Min <= Rssi_Low_bound)
pDM_PSTable->CurRFState = RF_Normal;
else
pDM_PSTable->CurRFState = RF_Save;
}
}
else
pDM_PSTable->CurRFState=RF_MAX;
}
else
{
pDM_PSTable->CurRFState = RF_Normal;
}
if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState)
{
if(pDM_PSTable->CurRFState == RF_Save)
{
// <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode.
// Suggested by SD3 Yu-Nan. 2011.01.20.
if(pDM_Odm->SupportICType == ODM_RTL8723A)
{
ODM_SetBBReg(pDM_Odm, 0x874 , BIT5, 0x1); //Reg874[5]=1b'1
}
ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010
ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63
ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
}
else
{
ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874);
ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0);
if(pDM_Odm->SupportICType == ODM_RTL8723A)
{
ODM_SetBBReg(pDM_Odm,0x874 , BIT5, 0x0); //Reg874[5]=1b'0
}
}
pDM_PSTable->PreRFState =pDM_PSTable->CurRFState;
}
#endif
}

884
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_DynamicTxPower.c
View File

@ -1,884 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "odm_precomp.h"
VOID
odm_DynamicTxPowerInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#if DEV_BUS_TYPE==RT_USB_INTERFACE
if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power)
{
odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
pMgntInfo->bDynamicTxPowerEnable = TRUE;
}
else
#else
//so 92c pci do not need dynamic tx power? vivi check it later
if(IS_HARDWARE_TYPE_8192D(Adapter))
pMgntInfo->bDynamicTxPowerEnable = TRUE;
else
pMgntInfo->bDynamicTxPowerEnable = FALSE;
#endif
pHalData->LastDTPLvl = TxHighPwrLevel_Normal;
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
pdmpriv->bDynamicTxPowerEnable = _FALSE;
#if (RTL8192C_SUPPORT==1)
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_INTEL_PROXIM
if((pHalData->BoardType == BOARD_USB_High_PA)||(Adapter->proximity.proxim_support==_TRUE))
#else
if(pHalData->BoardType == BOARD_USB_High_PA)
#endif
{
//odm_SavePowerIndex(Adapter);
odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
pdmpriv->bDynamicTxPowerEnable = _TRUE;
}
else
#else
pdmpriv->bDynamicTxPowerEnable = _FALSE;
#endif
#endif
pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
#endif
}
VOID
odm_DynamicTxPowerSavePowerIndex(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
u1Byte index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
for(index = 0; index< 6; index++)
pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
for(index = 0; index< 6; index++)
pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
#endif
#endif
}
VOID
odm_DynamicTxPowerRestorePowerIndex(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
u1Byte index;
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
for(index = 0; index< 6; index++)
PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]);
#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
struct dm_priv *pdmpriv = &pHalData->dmpriv;
for(index = 0; index< 6; index++)
rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
#endif
#endif
}
VOID
odm_DynamicTxPowerWritePowerIndex(
IN PVOID pDM_VOID,
IN u1Byte Value)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
for(index = 0; index< 6; index++)
//PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value);
ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
}
VOID
odm_DynamicTxPower(
IN PVOID pDM_VOID
)
{
//
// For AP/ADSL use prtl8192cd_priv
// For CE/NIC use PADAPTER
//
//PADAPTER pAdapter = pDM_Odm->Adapter;
// prtl8192cd_priv priv = pDM_Odm->priv;
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
return;
//
// 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
// at the same time. In the stage2/3, we need to prive universal interface and merge all
// HW dynamic mechanism.
//
switch (pDM_Odm->SupportPlatform)
{
case ODM_WIN:
case ODM_CE:
odm_DynamicTxPowerNIC(pDM_Odm);
break;
case ODM_AP:
odm_DynamicTxPowerAP(pDM_Odm);
break;
case ODM_ADSL:
//odm_DIGAP(pDM_Odm);
break;
}
}
VOID
odm_DynamicTxPowerNIC(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
return;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pDM_Odm->SupportICType == ODM_RTL8192C)
{
odm_DynamicTxPower_92C(pDM_Odm);
}
else if(pDM_Odm->SupportICType == ODM_RTL8192D)
{
odm_DynamicTxPower_92D(pDM_Odm);
}
else if (pDM_Odm->SupportICType == ODM_RTL8821)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter);
if (pMgntInfo->RegRspPwr == 1)
{
if(pDM_Odm->RSSI_Min > 60)
{
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); // Resp TXAGC offset = -3dB
}
else if(pDM_Odm->RSSI_Min < 55)
{
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); // Resp TXAGC offset = 0dB
}
}
#endif
}
#endif
}
VOID
odm_DynamicTxPowerAP(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
//#if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1))
prtl8192cd_priv priv = pDM_Odm->priv;
s4Byte i;
s2Byte pwr_thd = TX_POWER_NEAR_FIELD_THRESH_AP;
if(!priv->pshare->rf_ft_var.tx_pwr_ctrl)
return;
#if ((RTL8812E_SUPPORT==1) || (RTL8881A_SUPPORT==1))
if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8881A))
pwr_thd = TX_POWER_NEAR_FIELD_THRESH_8812;
#endif
#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT)
if(CHIP_VER_92X_SERIES(priv))
{
#ifdef HIGH_POWER_EXT_PA
if(pDM_Odm->ExtPA)
tx_power_control(priv);
#endif
}
#endif
/*
* Check if station is near by to use lower tx power
*/
if ((priv->up_time % 3) == 0 ) {
int disable_pwr_ctrl = ((pDM_Odm->FalseAlmCnt.Cnt_all > 1000 ) || ((pDM_Odm->FalseAlmCnt.Cnt_all > 300 ) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0;
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
if(IS_STA_VALID(pstat) ) {
if(disable_pwr_ctrl)
pstat->hp_level = 0;
else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd))
pstat->hp_level = 1;
else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd-8)))
pstat->hp_level = 0;
}
}
#if defined(CONFIG_WLAN_HAL_8192EE)
if (GET_CHIP_VER(priv) == VERSION_8192E) {
if( !disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff) ) {
if(pDM_Odm->RSSI_Min > pwr_thd)
RRSR_power_control_11n(priv, 1 );
else if(pDM_Odm->RSSI_Min < (pwr_thd-8))
RRSR_power_control_11n(priv, 0 );
} else {
RRSR_power_control_11n(priv, 0 );
}
}
#endif
}
//#endif
#endif
}
VOID
odm_DynamicTxPower_92C(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
s4Byte UndecoratedSmoothedPWDB;
// 2012/01/12 MH According to Luke's suggestion, only high power will support the feature.
if (pDM_Odm->ExtPA == FALSE)
return;
// STA not connected and AP not connected
if((!pMgntInfo->bMediaConnect) &&
(pHalData->EntryMinUndecoratedSmoothedPWDB == 0))
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any \n"));
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//the LastDTPlvl should reset when disconnect,
//otherwise the tx power level wouldn't change when disconnect and connect again.
// Maddest 20091220.
pHalData->LastDTPLvl=TxHighPwrLevel_Normal;
return;
}
#if (INTEL_PROXIMITY_SUPPORT == 1)
// Intel set fixed tx power
if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)
{
switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){
case 1:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_100\n"));
break;
case 2:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_70;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_70\n"));
break;
case 3:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_50;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_50\n"));
break;
case 4:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_35;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_35\n"));
break;
case 5:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_15;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_15\n"));
break;
default:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_100\n"));
break;
}
}
else
#endif
{
if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) ||
(pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) ||
pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
}
else
{
if(pMgntInfo->bMediaConnect) // Default port
{
if(ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter))
{
UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
}
else // associated entry pwdb
{
UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
}
}
}
if( pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl )
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192C() Channel = %d \n" , pHalData->CurrentChannel));
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
if( (pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) &&
(pHalData->LastDTPLvl == TxHighPwrLevel_Level1 || pHalData->LastDTPLvl == TxHighPwrLevel_Level2)) //TxHighPwrLevel_Normal
odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
}
pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#if (RTL8192C_SUPPORT==1)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
int UndecoratedSmoothedPWDB;
if(!pdmpriv->bDynamicTxPowerEnable)
return;
#ifdef CONFIG_INTEL_PROXIM
if(Adapter->proximity.proxim_on== _TRUE){
struct proximity_priv *prox_priv=Adapter->proximity.proximity_priv;
// Intel set fixed tx power
printk("\n %s Adapter->proximity.proxim_on=%d prox_priv->proxim_modeinfo->power_output=%d \n",__FUNCTION__,Adapter->proximity.proxim_on,prox_priv->proxim_modeinfo->power_output);
if(prox_priv!=NULL){
if(prox_priv->proxim_modeinfo->power_output> 0)
{
switch(prox_priv->proxim_modeinfo->power_output)
{
case 1:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
printk("TxHighPwrLevel_100\n");
break;
case 2:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_70;
printk("TxHighPwrLevel_70\n");
break;
case 3:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_50;
printk("TxHighPwrLevel_50\n");
break;
case 4:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_35;
printk("TxHighPwrLevel_35\n");
break;
case 5:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_15;
printk("TxHighPwrLevel_15\n");
break;
default:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
printk("TxHighPwrLevel_100\n");
break;
}
}
}
}
else
#endif
{
// STA not connected and AP not connected
if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
(pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
{
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//the LastDTPlvl should reset when disconnect,
//otherwise the tx power level wouldn't change when disconnect and connect again.
// Maddest 20091220.
pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
return;
}
if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
//todo: AP Mode
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
#else
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
}
else // associated entry pwdb
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
}
}
if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
{
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) // HP1 -> Normal or HP2 -> Normal
odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
}
pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
#endif
#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
}
VOID
odm_DynamicTxPower_92D(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
s4Byte UndecoratedSmoothedPWDB;
PADAPTER BuddyAdapter = Adapter->BuddyAdapter;
BOOLEAN bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(Adapter);
u1Byte HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
// 2012/01/12 MH According to Luke's suggestion, only high power will support the feature.
if (pDM_Odm->ExtPA == FALSE)
return;
// If dynamic high power is disabled.
if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) ||
(pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) ||
pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
return;
}
// STA not connected and AP not connected
if((!pMgntInfo->bMediaConnect) &&
(pHalData->EntryMinUndecoratedSmoothedPWDB == 0))
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any \n"));
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//the LastDTPlvl should reset when disconnect,
//otherwise the tx power level wouldn't change when disconnect and connect again.
// Maddest 20091220.
pHalData->LastDTPLvl=TxHighPwrLevel_Normal;
return;
}
if(pMgntInfo->bMediaConnect) // Default port
{
if(ACTING_AS_AP(Adapter) || pMgntInfo->mIbss)
{
UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
}
else // associated entry pwdb
{
UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
if(IS_HARDWARE_TYPE_8192D(Adapter) && GET_HAL_DATA(Adapter)->CurrentBandType == 1){
if(UndecoratedSmoothedPWDB >= 0x33)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB <0x33) &&
(UndecoratedSmoothedPWDB >= 0x2b) )
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < 0x2b)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
}
}
else
{
if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
}
}
//sherry delete flag 20110517
if(bGetValueFromBuddyAdapter)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n"));
if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() change value \n"));
HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = FALSE;
}
}
if( (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) )
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel));
if(Adapter->DualMacSmartConcurrent == TRUE)
{
if(BuddyAdapter == NULL)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n"));
if(!Adapter->bSlaveOfDMSP)
{
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
}
}
else
{
if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n"));
if(Adapter->bSlaveOfDMSP)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() bslave case \n"));
BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = TRUE;
BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() master case \n"));
if(!bGetValueFromBuddyAdapter)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n"));
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
}
}
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
}
}
}
else
{
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
}
}
pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#if (RTL8192D_SUPPORT==1)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
DM_ODM_T *podmpriv = &pHalData->odmpriv;
int UndecoratedSmoothedPWDB;
#if (RTL8192D_EASY_SMART_CONCURRENT == 1)
PADAPTER BuddyAdapter = Adapter->BuddyAdapter;
BOOLEAN bGetValueFromBuddyAdapter = DualMacGetParameterFromBuddyAdapter(Adapter);
u8 HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
#endif
// If dynamic high power is disabled.
if( (pdmpriv->bDynamicTxPowerEnable != _TRUE) ||
(!(podmpriv->SupportAbility& ODM_BB_DYNAMIC_TXPWR)) )
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
return;
}
// STA not connected and AP not connected
if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
(pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
{
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//the LastDTPlvl should reset when disconnect,
//otherwise the tx power level wouldn't change when disconnect and connect again.
// Maddest 20091220.
pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
return;
}
if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
//todo: AP Mode
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
#else
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
}
else // associated entry pwdb
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
#if TX_POWER_FOR_5G_BAND == 1
if(pHalData->CurrentBandType92D == BAND_ON_5G){
if(UndecoratedSmoothedPWDB >= 0x33)
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB <0x33) &&
(UndecoratedSmoothedPWDB >= 0x2b) )
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < 0x2b)
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
}
}
else
#endif
{
if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
}
}
#if (RTL8192D_EASY_SMART_CONCURRENT == 1)
if(bGetValueFromBuddyAdapter)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n"));
if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n"));
HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _FALSE;
}
}
#endif
if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
{
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel));
#if (RTL8192D_EASY_SMART_CONCURRENT == 1)
if(BuddyAdapter == NULL)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n"));
if(!Adapter->bSlaveOfDMSP)
{
PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
}
}
else
{
if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n"));
if(Adapter->bSlaveOfDMSP)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case \n"));
BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _TRUE;
BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
}
else
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case \n"));
if(!bGetValueFromBuddyAdapter)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n"));
PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
}
}
}
else
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
}
}
#else
PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
#endif
}
pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
#endif
#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
}

87
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_DynamicTxPower.h
View File

@ -1,87 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODMDYNAMICTXPOWER_H__
#define __ODMDYNAMICTXPOWER_H__
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
#define TX_POWER_NEAR_FIELD_THRESH_8812 60
#define TxHighPwrLevel_Normal 0
#define TxHighPwrLevel_Level1 1
#define TxHighPwrLevel_Level2 2
#define TxHighPwrLevel_BT1 3
#define TxHighPwrLevel_BT2 4
#define TxHighPwrLevel_15 5
#define TxHighPwrLevel_35 6
#define TxHighPwrLevel_50 7
#define TxHighPwrLevel_70 8
#define TxHighPwrLevel_100 9
VOID
odm_DynamicTxPowerInit(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerRestorePowerIndex(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerNIC(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_DynamicTxPowerSavePowerIndex(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerWritePowerIndex(
IN PVOID pDM_VOID,
IN u1Byte Value);
VOID
odm_DynamicTxPower_92C(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPower_92D(
IN PVOID pDM_VOID
);
#endif
VOID
odm_DynamicTxPower(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerAP(
IN PVOID pDM_VOID
);
#endif

1915
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_EdcaTurboCheck.c
View File

File diff suppressed because it is too large Load Diff

150
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_EdcaTurboCheck.h
View File

@ -1,150 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODMEDCATURBOCHECK_H__
#define __ODMEDCATURBOCHECK_H__
typedef struct _EDCA_TURBO_
{
BOOLEAN bCurrentTurboEDCA;
BOOLEAN bIsCurRDLState;
#if(DM_ODM_SUPPORT_TYPE == ODM_CE )
u4Byte prv_traffic_idx; // edca turbo
#endif
}EDCA_T,*pEDCA_T;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx)
{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx)
{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP
{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
//============================================================
// EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22
//============================================================
#elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL)
enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG };
static const struct ParaRecord rtl_ap_EDCA[] =
{
//ACM,AIFSN, ECWmin, ECWmax, TXOplimit
{0, 7, 4, 10, 0}, //BK
{0, 3, 4, 6, 0}, //BE
{0, 1, 3, 4, 188}, //VI
{0, 1, 2, 3, 102}, //VO
{0, 1, 3, 4, 94}, //VI_AG
{0, 1, 2, 3, 47}, //VO_AG
};
static const struct ParaRecord rtl_sta_EDCA[] =
{
//ACM,AIFSN, ECWmin, ECWmax, TXOplimit
{0, 7, 4, 10, 0},
{0, 3, 4, 10, 0},
{0, 2, 3, 4, 188},
{0, 2, 2, 3, 102},
{0, 2, 3, 4, 94},
{0, 2, 2, 3, 47},
};
#endif
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#ifdef WIFI_WMM
VOID
ODM_IotEdcaSwitch(
IN PVOID pDM_VOID,
IN unsigned char enable
);
#endif
BOOLEAN
ODM_ChooseIotMainSTA(
IN PVOID pDM_VOID,
IN PSTA_INFO_T pstat
);
#endif
VOID
odm_EdcaTurboCheck(
IN PVOID pDM_VOID
);
VOID
ODM_EdcaTurboInit(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
VOID
odm_EdcaTurboCheckMP(
IN PVOID pDM_VOID
);
//check if edca turbo is disabled
BOOLEAN
odm_IsEdcaTurboDisable(
IN PVOID pDM_VOID
);
//choose edca paramter for special IOT case
VOID
ODM_EdcaParaSelByIot(
IN PVOID pDM_VOID,
OUT u4Byte *EDCA_BE_UL,
OUT u4Byte *EDCA_BE_DL
);
//check if it is UL or DL
VOID
odm_EdcaChooseTrafficIdx(
IN PVOID pDM_VOID,
IN u8Byte cur_tx_bytes,
IN u8Byte cur_rx_bytes,
IN BOOLEAN bBiasOnRx,
OUT BOOLEAN *pbIsCurRDLState
);
#elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
VOID
odm_EdcaTurboCheckCE(
IN PVOID pDM_VOID
);
#else
VOID
odm_IotEngine(
IN PVOID pDM_VOID
);
VOID
odm_EdcaParaInit(
IN PVOID pDM_VOID
);
#endif
#endif

2327
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_HWConfig.c
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237
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_HWConfig.h
View File

@ -1,237 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
/*--------------------------Define -------------------------------------------*/
//#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
#define AGC_DIFF_CONFIG(ic, band) do {\
if (pDM_Odm->bIsMPChip)\
AGC_DIFF_CONFIG_MP(ic,band);\
else\
AGC_DIFF_CONFIG_TC(ic,band);\
} while(0)
//============================================================
// structure and define
//============================================================
typedef struct _Phy_Rx_AGC_Info
{
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte gain:7,trsw:1;
#else
u1Byte trsw:1,gain:7;
#endif
} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
typedef struct _Phy_Status_Rpt_8192cd
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_corr[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_rpt_b_ofdm_cfosho_b;
u1Byte rsvd_1;//ch_corr_msb;
u1Byte noise_power_db_msb;
s1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte noise_power_db_lsb;
u1Byte rsvd_2[3];
u1Byte stream_csi[2];
u1Byte stream_target_csi[2];
s1Byte sig_evm;
u1Byte rsvd_3;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u1Byte sgi_en:1;
u1Byte rxsc:2;
u1Byte idle_long:1;
u1Byte r_ant_train_en:1;
u1Byte ant_sel_b:1;
u1Byte ant_sel:1;
#else // _BIG_ENDIAN_
u1Byte ant_sel:1;
u1Byte ant_sel_b:1;
u1Byte r_ant_train_en:1;
u1Byte idle_long:1;
u1Byte rxsc:2;
u1Byte sgi_en:1;
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
#endif
} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
typedef struct _Phy_Status_Rpt_8812
{
#if 0
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_num[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_bb_pwr_ofdm_cfosho_b;
u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
u1Byte rsvd_1;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte rsvd_2[2];
u1Byte stream_snr[2];
u1Byte stream_csi[2];
u1Byte rsvd_3[2];
s1Byte sig_evm;
u1Byte rsvd_4;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte rsvd_5:2;
#else // _BIG_ENDIAN_
u1Byte rsvd_5:2;
u1Byte antidx_antb:3;
u1Byte antidx_anta:3;
#endif
#endif
//2012.05.24 LukeLee: This structure should take big/little endian in consideration later.....
//DWORD 0
u1Byte gain_trsw[2];
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u2Byte chl_num:10;
u2Byte sub_chnl:4;
u2Byte r_RFMOD:2;
#else // _BIG_ENDIAN_
u2Byte r_RFMOD:2;
u2Byte sub_chnl:4;
u2Byte chl_num:10;
#endif
//DWORD 1
u1Byte pwdb_all;
u1Byte cfosho[4]; // DW 1 byte 1 DW 2 byte 0
//DWORD 2
s1Byte cfotail[4]; // DW 2 byte 1 DW 3 byte 0
//DWORD 3
s1Byte rxevm[2]; // DW 3 byte 1 DW 3 byte 2
s1Byte rxsnr[2]; // DW 3 byte 3 DW 4 byte 0
//DWORD 4
u1Byte PCTS_MSK_RPT[2];
u1Byte pdsnr[2]; // DW 4 byte 3 DW 5 Byte 0
//DWORD 5
u1Byte csi_current[2];
u1Byte rx_gain_c;
//DWORD 6
u1Byte rx_gain_d;
s1Byte sigevm;
u1Byte resvd_0;
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte resvd_1:2;
} PHY_STATUS_RPT_8812_T,*PPHY_STATUS_RPT_8812_T;
VOID
odm_Init_RSSIForDM(
IN OUT PDM_ODM_T pDM_Odm
);
VOID
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
);
VOID
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN BOOLEAN bPacketMatchBSSID,
IN BOOLEAN bPacketToSelf,
IN BOOLEAN bPacketBeacon
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP))
HAL_STATUS
ODM_ConfigRFWithTxPwrTrackHeaderFile(
IN PDM_ODM_T pDM_Odm
);
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_Config_Type ConfigType,
IN ODM_RF_RADIO_PATH_E eRFPath
);
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
);
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
);
HAL_STATUS
ODM_ConfigFWWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_FW_Config_Type ConfigType,
OUT u1Byte *pFirmware,
OUT u4Byte *pSize
);
u4Byte
ODM_GetHWImgVersion(
IN PDM_ODM_T pDM_Odm
);
s4Byte
odm_SignalScaleMapping(
IN OUT PDM_ODM_T pDM_Odm,
IN s4Byte CurrSig
);
#endif
#endif

197
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_NoiseMonitor.c
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@ -1,197 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
//#include "Mp_Precomp.h"
#include "odm_precomp.h"
//=================================================
// This function is for inband noise test utility only
// To obtain the inband noise level(dbm), do the following.
// 1. disable DIG and Power Saving
// 2. Set initial gain = 0x1a
// 3. Stop updating idle time pwer report (for driver read)
// - 0x80c[25]
//
//=================================================
#define Valid_Min -35
#define Valid_Max 10
#define ValidCnt 5
s2Byte odm_InbandNoise_Monitor_NSeries(PDM_ODM_T pDM_Odm,u8 bPauseDIG,u8 IGIValue,u32 max_time)
{
u4Byte tmp4b;
u1Byte max_rf_path=0,rf_path;
u1Byte reg_c50, reg_c58,valid_done=0;
struct noise_level noise_data;
u32 start = 0, func_start=0, func_end = 0;
func_start = ODM_GetCurrentTime(pDM_Odm);
pDM_Odm->noise_level.noise_all = 0;
if((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R))
max_rf_path = 2;
else
max_rf_path = 1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() ==> \n"));
ODM_Memory_Set(pDM_Odm,&noise_data,0,sizeof(struct noise_level));
//
// Step 1. Disable DIG && Set initial gain.
//
if(bPauseDIG)
{
odm_PauseDIG(pDM_Odm,ODM_PAUSE_DIG,IGIValue);
}
//
// Step 2. Disable all power save for read registers
//
//dcmd_DebugControlPowerSave(pAdapter, PSDisable);
//
// Step 3. Get noise power level
//
start = ODM_GetCurrentTime(pDM_Odm);
while(1)
{
//Stop updating idle time pwer report (for driver read)
ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 1);
//Read Noise Floor Report
tmp4b = ODM_GetBBReg(pDM_Odm, 0x8f8,bMaskDWord );
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b));
//ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, TestInitialGain);
//if(max_rf_path == 2)
// ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, TestInitialGain);
//update idle time pwer report per 5us
ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 0);
noise_data.value[ODM_RF_PATH_A] = (u1Byte)(tmp4b&0xff);
noise_data.value[ODM_RF_PATH_B] = (u1Byte)((tmp4b&0xff00)>>8);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B]));
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
{
noise_data.sval[rf_path] = (s1Byte)noise_data.value[rf_path];
noise_data.sval[rf_path] /= 2;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("sval_a = %d, sval_b = %d\n",
noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B]));
//ODM_delay_ms(10);
//ODM_sleep_ms(10);
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
{
if( (noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min))
{
noise_data.valid_cnt[rf_path]++;
noise_data.sum[rf_path] += noise_data.sval[rf_path];
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("RF_Path:%d Valid sval = %d\n", rf_path,noise_data.sval[rf_path]));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Sum of sval = %d, \n", noise_data.sum[rf_path]));
if(noise_data.valid_cnt[rf_path] == ValidCnt)
{
valid_done++;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("After divided, RF_Path:%d ,sum = %d \n", rf_path,noise_data.sum[rf_path]));
}
}
}
//printk("####### valid_done:%d #############\n",valid_done);
if ((valid_done==max_rf_path) || (ODM_GetProgressingTime(pDM_Odm,start) > max_time))
{
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
{
//printk("%s PATH_%d - sum = %d, valid_cnt = %d \n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]);
if(noise_data.valid_cnt[rf_path])
noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path];
else
noise_data.sum[rf_path] = 0;
}
break;
}
}
reg_c50 = (s4Byte)ODM_GetBBReg(pDM_Odm,rOFDM0_XAAGCCore1,bMaskByte0);
reg_c50 &= ~BIT7;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XAAGCCore1, reg_c50, reg_c50));
pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = -110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A];
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A];
if(max_rf_path == 2){
reg_c58 = (s4Byte)ODM_GetBBReg(pDM_Odm,rOFDM0_XBAGCCore1,bMaskByte0);
reg_c58 &= ~BIT7;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XBAGCCore1, reg_c58, reg_c58));
pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = -110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B];
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B];
}
pDM_Odm->noise_level.noise_all /= max_rf_path;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("noise_a = %d, noise_b = %d\n",
pDM_Odm->noise_level.noise[ODM_RF_PATH_A],
pDM_Odm->noise_level.noise[ODM_RF_PATH_B]));
//
// Step 4. Recover the Dig
//
if(bPauseDIG)
{
odm_PauseDIG(pDM_Odm,ODM_RESUME_DIG,IGIValue);
}
func_end = ODM_GetProgressingTime(pDM_Odm,func_start) ;
//printk("%s noise_a = %d, noise_b = %d noise_all:%d (%d ms)\n",__FUNCTION__,
// pDM_Odm->noise_level.noise[ODM_RF_PATH_A],
// pDM_Odm->noise_level.noise[ODM_RF_PATH_B],
// pDM_Odm->noise_level.noise_all,func_end);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() <== \n"));
return pDM_Odm->noise_level.noise_all;
}
s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES )
{
//odm_InbandNoise_Monitor_JaguarSeries(pDM_Odm,bPauseDIG,IGIValue,max_time);
return 0;
}
else
{
return odm_InbandNoise_Monitor_NSeries(pDM_VOID,bPauseDIG,IGIValue,max_time);
}
}

1580
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_PathDiv.c
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File diff suppressed because it is too large Load Diff

196
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_PathDiv.h
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@ -1,196 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODMPATHDIV_H__
#define __ODMPATHDIV_H__
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_PathDiversityInit(
IN PVOID pDM_VOID
);
VOID
odm_PathDiversity(
IN PVOID pDM_VOID
);
#endif //(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
//#define PATHDIV_ENABLE 1
#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi
#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C
typedef struct _PathDiv_Parameter_define_
{
u4Byte org_5g_RegE30;
u4Byte org_5g_RegC14;
u4Byte org_5g_RegCA0;
u4Byte swt_5g_RegE30;
u4Byte swt_5g_RegC14;
u4Byte swt_5g_RegCA0;
//for 2G IQK information
u4Byte org_2g_RegC80;
u4Byte org_2g_RegC4C;
u4Byte org_2g_RegC94;
u4Byte org_2g_RegC14;
u4Byte org_2g_RegCA0;
u4Byte swt_2g_RegC80;
u4Byte swt_2g_RegC4C;
u4Byte swt_2g_RegC94;
u4Byte swt_2g_RegC14;
u4Byte swt_2g_RegCA0;
}PATHDIV_PARA,*pPATHDIV_PARA;
VOID
odm_PathDiversityInit_92C(
IN PADAPTER Adapter
);
VOID
odm_2TPathDiversityInit_92C(
IN PADAPTER Adapter
);
VOID
odm_1TPathDiversityInit_92C(
IN PADAPTER Adapter
);
BOOLEAN
odm_IsConnected_92C(
IN PADAPTER Adapter
);
BOOLEAN
ODM_PathDiversityBeforeLink92C(
//IN PADAPTER Adapter
IN PDM_ODM_T pDM_Odm
);
VOID
odm_PathDiversityAfterLink_92C(
IN PADAPTER Adapter
);
VOID
odm_SetRespPath_92C(
IN PADAPTER Adapter,
IN u1Byte DefaultRespPath
);
VOID
odm_OFDMTXPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_CCKTXPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_ResetPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_CCKTXPathDiversityCallback(
PRT_TIMER pTimer
);
VOID
odm_CCKTXPathDiversityWorkItemCallback(
IN PVOID pContext
);
VOID
odm_PathDivChkAntSwitchCallback(
PRT_TIMER pTimer
);
VOID
odm_PathDivChkAntSwitchWorkitemCallback(
IN PVOID pContext
);
VOID
odm_PathDivChkAntSwitch(
PDM_ODM_T pDM_Odm
);
VOID
ODM_CCKPathDiversityChkPerPktRssi(
PADAPTER Adapter,
BOOLEAN bIsDefPort,
BOOLEAN bMatchBSSID,
PRT_WLAN_STA pEntry,
PRT_RFD pRfd,
pu1Byte pDesc
);
VOID
ODM_PathDivChkPerPktRssi(
PADAPTER Adapter,
BOOLEAN bIsDefPort,
BOOLEAN bMatchBSSID,
PRT_WLAN_STA pEntry,
PRT_RFD pRfd
);
VOID
ODM_PathDivRestAfterLink(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_FillTXPathInTXDESC(
IN PADAPTER Adapter,
IN PRT_TCB pTcb,
IN pu1Byte pDesc
);
VOID
odm_PathDivInit_92D(
IN PDM_ODM_T pDM_Odm
);
u1Byte
odm_SwAntDivSelectScanChnl(
IN PADAPTER Adapter
);
VOID
odm_SwAntDivConstructScanChnl(
IN PADAPTER Adapter,
IN u1Byte ScanChnl
);
#endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
#endif //#ifndef __ODMPATHDIV_H__

75
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_RegDefine11AC.h
View File

@ -1,75 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11AC_H__
#define __ODM_REGDEFINE11AC_H__
//2 RF REG LIST
//2 BB REG LIST
//PAGE 8
#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
#define ODM_REG_BB_RX_PATH_11AC 0x808
#define ODM_REG_BB_ATC_11AC 0x860
#define ODM_REG_DBG_RPT_11AC 0x8fc
//PAGE 9
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
#define ODM_REG_NHM_TIMER_11AC 0x990
#define ODM_REG_NHM_TH9_TH10_11AC 0x994
#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
#define ODM_REG_NHM_TH8_11AC 0x9a0
#define ODM_REG_NHM_9E8_11AC 0x9e8
//PAGE A
#define ODM_REG_CCK_CCA_11AC 0xA0A
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
#define ODM_REG_CCK_FA_11AC 0xA5C
//PAGE B
#define ODM_REG_RST_RPT_11AC 0xB58
//PAGE C
#define ODM_REG_TRMUX_11AC 0xC08
#define ODM_REG_IGI_A_11AC 0xC50
//PAGE E
#define ODM_REG_IGI_B_11AC 0xE50
//PAGE F
#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
#define ODM_REG_OFDM_FA_11AC 0xF48
#define ODM_REG_RPT_11AC 0xfa0
#define ODM_REG_NHM_CNT_11AC 0xfa8
//PAGE 18
#define ODM_REG_IGI_C_11AC 0x1850
//PAGE 1A
#define ODM_REG_IGI_D_11AC 0x1A50
//2 MAC REG LIST
#define ODM_REG_RESP_TX_11AC 0x6D8
//DIG Related
#define ODM_BIT_IGI_11AC 0xFFFFFFFF
#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16
#define ODM_BIT_BB_RX_PATH_11AC 0xF
#define ODM_BIT_BB_ATC_11AC BIT14
#endif

180
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_RegDefine11N.h
View File

@ -1,180 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__
//2 RF REG LIST
#define ODM_REG_RF_MODE_11N 0x00
#define ODM_REG_RF_0B_11N 0x0B
#define ODM_REG_CHNBW_11N 0x18
#define ODM_REG_T_METER_11N 0x24
#define ODM_REG_RF_25_11N 0x25
#define ODM_REG_RF_26_11N 0x26
#define ODM_REG_RF_27_11N 0x27
#define ODM_REG_RF_2B_11N 0x2B
#define ODM_REG_RF_2C_11N 0x2C
#define ODM_REG_RXRF_A3_11N 0x3C
#define ODM_REG_T_METER_92D_11N 0x42
#define ODM_REG_T_METER_88E_11N 0x42
//2 BB REG LIST
//PAGE 8
#define ODM_REG_BB_CTRL_11N 0x800
#define ODM_REG_RF_PIN_11N 0x804
#define ODM_REG_PSD_CTRL_11N 0x808
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
#define ODM_REG_BB_PWR_SAV5_11N 0x818
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
#define ODM_REG_RX_DEFUALT_A_11N 0x858
#define ODM_REG_RX_DEFUALT_B_11N 0x85A
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
#define ODM_REG_ANTSEL_CTRL_11N 0x860
#define ODM_REG_RX_ANT_CTRL_11N 0x864
#define ODM_REG_PIN_CTRL_11N 0x870
#define ODM_REG_BB_PWR_SAV1_11N 0x874
#define ODM_REG_ANTSEL_PATH_11N 0x878
#define ODM_REG_BB_3WIRE_11N 0x88C
#define ODM_REG_SC_CNT_11N 0x8C4
#define ODM_REG_PSD_DATA_11N 0x8B4
#define ODM_REG_PSD_DATA_11N 0x8B4
#define ODM_REG_NHM_TIMER_11N 0x894
#define ODM_REG_NHM_TH9_TH10_11N 0x890
#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
#define ODM_REG_NHM_CNT_11N 0x8d8
//PAGE 9
#define ODM_REG_DBG_RPT_11N 0x908
#define ODM_REG_ANT_MAPPING1_11N 0x914
#define ODM_REG_ANT_MAPPING2_11N 0x918
//PAGE A
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
#define ODM_REG_CCK_FA_RST_11N 0xA2C
#define ODM_REG_CCK_FA_MSB_11N 0xA58
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
//PAGE B
#define ODM_REG_LNA_SWITCH_11N 0xB2C
#define ODM_REG_PATH_SWITCH_11N 0xB30
#define ODM_REG_RSSI_CTRL_11N 0xB38
#define ODM_REG_CONFIG_ANTA_11N 0xB68
#define ODM_REG_RSSI_BT_11N 0xB9C
//PAGE C
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_BB_RX_PATH_11N 0xC04
#define ODM_REG_TRMUX_11N 0xC08
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define ODM_REG_IGI_A_11N 0xC50
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
#define ODM_REG_IGI_B_11N 0xC58
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
#define ODM_REG_RX_OFF_11N 0xC7C
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
//PAGE D
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_BB_ATC_11N 0xD2C
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
#define ODM_REG_RPT_11N 0xDF4
//PAGE E
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define ODM_REG_FPGA0_IQK_11N 0xE28
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
#define ODM_REG_TXIQK_PI_A_11N 0xE38
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
#define ODM_REG_TXIQK_11N 0xE40
#define ODM_REG_RXIQK_11N 0xE44
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
#define ODM_REG_BLUETOOTH_11N 0xE6C
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
#define ODM_REG_TX_CCK_RFON_11N 0xE74
#define ODM_REG_TX_CCK_BBON_11N 0xE78
#define ODM_REG_OFDM_RFON_11N 0xE7C
#define ODM_REG_OFDM_BBON_11N 0xE80
#define ODM_REG_TX2RX_11N 0xE84
#define ODM_REG_TX2TX_11N 0xE88
#define ODM_REG_RX_CCK_11N 0xE8C
#define ODM_REG_RX_OFDM_11N 0xED0
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
#define ODM_REG_RX2RX_11N 0xED8
#define ODM_REG_STANDBY_11N 0xEDC
#define ODM_REG_SLEEP_11N 0xEE0
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
#define ODM_REG_IGI_C_11N 0xF84
#define ODM_REG_IGI_D_11N 0xF88
//2 MAC REG LIST
#define ODM_REG_BB_RST_11N 0x02
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_EARLY_MODE_11N 0x4D0
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
#define ODM_REG_EDCA_VO_11N 0x500
#define ODM_REG_EDCA_VI_11N 0x504
#define ODM_REG_EDCA_BE_11N 0x508
#define ODM_REG_EDCA_BK_11N 0x50C
#define ODM_REG_TXPAUSE_11N 0x522
#define ODM_REG_RESP_TX_11N 0x6D8
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
//DIG Related
#define ODM_BIT_IGI_11N 0x0000007F
#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9
#define ODM_BIT_BB_RX_PATH_11N 0xF
#define ODM_BIT_BB_ATC_11N BIT11
#endif

629
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_debug.c
View File

@ -1,629 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "odm_precomp.h"
VOID
ODM_InitDebugSetting(
IN PDM_ODM_T pDM_Odm
)
{
pDM_Odm->DebugLevel = ODM_DBG_LOUD;
pDM_Odm->DebugComponents =
\
#if DBG
//BB Functions
// ODM_COMP_DIG |
// ODM_COMP_RA_MASK |
// ODM_COMP_DYNAMIC_TXPWR |
// ODM_COMP_FA_CNT |
// ODM_COMP_RSSI_MONITOR |
// ODM_COMP_CCK_PD |
// ODM_COMP_ANT_DIV |
// ODM_COMP_PWR_SAVE |
// ODM_COMP_PWR_TRAIN |
// ODM_COMP_RATE_ADAPTIVE |
// ODM_COMP_PATH_DIV |
// ODM_COMP_DYNAMIC_PRICCA |
// ODM_COMP_RXHP |
// ODM_COMP_MP |
// ODM_COMP_CFO_TRACKING |
//MAC Functions
// ODM_COMP_EDCA_TURBO |
// ODM_COMP_EARLY_MODE |
//RF Functions
// ODM_COMP_TX_PWR_TRACK |
// ODM_COMP_RX_GAIN_TRACK |
// ODM_COMP_CALIBRATION |
//Common
// ODM_COMP_COMMON |
// ODM_COMP_INIT |
// ODM_COMP_PSD |
#endif
0;
}
#if 0
/*------------------Declare variable-----------------------
// Define debug flag array for common debug print macro. */
u4Byte ODM_DBGP_Type[ODM_DBGP_TYPE_MAX];
/* Define debug print header for every service module. */
ODM_DBGP_HEAD_T ODM_DBGP_Head;
/*-----------------------------------------------------------------------------
* Function: DBGP_Flag_Init
*
* Overview: Refresh all debug print control flag content to zero.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 10/20/2006 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void ODM_DBGP_Flag_Init(void)
{
u1Byte i;
for (i = 0; i < ODM_DBGP_TYPE_MAX; i++)
{
ODM_DBGP_Type[i] = 0;
}
#ifndef ADSL_AP_BUILD_WORKAROUND
#if DBG
// 2010/06/02 MH Free build driver can not out any debug message!!!
// Init Debug flag enable condition
ODM_DBGP_Type[FINIT] = \
// INIT_EEPROM |
// INIT_TxPower |
// INIT_IQK |
// INIT_RF |
0;
ODM_DBGP_Type[FDM] = \
// WA_IOT |
// DM_PWDB |
// DM_Monitor |
// DM_DIG |
// DM_EDCA_Turbo |
// DM_BT30 |
0;
ODM_DBGP_Type[FIOCTL] = \
// IOCTL_IRP |
// IOCTL_IRP_DETAIL |
// IOCTL_IRP_STATISTICS |
// IOCTL_IRP_HANDLE |
// IOCTL_BT_HCICMD |
// IOCTL_BT_HCICMD_DETAIL |
// IOCTL_BT_HCICMD_EXT |
// IOCTL_BT_EVENT |
// IOCTL_BT_EVENT_DETAIL |
// IOCTL_BT_EVENT_PERIODICAL |
// IOCTL_BT_TX_ACLDATA |
// IOCTL_BT_TX_ACLDATA_DETAIL |
// IOCTL_BT_RX_ACLDATA |
// IOCTL_BT_RX_ACLDATA_DETAIL |
// IOCTL_BT_TP |
// IOCTL_STATE |
// IOCTL_BT_LOGO |
// IOCTL_CALLBACK_FUN |
// IOCTL_PARSE_BT_PKT |
0;
ODM_DBGP_Type[FBT] = \
// BT_TRACE |
0;
ODM_DBGP_Type[FEEPROM] = \
// EEPROM_W |
// EFUSE_PG |
// EFUSE_READ_ALL |
// EFUSE_ANALYSIS |
// EFUSE_PG_DETAIL |
0;
ODM_DBGP_Type[FDBG_CTRL] = \
// DBG_CTRL_TRACE |
// DBG_CTRL_INBAND_NOISE |
0;
// 2011/07/20 MH Add for short cut
ODM_DBGP_Type[FSHORT_CUT] = \
// SHCUT_TX |
// SHCUT_RX |
0;
#endif
#endif
/* Define debug header of every service module. */
//ODM_DBGP_Head.pMANS = "\n\r[MANS] ";
//ODM_DBGP_Head.pRTOS = "\n\r[RTOS] ";
//ODM_DBGP_Head.pALM = "\n\r[ALM] ";
//ODM_DBGP_Head.pPEM = "\n\r[PEM] ";
//ODM_DBGP_Head.pCMPK = "\n\r[CMPK] ";
//ODM_DBGP_Head.pRAPD = "\n\r[RAPD] ";
//ODM_DBGP_Head.pTXPB = "\n\r[TXPB] ";
//ODM_DBGP_Head.pQUMG = "\n\r[QUMG] ";
} /* DBGP_Flag_Init */
#endif
#if 0
u4Byte GlobalDebugLevel = DBG_LOUD;
//
// 2009/06/22 MH Allow Fre build to print none debug info at init time.
//
#if DBG
u8Byte GlobalDebugComponents = \
// COMP_TRACE |
// COMP_DBG |
// COMP_INIT |
// COMP_OID_QUERY |
// COMP_OID_SET |
// COMP_RECV |
// COMP_SEND |
// COMP_IO |
// COMP_POWER |
// COMP_MLME |
// COMP_SCAN |
// COMP_SYSTEM |
// COMP_SEC |
// COMP_AP |
// COMP_TURBO |
// COMP_QOS |
// COMP_AUTHENTICATOR |
// COMP_BEACON |
// COMP_ANTENNA |
// COMP_RATE |
// COMP_EVENTS |
// COMP_FPGA |
// COMP_RM |
// COMP_MP |
// COMP_RXDESC |
// COMP_CKIP |
// COMP_DIG |
// COMP_TXAGC |
// COMP_HIPWR |
// COMP_HALDM |
// COMP_RSNA |
// COMP_INDIC |
// COMP_LED |
// COMP_RF |
// COMP_DUALMACSWITCH |
// COMP_EASY_CONCURRENT |
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
// COMP_HT |
// COMP_POWER_TRACKING |
// COMP_RX_REORDER |
// COMP_AMSDU |
// COMP_WPS |
// COMP_RATR |
// COMP_RESET |
// COMP_CMD |
// COMP_EFUSE |
// COMP_MESH_INTERWORKING |
// COMP_CCX |
// COMP_IOCTL |
// COMP_GP |
// COMP_TXAGG |
// COMP_BB_POWERSAVING |
// COMP_SWAS |
// COMP_P2P |
// COMP_MUX |
// COMP_FUNC |
// COMP_TDLS |
// COMP_OMNIPEEK |
// COMP_PSD |
0;
#else
u8Byte GlobalDebugComponents = 0;
#endif
#if (RT_PLATFORM==PLATFORM_LINUX)
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
EXPORT_SYMBOL(GlobalDebugComponents);
EXPORT_SYMBOL(GlobalDebugLevel);
#endif
#endif
/*------------------Declare variable-----------------------
// Define debug flag array for common debug print macro. */
u4Byte DBGP_Type[DBGP_TYPE_MAX];
/* Define debug print header for every service module. */
DBGP_HEAD_T DBGP_Head;
/*-----------------------------------------------------------------------------
* Function: DBGP_Flag_Init
*
* Overview: Refresh all debug print control flag content to zero.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 10/20/2006 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void DBGP_Flag_Init(void)
{
u1Byte i;
for (i = 0; i < DBGP_TYPE_MAX; i++)
{
DBGP_Type[i] = 0;
}
#if DBG
// 2010/06/02 MH Free build driver can not out any debug message!!!
// Init Debug flag enable condition
DBGP_Type[FINIT] = \
// INIT_EEPROM |
// INIT_TxPower |
// INIT_IQK |
// INIT_RF |
0;
DBGP_Type[FDM] = \
// WA_IOT |
// DM_PWDB |
// DM_Monitor |
// DM_DIG |
// DM_EDCA_Turbo |
// DM_BT30 |
0;
DBGP_Type[FIOCTL] = \
// IOCTL_IRP |
// IOCTL_IRP_DETAIL |
// IOCTL_IRP_STATISTICS |
// IOCTL_IRP_HANDLE |
// IOCTL_BT_HCICMD |
// IOCTL_BT_HCICMD_DETAIL |
// IOCTL_BT_HCICMD_EXT |
// IOCTL_BT_EVENT |
// IOCTL_BT_EVENT_DETAIL |
// IOCTL_BT_EVENT_PERIODICAL |
// IOCTL_BT_TX_ACLDATA |
// IOCTL_BT_TX_ACLDATA_DETAIL |
// IOCTL_BT_RX_ACLDATA |
// IOCTL_BT_RX_ACLDATA_DETAIL |
// IOCTL_BT_TP |
// IOCTL_STATE |
// IOCTL_BT_LOGO |
// IOCTL_CALLBACK_FUN |
// IOCTL_PARSE_BT_PKT |
0;
DBGP_Type[FBT] = \
// BT_TRACE |
0;
DBGP_Type[FEEPROM] = \
// EEPROM_W |
// EFUSE_PG |
// EFUSE_READ_ALL |
// EFUSE_ANALYSIS |
// EFUSE_PG_DETAIL |
0;
DBGP_Type[FDBG_CTRL] = \
// DBG_CTRL_TRACE |
// DBG_CTRL_INBAND_NOISE |
0;
// 2011/07/20 MH Add for short cut
DBGP_Type[FSHORT_CUT] = \
// SHCUT_TX |
// SHCUT_RX |
0;
#endif
/* Define debug header of every service module. */
DBGP_Head.pMANS = "\n\r[MANS] ";
DBGP_Head.pRTOS = "\n\r[RTOS] ";
DBGP_Head.pALM = "\n\r[ALM] ";
DBGP_Head.pPEM = "\n\r[PEM] ";
DBGP_Head.pCMPK = "\n\r[CMPK] ";
DBGP_Head.pRAPD = "\n\r[RAPD] ";
DBGP_Head.pTXPB = "\n\r[TXPB] ";
DBGP_Head.pQUMG = "\n\r[QUMG] ";
} /* DBGP_Flag_Init */
/*-----------------------------------------------------------------------------
* Function: DBG_PrintAllFlag
*
* Overview: Print All debug flag
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 12/10/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void DBG_PrintAllFlag(void)
{
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 0 FQoS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 1 FTX\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 2 FRX\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 3 FSEC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 4 FMGNT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 5 FMLME\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 6 FRESOURCE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 7 FBEACON\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 8 FISR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 9 FPHY\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 11 FMP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 12 FPWR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 13 FDM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 14 FDBG_CTRL\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 15 FC2H\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 16 FBT\n"));
} // DBG_PrintAllFlag
extern void DBG_PrintAllComp(void)
{
u1Byte i;
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents Definition\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT0 COMP_TRACE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT1 COMP_DBG\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT2 COMP_INIT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT3 COMP_OID_QUERY\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT4 COMP_OID_SET\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT5 COMP_RECV\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT6 COMP_SEND\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT7 COMP_IO\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT8 COMP_POWER\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT9 COMP_MLME\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT10 COMP_SCAN\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT11 COMP_SYSTEM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT12 COMP_SEC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT13 COMP_AP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT14 COMP_TURBO\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT15 COMP_QOS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT16 COMP_AUTHENTICATOR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT17 COMP_BEACON\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT18 COMP_BEACON\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT19 COMP_RATE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT20 COMP_EVENTS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT21 COMP_FPGA\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT22 COMP_RM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT23 COMP_MP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT24 COMP_RXDESC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT25 COMP_CKIP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT26 COMP_DIG\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT27 COMP_TXAGC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT28 COMP_HIPWR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT29 COMP_HALDM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT30 COMP_RSNA\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT31 COMP_INDIC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT32 COMP_LED\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT33 COMP_RF\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT34 COMP_HT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT35 COMP_POWER_TRACKING\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT36 COMP_POWER_TRACKING\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT37 COMP_AMSDU\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT38 COMP_WPS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT39 COMP_RATR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT40 COMP_RESET\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT41 COMP_CMD\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT42 COMP_EFUSE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_MESH_INTERWORKING\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_CCX\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents = %"i64fmt"x\n", GlobalDebugComponents));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("Enable DBG COMP ="));
for (i = 0; i < 64; i++)
{
if (GlobalDebugComponents & ((u8Byte)0x1 << i) )
{
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT%02d |\n", i));
}
}
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("\n"));
} // DBG_PrintAllComp
/*-----------------------------------------------------------------------------
* Function: DBG_PrintFlagEvent
*
* Overview: Print dedicated debug flag event
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 12/10/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void DBG_PrintFlagEvent(u1Byte DbgFlag)
{
switch(DbgFlag)
{
case FQoS:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 QoS_INIT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 QoS_VISTA\n"));
break;
case FTX:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 TX_DESC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 TX_DESC_TID\n"));
break;
case FRX:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 RX_DATA\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 RX_PHY_STS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 RX_PHY_SS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 RX_PHY_SQ\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 RX_PHY_ASTS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 RX_ERR_LEN\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 RX_DEFRAG\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 RX_ERR_RATE\n"));
break;
case FSEC:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n"));
break;
case FMGNT:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n"));
break;
case FMLME:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MEDIA_STS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 LINK_STS\n"));
break;
case FRESOURCE:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 OS_CHK\n"));
break;
case FBEACON:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BCN_SHOW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BCN_PEER\n"));
break;
case FISR:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 ISR_CHK\n"));
break;
case FPHY:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 PHY_BBR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 PHY_BBW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PHY_RFR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PHY_RFW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PHY_MACR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 PHY_MACW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 PHY_ALLR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 PHY_ALLW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 8 PHY_TXPWR\n"));
break;
case FMP:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MP_RX\n"));
break;
case FEEPROM:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 EEPROM_W\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 EFUSE_PG\n"));
break;
case FPWR:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 LPS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 IPS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PWRSW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PWRHW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PWRHAL\n"));
break;
case FDM:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 WA_IOT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DM_PWDB\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 DM_Monitor\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 DM_DIG\n"));
break;
case FDBG_CTRL:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 DBG_CTRL_TRACE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DBG_CTRL_INBAND_NOISE\n"));
break;
case FC2H:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 C2H_Summary\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 C2H_PacketData\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 C2H_ContentData\n"));
break;
case FBT:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BT_TRACE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BT_RFPoll\n"));
break;
default:
break;
}
} // DBG_PrintFlagEvent
extern void DBG_DumpMem(const u1Byte DbgComp,
const u1Byte DbgLevel,
pu1Byte pMem,
u2Byte Len)
{
u2Byte i;
for (i=0;i<((Len>>3) + 1);i++)
{
ODM_RT_TRACE(pDM_Odm,DbgComp, DbgLevel, ("%02X %02X %02X %02X %02X %02X %02X %02X\n",
*(pMem+(i*8)), *(pMem+(i*8+1)), *(pMem+(i*8+2)), *(pMem+(i*8+3)),
*(pMem+(i*8+4)), *(pMem+(i*8+5)), *(pMem+(i*8+6)), *(pMem+(i*8+7))));
}
}
#endif

892
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_debug.h
View File

@ -1,892 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE()!
//
#define ODM_DBG_OFF 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define ODM_DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define ODM_DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define ODM_DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define ODM_DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
//BB Functions
#define ODM_COMP_DIG BIT0
#define ODM_COMP_RA_MASK BIT1
#define ODM_COMP_DYNAMIC_TXPWR BIT2
#define ODM_COMP_FA_CNT BIT3
#define ODM_COMP_RSSI_MONITOR BIT4
#define ODM_COMP_CCK_PD BIT5
#define ODM_COMP_ANT_DIV BIT6
#define ODM_COMP_PWR_SAVE BIT7
#define ODM_COMP_PWR_TRAIN BIT8
#define ODM_COMP_RATE_ADAPTIVE BIT9
#define ODM_COMP_PATH_DIV BIT10
#define ODM_COMP_PSD BIT11
#define ODM_COMP_DYNAMIC_PRICCA BIT12
#define ODM_COMP_RXHP BIT13
#define ODM_COMP_MP BIT14
#define ODM_COMP_CFO_TRACKING BIT15
//MAC Functions
#define ODM_COMP_EDCA_TURBO BIT16
#define ODM_COMP_EARLY_MODE BIT17
//RF Functions
#define ODM_COMP_TX_PWR_TRACK BIT24
#define ODM_COMP_RX_GAIN_TRACK BIT25
#define ODM_COMP_CALIBRATION BIT26
//Common Functions
#define ODM_COMP_COMMON BIT30
#define ODM_COMP_INIT BIT31
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define RT_PRINTK DbgPrint
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define DbgPrint printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#define RT_DISP(dbgtype, dbgflag, printstr)
#else
#define DbgPrint panic_printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#endif
#ifndef ASSERT
#define ASSERT(expr)
#endif
#if DBG
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \
if(!(expr)) { \
DbgPrint( "Assertion failed! %s at ......\n", #expr); \
DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
RT_PRINTK fmt; \
ASSERT(FALSE); \
}
#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); }
#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); }
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); }
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
int __i; \
pu1Byte __ptr = (pu1Byte)ptr; \
DbgPrint("[ODM] "); \
DbgPrint(title_str); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#else
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
#define ODM_dbg_enter()
#define ODM_dbg_exit()
#define ODM_dbg_trace(str)
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
#endif
VOID
ODM_InitDebugSetting(
IN PDM_ODM_T pDM_Odm
);
#if 0
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif
#if 0
/* Define debug print header for every service module.*/
typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}ODM_DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_ODM_DBGP_Flag_Type_Definition
{
ODM_FTX = 0,
ODM_FRX ,
ODM_FPHY ,
ODM_FPWR ,
ODM_FDM ,
ODM_FC2H ,
ODM_FBT ,
ODM_DBGP_TYPE_MAX
}ODM_DBGP_FLAG_E;
// Define TX relative debug bit --> FTX
#define ODM_TX_DESC BIT0
#define ODM_TX_DESC_TID BIT1
#define ODM_TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define ODM_RX_DATA BIT0
#define ODM_RX_PHY_STS BIT1
#define ODM_RX_PHY_SS BIT2
#define ODM_RX_PHY_SQ BIT3
#define ODM_RX_PHY_ASTS BIT4
#define ODM_RX_ERR_LEN BIT5
#define ODM_RX_DEFRAG BIT6
#define ODM_RX_ERR_RATE BIT7
#define ODM_RX_PATH BIT8
#define ODM_RX_BEACON BIT9
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define ODM_PHY_BBR BIT0
#define ODM_PHY_BBW BIT1
#define ODM_PHY_RFR BIT2
#define ODM_PHY_RFW BIT3
#define ODM_PHY_MACR BIT4
#define ODM_PHY_MACW BIT5
#define ODM_PHY_ALLR BIT6
#define ODM_PHY_ALLW BIT7
#define ODM_PHY_TXPWR BIT8
#define ODM_PHY_PWRDIFF BIT9
#define ODM_PHY_SICR BIT10
#define ODM_PHY_SICW BIT11
extern u4Byte ODM_GlobalDebugLevel;
#if DBG
extern u8Byte ODM_GlobalDebugComponents;
#endif
#endif
#if 0
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE(pDM_Odm,)!
//
#define DBG_OFF 0
//
// Deprecated! Don't use it!
// TODO: fix related debug message!
//
//#define DBG_SEC 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
#define COMP_TRACE BIT0 // For function call tracing.
#define COMP_DBG BIT1 // Only for temporary debug message.
#define COMP_INIT BIT2 // during driver initialization / halt / reset.
#define COMP_OID_QUERY BIT3 // Query OID.
#define COMP_OID_SET BIT4 // Set OID.
#define COMP_RECV BIT5 // Reveive part data path.
#define COMP_SEND BIT6 // Send part path.
#define COMP_IO BIT7 // I/O Related. Added by Annie, 2006-03-02.
#define COMP_POWER BIT8 // 802.11 Power Save mode or System/Device Power state related.
#define COMP_MLME BIT9 // 802.11 link related: join/start BSS, leave BSS.
#define COMP_SCAN BIT10 // For site survey.
#define COMP_SYSTEM BIT11 // For general platform function.
#define COMP_SEC BIT12 // For Security.
#define COMP_AP BIT13 // For AP mode related.
#define COMP_TURBO BIT14 // For Turbo Mode related. By Annie, 2005-10-21.
#define COMP_QOS BIT15 // For QoS.
#define COMP_AUTHENTICATOR BIT16 // For AP mode Authenticator. Added by Annie, 2006-01-30.
#define COMP_BEACON BIT17 // For Beacon related, by rcnjko.
#define COMP_ANTENNA BIT18 // For Antenna diversity related, by rcnjko.
#define COMP_RATE BIT19 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
#define COMP_EVENTS BIT20 // Event handling
#define COMP_FPGA BIT21 // For FPGA verfication
#define COMP_RM BIT22 // For Radio Measurement.
#define COMP_MP BIT23 // For mass production test, by shien chang, 2006.07.13
#define COMP_RXDESC BIT24 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
#define COMP_CKIP BIT25 // For CCX 1 S13: CKIP. Added by Annie, 2006-08-14.
#define COMP_DIG BIT26 // For DIG, 2006.09.25, by rcnjko.
#define COMP_TXAGC BIT27 // For Tx power, 060928, by rcnjko.
#define COMP_HIPWR BIT28 // For High Power Mechanism, 060928, by rcnjko.
#define COMP_HALDM BIT29 // For HW Dynamic Mechanism, 061010, by rcnjko.
#define COMP_RSNA BIT30 // For RSNA IBSS , 061201, by CCW.
#define COMP_INDIC BIT31 // For link indication
#define COMP_LED BIT32 // For LED.
#define COMP_RF BIT33 // For RF.
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
#define COMP_HT BIT34 // For 802.11n HT related information. by Emily 2006-8-11
#define COMP_POWER_TRACKING BIT35 //FOR 8190 TX POWER TRACKING
#define COMP_RX_REORDER BIT36 // 8190 Rx Reorder
#define COMP_AMSDU BIT37 // For A-MSDU Debugging
#define COMP_WPS BIT38 //WPS Debug Message
#define COMP_RATR BIT39
#define COMP_RESET BIT40
// For debug command to print on dbgview!!
#define COMP_CMD BIT41
#define COMP_EFUSE BIT42
#define COMP_MESH_INTERWORKING BIT43
#define COMP_CCX BIT44 //CCX Debug Flag
#define COMP_IOCTL BIT45 // IO Control
#define COMP_GP BIT46 // For generic parser.
#define COMP_TXAGG BIT47
#define COMP_HVL BIT48 // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer
#define COMP_TEST BIT49
#define COMP_BB_POWERSAVING BIT50
#define COMP_SWAS BIT51 // For SW Antenna Switch
#define COMP_P2P BIT52
#define COMP_MUX BIT53
#define COMP_FUNC BIT54
#define COMP_TDLS BIT55
#define COMP_OMNIPEEK BIT56
#define COMP_DUALMACSWITCH BIT60 // 2010/12/27 Add for Dual mac mode debug
#define COMP_EASY_CONCURRENT BIT61 // 2010/12/27 Add for easy cncurrent mode debug
#define COMP_PSD BIT63 //2011/3/9 Add for WLAN PSD for BT AFH
#define COMP_DFS BIT62
#define COMP_ALL UINT64_C(0xFFFFFFFFFFFFFFFF) // All components
// For debug print flag to use
/*------------------------------Define structure----------------------------*/
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/* Defnie structure to store different debug flag variable. Every debug flag
is a UINT32 integer and you can assign 32 different events. */
typedef struct tag_DBGP_Debug_Flag_Structure
{
u4Byte Mans; /* Main Scheduler module. */
u4Byte Rtos; /* RTOS module. */
u4Byte Alarm; /* Alarm module. */
u4Byte Pm; /* Performance monitor module. */
}DBGP_FLAG_T;
/* Define debug print header for every service module.*/
typedef struct tag_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_DBGP_Flag_Type_Definition
{
FQoS = 0,
FTX = 1,
FRX = 2,
FSEC = 3,
FMGNT = 4,
FMLME = 5,
FRESOURCE = 6,
FBEACON = 7,
FISR = 8,
FPHY = 9,
FMP = 10,
FEEPROM = 11,
FPWR = 12,
FDM = 13,
FDBG_CTRL = 14,
FC2H = 15,
FBT = 16,
FINIT = 17,
FIOCTL = 18,
FSHORT_CUT = 19,
DBGP_TYPE_MAX
}DBGP_FLAG_E;
// Define Qos Relative debug flag bit --> FQoS
#define QoS_INIT BIT0
#define QoS_VISTA BIT1
// Define TX relative debug bit --> FTX
#define TX_DESC BIT0
#define TX_DESC_TID BIT1
#define TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define RX_DATA BIT0
#define RX_PHY_STS BIT1
#define RX_PHY_SS BIT2
#define RX_PHY_SQ BIT3
#define RX_PHY_ASTS BIT4
#define RX_ERR_LEN BIT5
#define RX_DEFRAG BIT6
#define RX_ERR_RATE BIT7
#define RX_PATH BIT8
#define RX_BEACON BIT9
// Define Security relative debug bit --> FSEC
// Define MGNT relative debug bit --> FMGNT
// Define MLME relative debug bit --> FMLME
#define MEDIA_STS BIT0
#define LINK_STS BIT1
// Define OS resource check module bit --> FRESOURCE
#define OS_CHK BIT0
// Define beacon content check module bit --> FBEACON
#define BCN_SHOW BIT0
#define BCN_PEER BIT1
// Define ISR/IMR check module bit --> FISR
#define ISR_CHK BIT0
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define PHY_BBR BIT0
#define PHY_BBW BIT1
#define PHY_RFR BIT2
#define PHY_RFW BIT3
#define PHY_MACR BIT4
#define PHY_MACW BIT5
#define PHY_ALLR BIT6
#define PHY_ALLW BIT7
#define PHY_TXPWR BIT8
#define PHY_PWRDIFF BIT9
#define PHY_SICR BIT10
#define PHY_SICW BIT11
// Define MPT driver check module bit --> FMP
#define MP_RX BIT0
#define MP_SWICH_CH BIT1
// Define EEPROM and EFUSE check module bit --> FEEPROM
#define EEPROM_W BIT0
#define EFUSE_PG BIT1
#define EFUSE_READ_ALL BIT2
#define EFUSE_ANALYSIS BIT3
#define EFUSE_PG_DETAIL BIT4
// Define power save check module bit --> FPWR
#define LPS BIT0
#define IPS BIT1
#define PWRSW BIT2
#define PWRHW BIT3
#define PWRHAL BIT4
// Define Dynamic Mechanism check module bit --> FDM
#define WA_IOT BIT0
#define DM_PWDB BIT1
#define DM_Monitor BIT2
#define DM_DIG BIT3
#define DM_EDCA_Turbo BIT4
#define DM_BT30 BIT5
// Define Dbg Control module bit --> FDBG_CTRL
#define DBG_CTRL_TRACE BIT0
#define DBG_CTRL_INBAND_NOISE BIT1
// Define FW C2H Cmd check module bit --> FC2H
#define C2H_Summary BIT0
#define C2H_PacketData BIT1
#define C2H_ContentData BIT2
// Define BT Cmd check module bit --> FBT
#define BT_TRACE BIT0
#define BT_RFPoll BIT1
// Define init check for module bit --> FINIT
#define INIT_EEPROM BIT0
#define INIT_TxPower BIT1
#define INIT_IQK BIT2
#define INIT_RF BIT3
// Define IOCTL Cmd check module bit --> FIOCTL
// section 1 : IRP related
#define IOCTL_IRP BIT0
#define IOCTL_IRP_DETAIL BIT1
#define IOCTL_IRP_STATISTICS BIT2
#define IOCTL_IRP_HANDLE BIT3
// section 2 : HCI command/event
#define IOCTL_BT_HCICMD BIT8
#define IOCTL_BT_HCICMD_DETAIL BIT9
#define IOCTL_BT_HCICMD_EXT BIT10
#define IOCTL_BT_EVENT BIT11
#define IOCTL_BT_EVENT_DETAIL BIT12
#define IOCTL_BT_EVENT_PERIODICAL BIT13
// section 3 : BT tx/rx data and throughput
#define IOCTL_BT_TX_ACLDATA BIT16
#define IOCTL_BT_TX_ACLDATA_DETAIL BIT17
#define IOCTL_BT_RX_ACLDATA BIT18
#define IOCTL_BT_RX_ACLDATA_DETAIL BIT19
#define IOCTL_BT_TP BIT20
// section 4 : BT connection state machine.
#define IOCTL_STATE BIT21
#define IOCTL_BT_LOGO BIT22
// section 5 : BT function trace
#define IOCTL_CALLBACK_FUN BIT24
#define IOCTL_PARSE_BT_PKT BIT25
#define IOCTL_BT_TX_PKT BIT26
#define IOCTL_BT_FLAG_MON BIT27
//
// Define init check for module bit --> FSHORT_CUT
// 2011/07/20 MH Add for short but definition.
//
#define SHCUT_TX BIT0
#define SHCUT_RX BIT1
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define RT_PRINTK(fmt, args...) printk( "%s(): " fmt, __FUNCTION__, ## args);
#if DBG
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) \
if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_TRACE_F(comp, level, fmt) \
if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_ASSERT(expr,fmt) \
if(!(expr)) { \
printk( "Assertion failed! %s at ......\n", #expr); \
printk( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
}
#define dbg_enter() { printk("==> %s\n", __FUNCTION__); }
#define dbg_exit() { printk("<== %s\n", __FUNCTION__); }
#define dbg_trace(str) { printk("%s:%s\n", __FUNCTION__, str); }
#else
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt)
#define RT_TRACE_F(comp, level, fmt)
#define RT_ASSERT(expr, fmt)
#define dbg_enter()
#define dbg_exit()
#define dbg_trace(str)
#endif
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif // #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define DEBUG_PRINT 1
// Please add new OS's print API by yourself
//#if (RT_PLATFORM==PLATFORM_WINDOWS)
#if (DEBUG_PRINT == 1) && DBG
#define RT_DISP(dbgtype, dbgflag, printstr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
DbgPrint printstr;\
}\
}
#define RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint printstr; \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}\
}
#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" ");\
if (((__i + 1) % 16) == 0) DbgPrint("\n");\
} \
DbgPrint("\n"); \
}\
}
#define FunctionIn(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n", __FUNCTION__))
#define FunctionOut(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n", __FUNCTION__))
#else
#define RT_DISP(dbgtype, dbgflag, printstr)
#define RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)
#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)
#define FunctionIn(_comp)
#define FunctionOut(_comp)
#endif
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export global variable----------------------------*/
extern u4Byte DBGP_Type[DBGP_TYPE_MAX];
extern DBGP_HEAD_T DBGP_Head;
/*------------------------Export global variable----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
extern void DBGP_Flag_Init(void);
extern void DBG_PrintAllFlag(void);
extern void DBG_PrintAllComp(void);
extern void DBG_PrintFlagEvent(u1Byte DbgFlag);
extern void DBG_DumpMem(const u1Byte DbgComp,
const u1Byte DbgLevel,
pu1Byte pMem,
u2Byte Len);
/*--------------------------Exported Function prototype---------------------*/
extern u4Byte GlobalDebugLevel;
extern u8Byte GlobalDebugComponents;
#endif
#endif // __ODM_DBG_H__

764
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_interface.c
View File

@ -1,764 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "odm_precomp.h"
//
// ODM IO Relative API.
//
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R8(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read8(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead1Byte(Adapter, RegAddr);
#endif
}
u2Byte
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R16(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read16(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead2Byte(Adapter, RegAddr);
#endif
}
u4Byte
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R32(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read32(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead4Byte(Adapter, RegAddr);
#endif
}
VOID
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u1Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W8(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write8(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite1Byte(Adapter, RegAddr, Data);
#endif
}
VOID
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W16(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write16(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite2Byte(Adapter, RegAddr, Data);
#endif
}
VOID
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W32(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write32(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite4Byte(Adapter, RegAddr, Data);
#endif
}
VOID
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
#endif
}
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryMacReg(pDM_Odm->priv, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryMacReg(Adapter, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
return PHY_QueryBBReg(pDM_Odm->Adapter, RegAddr, BitMask);
#endif
}
VOID
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
#endif
}
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
#endif
}
VOID
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data);
#endif
}
u4Byte
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask);
#endif
}
//
// ODM Memory relative API.
//
VOID
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID *pPtr,
IN u4Byte length
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
*pPtr = kmalloc(length, GFP_ATOMIC);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
*pPtr = rtw_zvmalloc(length);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformAllocateMemory(Adapter, pPtr, length);
#endif
}
// length could be ignored, used to detect memory leakage.
VOID
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pPtr,
IN u4Byte length
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
kfree(pPtr);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
rtw_vmfree(pPtr, length);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
//PADAPTER Adapter = pDM_Odm->Adapter;
PlatformFreeMemory(pPtr, length);
#endif
}
VOID
ODM_MoveMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pDest,
IN PVOID pSrc,
IN u4Byte Length
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
_rtw_memcpy(pDest, pSrc, Length);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformMoveMemory(pDest, pSrc, Length);
#endif
}
void ODM_Memory_Set
(IN PDM_ODM_T pDM_Odm,
IN PVOID pbuf,
IN s1Byte value,
IN u4Byte length)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
_rtw_memset(pbuf,value, length);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformFillMemory(pbuf,length,value);
#endif
}
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN PVOID pBuf1,
IN PVOID pBuf2,
IN u4Byte length
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return memcmp(pBuf1,pBuf2,length);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
return _rtw_memcmp(pBuf1,pBuf2,length);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
return PlatformCompareMemory(pBuf1,pBuf2,length);
#endif
}
//
// ODM MISC relative API.
//
VOID
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformAcquireSpinLock(Adapter, type);
#endif
}
VOID
ODM_ReleaseSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformReleaseSpinLock(Adapter, type);
#endif
}
//
// Work item relative API. FOr MP driver only~!
//
VOID
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
IN PRT_WORK_ITEM pRtWorkItem,
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
IN PVOID pContext,
IN const char* szID
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformInitializeWorkItem(Adapter, pRtWorkItem, RtWorkItemCallback, pContext, szID);
#endif
}
VOID
ODM_StartWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformStartWorkItem(pRtWorkItem);
#endif
}
VOID
ODM_StopWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformStopWorkItem(pRtWorkItem);
#endif
}
VOID
ODM_FreeWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformFreeWorkItem(pRtWorkItem);
#endif
}
VOID
ODM_ScheduleWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformScheduleWorkItem(pRtWorkItem);
#endif
}
VOID
ODM_IsWorkItemScheduled(
IN PRT_WORK_ITEM pRtWorkItem
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformIsWorkItemScheduled(pRtWorkItem);
#endif
}
//
// ODM Timer relative API.
//
VOID
ODM_StallExecution(
IN u4Byte usDelay
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_udelay_os(usDelay);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformStallExecution(usDelay);
#endif
}
VOID
ODM_delay_ms(IN u4Byte ms)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
delay_ms(ms);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_mdelay_os(ms);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
delay_ms(ms);
#endif
}
VOID
ODM_delay_us(IN u4Byte us)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
delay_us(us);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_udelay_os(us);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformStallExecution(us);
#endif
}
VOID
ODM_sleep_ms(IN u4Byte ms)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_msleep_os(ms);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
#endif
}
VOID
ODM_sleep_us(IN u4Byte us)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_usleep_os(us);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
#endif
}
VOID
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
mod_timer(pTimer, jiffies + (msDelay+9)/10);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
_set_timer(pTimer,msDelay ); //ms
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformSetTimer(Adapter, pTimer, msDelay);
#endif
}
VOID
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN PVOID pContext,
IN const char* szID
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pTimer->function = CallBackFunc;
pTimer->data = (unsigned long)pDM_Odm;
init_timer(pTimer);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
_init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID);
#endif
}
VOID
ODM_CancelTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
del_timer_sync(pTimer);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
_cancel_timer_ex(pTimer);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformCancelTimer(Adapter, pTimer);
#endif
}
VOID
ODM_ReleaseTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
// <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm.
// Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail.
if (pTimer == 0)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n"));
return;
}
PlatformReleaseTimer(Adapter, pTimer);
#endif
}
//
// ODM FW relative API.
//
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
VOID
ODM_FillH2CCmd(
IN PADAPTER Adapter,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
)
{
if(IS_HARDWARE_TYPE_JAGUAR(Adapter))
{
switch(ElementID)
{
case ODM_H2C_RSSI_REPORT:
FillH2CCmd8812(Adapter, H2C_8812_RSSI_REPORT, CmdLen, pCmdBuffer);
break;
default:
break;
}
}
else if(IS_HARDWARE_TYPE_8192E(Adapter))
{
switch(ElementID)
{
case ODM_H2C_RSSI_REPORT:
FillH2CCmd8812(Adapter, H2C_8812_RSSI_REPORT, CmdLen, pCmdBuffer);
break;
default:
break;
}
}
else if(IS_HARDWARE_TYPE_8723B(Adapter))
{
//
// <Roger_TODO> We should take RTL8723B into consideration, 2012.10.08
//
switch(ElementID)
{
case ODM_H2C_RSSI_REPORT:
FillH2CCmd8723B(Adapter, H2C_8723B_RSSI_REPORT, CmdLen, pCmdBuffer);
break;
default:
break;
}
}
else if(IS_HARDWARE_TYPE_8188E(Adapter))
{
switch(ElementID)
{
case ODM_H2C_PSD_RESULT:
FillH2CCmd88E(Adapter, H2C_88E_PSD_RESULT, CmdLen, pCmdBuffer);
break;
case ODM_H2C_RSSI_REPORT:
if(IS_VENDOR_8188E_I_CUT_SERIES(Adapter))
FillH2CCmd88E(Adapter, H2C_88E_RSSI_REPORT, CmdLen, pCmdBuffer);
break;
default:
break;
}
}
else
{
switch(ElementID)
{
case ODM_H2C_RSSI_REPORT:
FillH2CCmd92C(Adapter, H2C_RSSI_REPORT, CmdLen, pCmdBuffer);
break;
case ODM_H2C_PSD_RESULT:
FillH2CCmd92C(Adapter, H2C_92C_PSD_RESULT, CmdLen, pCmdBuffer);
break;
default:
break;
}
}
}
#else
u4Byte
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u4Byte H2CBufferLen,
IN u4Byte CmdNum,
IN pu4Byte pElementID,
IN pu4Byte pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
//FillH2CCmd(pH2CBuffer, H2CBufferLen, CmdNum, pElementID, pCmdLen, pCmbBuffer, CmdStartSeq);
return FALSE;
#endif
return TRUE;
}
#endif
u4Byte
ODM_GetCurrentTime(
IN PDM_ODM_T pDM_Odm
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return 0;
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
return rtw_get_current_time();
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
return 0;
#endif
}
s4Byte
ODM_GetProgressingTime(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Start_Time
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return 0;
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
return rtw_get_passing_time_ms(Start_Time);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
return 0;
#endif
}

400
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_interface.h
View File

@ -1,400 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_INTERFACE_H__
#define __ODM_INTERFACE_H__
//
// =========== Constant/Structure/Enum/... Define
//
//
// =========== Macro Define
//
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
// _cat: implemented by Token-Pasting Operator.
#if 0
#define _cat(_name, _ic_type, _func) \
( \
_func##_all(_name) \
)
#endif
/*===================================
#define ODM_REG_DIG_11N 0xC50
#define ODM_REG_DIG_11AC 0xDDD
ODM_REG(DIG,_pDM_Odm)
=====================================*/
#define _reg_11N(_name) ODM_REG_##_name##_11N
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#if 1 //TODO: enable it if we need to support run-time to differentiate between 92C_SERIES and JAGUAR_SERIES.
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
_func##_11AC(_name) \
)
#endif
#if 0 // only sample code
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C): \
((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D): \
((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S): \
((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A): \
((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \
_func##_ic(_name, _8195) \
)
#endif
// _name: name of register or bit.
// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)"
// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType.
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
typedef enum _ODM_H2C_CMD
{
ODM_H2C_RSSI_REPORT = 0,
ODM_H2C_PSD_RESULT=1,
ODM_H2C_PathDiv = 2,
ODM_MAX_H2CCMD
}ODM_H2C_CMD;
//
// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem.
// Suggest HW team to use thread instead of workitem. Windows also support the feature.
//
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
typedef void *PRT_WORK_ITEM ;
typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
#if 0
typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE;
typedef struct _RT_WORK_ITEM
{
RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object.
PVOID Adapter; // Pointer to Adapter object.
PVOID pContext; // Parameter to passed to CallBackFunc().
RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem.
u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled.
PVOID pPlatformExt; // Pointer to platform-dependent extension.
BOOLEAN bFree;
char szID[36]; // An identity string of this workitem.
}RT_WORK_ITEM, *PRT_WORK_ITEM;
#endif
#endif
//
// =========== Extern Variable ??? It should be forbidden.
//
//
// =========== EXtern Function Prototype
//
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u2Byte
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u4Byte
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
VOID
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u1Byte Data
);
VOID
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
);
VOID
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
);
VOID
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
//
// Memory Relative Function.
//
VOID
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID *pPtr,
IN u4Byte length
);
VOID
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pPtr,
IN u4Byte length
);
VOID
ODM_MoveMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pDest,
IN PVOID pSrc,
IN u4Byte Length
);
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN PVOID pBuf1,
IN PVOID pBuf2,
IN u4Byte length
);
void ODM_Memory_Set
(IN PDM_ODM_T pDM_Odm,
IN PVOID pbuf,
IN s1Byte value,
IN u4Byte length);
//
// ODM MISC-spin lock relative API.
//
VOID
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
VOID
ODM_ReleaseSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
//
// ODM MISC-workitem relative API.
//
VOID
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
IN PRT_WORK_ITEM pRtWorkItem,
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_StartWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_StopWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_FreeWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_ScheduleWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_IsWorkItemScheduled(
IN PRT_WORK_ITEM pRtWorkItem
);
//
// ODM Timer relative API.
//
VOID
ODM_StallExecution(
IN u4Byte usDelay
);
VOID
ODM_delay_ms(IN u4Byte ms);
VOID
ODM_delay_us(IN u4Byte us);
VOID
ODM_sleep_ms(IN u4Byte ms);
VOID
ODM_sleep_us(IN u4Byte us);
VOID
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
);
VOID
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_CancelTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
VOID
ODM_ReleaseTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
//
// ODM FW relative API.
//
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
VOID
ODM_FillH2CCmd(
IN PADAPTER Adapter,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
);
#else
u4Byte
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u4Byte H2CBufferLen,
IN u4Byte CmdNum,
IN pu4Byte pElementID,
IN pu4Byte pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
);
#endif
u4Byte
ODM_GetCurrentTime(
IN PDM_ODM_T pDM_Odm
);
s4Byte
ODM_GetProgressingTime(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Start_Time
);
#endif // __ODM_INTERFACE_H__

314
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_precomp.h
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@ -1,314 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_PRECOMP_H__
#define __ODM_PRECOMP_H__
#include "odm_types.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting.
#else
#define TEST_FALG___ 1
#endif
//2 Config Flags and Structs - defined by each ODM Type
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "../8192cd_cfg.h"
#include "../odm_inc.h"
#include "../8192cd.h"
#include "../8192cd_util.h"
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#ifdef AP_BUILD_WORKAROUND
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
// Flags
#include "../8192cd_cfg.h" // OUTSRC needs ADSL config flags.
#include "../odm_inc.h" // OUTSRC needs some extra flags.
// Data Structure
#include "../common_types.h" // OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0.
#include "../8192cd.h" // OUTSRC needs basic ADSL struct definition.
#include "../8192cd_util.h" // OUTSRC needs basic I/O function.
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#ifdef ADSL_AP_BUILD_WORKAROUND
// NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14.
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE)
//#include <drv_conf.h>
//#include <basic_types.h>
//#include <osdep_service.h>
//#include <drv_types.h>
//#include <rtw_byteorder.h>
//#include <hal_intf.h>
#define BEAMFORMING_SUPPORT 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Mp_Precomp.h"
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
//2 Hardware Parameter Files
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/Hal8192CEFWImg_AP.h"
#include "rtl8192c/Hal8192CEPHYImg_AP.h"
#include "rtl8192c/Hal8192CEMACImg_AP.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/Hal8192CEFWImg_ADSL.h"
#include "rtl8192c/Hal8192CEPHYImg_ADSL.h"
#include "rtl8192c/Hal8192CEMACImg_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#if(RTL8192CE_SUPPORT ==1)
#include "rtl8192c/Hal8192CEFWImg_CE.h"
#include "rtl8192c/Hal8192CEPHYImg_CE.h"
#include "rtl8192c/Hal8192CEMACImg_CE.h"
#endif
#if(RTL8192CU_SUPPORT ==1)
#include "rtl8192c/Hal8192CUFWImg_CE.h"
#include "rtl8192c/Hal8192CUPHYImg_CE.h"
#include "rtl8192c/Hal8192CUMACImg_CE.h"
#endif
#if(RTL8192DE_SUPPORT ==1)
#include "rtl8192d/Hal8192DEFWImg_CE.h"
#include "rtl8192d/Hal8192DEPHYImg_CE.h"
#include "rtl8192d/Hal8192DEMACImg_CE.h"
#endif
#if(RTL8192DU_SUPPORT ==1)
#include "rtl8192d/Hal8192DUFWImg_CE.h"
#include "rtl8192d/Hal8192DUPHYImg_CE.h"
#include "rtl8192d/Hal8192DUMACImg_CE.h"
#endif
#if(RTL8723AS_SUPPORT==1)
#include "rtl8723a/Hal8723SHWImg_CE.h"
#endif
#if(RTL8723AU_SUPPORT==1)
#include "rtl8723a/Hal8723UHWImg_CE.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#endif
//2 OutSrc Header Files
#include "odm.h"
#include "odm_HWConfig.h"
#include "odm_debug.h"
#include "odm_RegDefine11AC.h"
#include "odm_RegDefine11N.h"
#include "odm_AntDiv.h"
#include "odm_EdcaTurboCheck.h"
#include "odm_DIG.h"
#include "odm_PathDiv.h"
#include "odm_DynamicBBPowerSaving.h"
#include "odm_DynamicTxPower.h"
#include "odm_CfoTracking.h"
#include "odm_NoiseMonitor.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_AP.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/HalDMOutSrc8192C_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
//#include "hal_com.h"
#include "HalPhyRf.h"
#if (RTL8192C_SUPPORT==1)
#ifdef CONFIG_INTEL_PROXIM
#include "../proxim/intel_proxim.h"
#endif
#include "rtl8192c/HalDMOutSrc8192C_CE.h"
#include <rtl8192c_hal.h>
#endif
#if (RTL8192D_SUPPORT==1)
#include "rtl8192d/HalDMOutSrc8192D_CE.h"
#include "rtl8192d_hal.h"
#endif
#if (RTL8723A_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_CE.h" //for IQK,LCK,Power-tracking
#include "rtl8723a_hal.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#include "rtl8188e_hal.h"
#endif
#if (RTL8192E_SUPPORT==1)
#include "rtl8192e/HalPhyRf_8192e.h"//for IQK,LCK,Power-tracking
#include "rtl8192e_hal.h"
#endif
#if (RTL8812A_SUPPORT==1)
#include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a_hal.h"
#endif
#if (RTL8821A_SUPPORT==1)
#include "rtl8821a/HalPhyRf_8821A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a_hal.h"
#endif
#if (RTL8723B_SUPPORT==1)
#include "rtl8723b/HalPhyRf_8723B.h"//for IQK,LCK,Power-tracking
#include "rtl8723b_hal.h"
#endif
#endif
#include "odm_interface.h"
#include "odm_reg.h"
#if (RTL8192C_SUPPORT==1)
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "rtl8192c/Hal8192CHWImg_MAC.h"
#include "rtl8192c/Hal8192CHWImg_RF.h"
#include "rtl8192c/Hal8192CHWImg_BB.h"
#include "rtl8192c/Hal8192CHWImg_FW.h"
#endif
#include "rtl8192c/odm_RTL8192C.h"
#endif
#if (RTL8192D_SUPPORT==1)
#include "rtl8192d/odm_RTL8192D.h"
#endif
#if (RTL8723A_SUPPORT==1)
#include "rtl8723a/HalHWImg8723A_MAC.h"
#include "rtl8723a/HalHWImg8723A_RF.h"
#include "rtl8723a/HalHWImg8723A_BB.h"
#include "rtl8723a/HalHWImg8723A_FW.h"
#include "rtl8723a/odm_RegConfig8723A.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/HalHWImg8188E_MAC.h"
#include "rtl8188e/HalHWImg8188E_RF.h"
#include "rtl8188e/HalHWImg8188E_BB.h"
#include "rtl8188e/HalHWImg8188E_FW.h"
#include "rtl8188e/Hal8188EReg.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#include "rtl8188e/HalPhyRf_8188e.h"
#endif
#if (TESTCHIP_SUPPORT == 1)
#include "rtl8188e/HalHWImg8188E_TestChip_MAC.h"
#include "rtl8188e/HalHWImg8188E_TestChip_RF.h"
#include "rtl8188e/HalHWImg8188E_TestChip_BB.h"
#endif
#include "rtl8188e/odm_RegConfig8188E.h"
#include "rtl8188e/odm_RTL8188E.h"
#endif
#if (RTL8192E_SUPPORT==1)
#include "rtl8192e/HalHWImg8192E_MAC.h"
#include "rtl8192e/HalHWImg8192E_RF.h"
#include "rtl8192e/HalHWImg8192E_BB.h"
#include "rtl8192e/HalHWImg8192E_FW.h"
#include "rtl8192e/Hal8192EReg.h"
#include "rtl8192e/odm_RegConfig8192E.h"
#include "rtl8192e/odm_RTL8192E.h"
#endif
#if (RTL8723B_SUPPORT==1)
#include "rtl8723b/HalHWImg8723B_MAC.h"
#include "rtl8723b/HalHWImg8723B_RF.h"
#include "rtl8723b/HalHWImg8723B_BB.h"
#include "rtl8723b/HalHWImg8723B_FW.h"
#include "rtl8723b/HalHWImg8723B_MP.h"
#include "rtl8723b/Hal8723BReg.h"
#include "rtl8723b/odm_RTL8723B.h"
#include "rtl8723b/odm_RegConfig8723B.h"
#endif
#if (RTL8812A_SUPPORT==1)
#include "rtl8812a/HalHWImg8812A_MAC.h"
#include "rtl8812a/HalHWImg8812A_RF.h"
#include "rtl8812a/HalHWImg8812A_BB.h"
#include "rtl8812a/HalHWImg8812A_FW.h"
#include "rtl8812a/odm_RegConfig8812A.h"
#include "rtl8812a/odm_RTL8812A.h"
#if (TESTCHIP_SUPPORT == 1)
#include "rtl8812a/HalHWImg8812A_TestChip_MAC.h"
#include "rtl8812a/HalHWImg8812A_TestChip_RF.h"
#include "rtl8812a/HalHWImg8812A_TestChip_BB.h"
#endif
#endif
#if (RTL8821A_SUPPORT==1)
#include "rtl8821a/HalHWImg8821A_MAC.h"
#include "rtl8821a/HalHWImg8821A_RF.h"
#include "rtl8821a/HalHWImg8821A_BB.h"
#include "rtl8821a/HalHWImg8821A_FW.h"
#include "rtl8821a/odm_RegConfig8821A.h"
#include "rtl8821a/odm_RTL8821A.h"
#if (TESTCHIP_SUPPORT == 1)
#include "rtl8821a/HalHWImg8821A_TestChip_MAC.h"
#include "rtl8821a/HalHWImg8821A_TestChip_RF.h"
#include "rtl8821a/HalHWImg8821A_TestChip_BB.h"
#include "rtl8821a/HalHWImg8821A_TestChip_FW.h"
#endif
#endif
#endif // __ODM_PRECOMP_H__

122
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/odm_reg.h
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@ -1,122 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// File Name: odm_reg.h
//
// Description:
//
// This file is for general register definition.
//
//
//============================================================
#ifndef __HAL_ODM_REG_H__
#define __HAL_ODM_REG_H__
//
// Register Definition
//
//MAC REG
#define ODM_BB_RESET 0x002
#define ODM_DUMMY 0x4fe
#define RF_T_METER_OLD 0x24
#define RF_T_METER_NEW 0x42
#define ODM_EDCA_VO_PARAM 0x500
#define ODM_EDCA_VI_PARAM 0x504
#define ODM_EDCA_BE_PARAM 0x508
#define ODM_EDCA_BK_PARAM 0x50C
#define ODM_TXPAUSE 0x522
//BB REG
#define ODM_FPGA_PHY0_PAGE8 0x800
#define ODM_PSD_SETTING 0x808
#define ODM_AFE_SETTING 0x818
#define ODM_TXAGC_B_24_54 0x834
#define ODM_TXAGC_B_MCS32_5 0x838
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
#define ODM_TXAGC_B_MCS4_MCS7 0x848
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
#define ODM_ANALOG_REGISTER 0x85c
#define ODM_RF_INTERFACE_OUTPUT 0x860
#define ODM_TXAGC_B_MCS12_MCS15 0x868
#define ODM_TXAGC_B_11_A_2_11 0x86c
#define ODM_AD_DA_LSB_MASK 0x874
#define ODM_ENABLE_3_WIRE 0x88c
#define ODM_PSD_REPORT 0x8b4
#define ODM_R_ANT_SELECT 0x90c
#define ODM_CCK_ANT_SELECT 0xa07
#define ODM_CCK_PD_THRESH 0xa0a
#define ODM_CCK_RF_REG1 0xa11
#define ODM_CCK_MATCH_FILTER 0xa20
#define ODM_CCK_RAKE_MAC 0xa2e
#define ODM_CCK_CNT_RESET 0xa2d
#define ODM_CCK_TX_DIVERSITY 0xa2f
#define ODM_CCK_FA_CNT_MSB 0xa5b
#define ODM_CCK_FA_CNT_LSB 0xa5c
#define ODM_CCK_NEW_FUNCTION 0xa75
#define ODM_OFDM_PHY0_PAGE_C 0xc00
#define ODM_OFDM_RX_ANT 0xc04
#define ODM_R_A_RXIQI 0xc14
#define ODM_R_A_AGC_CORE1 0xc50
#define ODM_R_A_AGC_CORE2 0xc54
#define ODM_R_B_AGC_CORE1 0xc58
#define ODM_R_AGC_PAR 0xc70
#define ODM_R_HTSTF_AGC_PAR 0xc7c
#define ODM_TX_PWR_TRAINING_A 0xc90
#define ODM_TX_PWR_TRAINING_B 0xc98
#define ODM_OFDM_FA_CNT1 0xcf0
#define ODM_OFDM_PHY0_PAGE_D 0xd00
#define ODM_OFDM_FA_CNT2 0xda0
#define ODM_OFDM_FA_CNT3 0xda4
#define ODM_OFDM_FA_CNT4 0xda8
#define ODM_TXAGC_A_6_18 0xe00
#define ODM_TXAGC_A_24_54 0xe04
#define ODM_TXAGC_A_1_MCS32 0xe08
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
//RF REG
#define ODM_GAIN_SETTING 0x00
#define ODM_CHANNEL 0x18
//Ant Detect Reg
#define ODM_DPDT 0x300
//PSD Init
#define ODM_PSDREG 0x808
//92D Path Div
#define PATHDIV_REG 0xB30
#define PATHDIV_TRI 0xBA0
//
// Bitmap Definition
//
#define BIT_FA_RESET BIT0
#endif

213
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_ACS.c
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@ -1,213 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
u1Byte
ODM_GetAutoChannelSelectResult(
IN PVOID pDM_VOID,
IN u1Byte Band
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(Band == ODM_BAND_2_4G)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_2G(%d)\n", pACS->CleanChannel_2G));
return (u1Byte)pACS->CleanChannel_2G;
}
else
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_5G(%d)\n", pACS->CleanChannel_5G));
return (u1Byte)pACS->CleanChannel_5G;
}
#else
return (u1Byte)pACS->CleanChannel_2G;
#endif
}
VOID
odm_AutoChannelSelectSetting(
IN PVOID pDM_VOID,
IN BOOLEAN IsEnable
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u2Byte period = 0x2710;// 40ms in default
u2Byte NHMType = 0x7;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSetting()=========> \n"));
if(IsEnable)
{//20 ms
period = 0x1388;
NHMType = 0x1;
}
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
//PHY parameters initialize for ac series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, period); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, NHMType); //0x994[9:8]=3 enable CCX
}
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
//PHY parameters initialize for n series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, period); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, NHMType); //0x890[9:8]=3 enable CCX
}
#endif
}
VOID
odm_AutoChannelSelectInit(
IN PVOID pDM_VOID
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
u1Byte i;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
if(pACS->bForceACSResult)
return;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectInit()=========> \n"));
pACS->CleanChannel_2G = 1;
pACS->CleanChannel_5G = 36;
for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i)
{
pACS->Channel_Info_2G[0][i] = 0;
pACS->Channel_Info_2G[1][i] = 0;
}
if(pDM_Odm->SupportICType & (ODM_IC_11AC_SERIES|ODM_RTL8192D))
{
for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i)
{
pACS->Channel_Info_5G[0][i] = 0;
pACS->Channel_Info_5G[1][i] = 0;
}
}
#endif
}
VOID
odm_AutoChannelSelectReset(
IN PVOID pDM_VOID
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
if(pACS->bForceACSResult)
return;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectReset()=========> \n"));
odm_AutoChannelSelectSetting(pDM_Odm,TRUE);// for 20ms measurement
Phydm_NHMCounterStatisticsReset(pDM_Odm);
#endif
}
VOID
odm_AutoChannelSelect(
IN PVOID pDM_VOID,
IN u1Byte Channel
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
u1Byte ChannelIDX = 0, SearchIDX = 0;
u2Byte MaxScore=0;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Return: SupportAbility ODM_BB_NHM_CNT is disabled\n"));
return;
}
if(pACS->bForceACSResult)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Force 2G clean channel = %d, 5G clean channel = %d\n",
pACS->CleanChannel_2G, pACS->CleanChannel_5G));
return;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel = %d=========> \n", Channel));
Phydm_GetNHMCounterStatistics(pDM_Odm);
odm_AutoChannelSelectSetting(pDM_Odm,FALSE);
if(Channel >=1 && Channel <=14)
{
ChannelIDX = Channel - 1;
pACS->Channel_Info_2G[1][ChannelIDX]++;
if(pACS->Channel_Info_2G[1][ChannelIDX] >= 2)
pACS->Channel_Info_2G[0][ChannelIDX] = (pACS->Channel_Info_2G[0][ChannelIDX] >> 1) +
(pACS->Channel_Info_2G[0][ChannelIDX] >> 2) + (pDM_Odm->NHM_cnt_0>>2);
else
pACS->Channel_Info_2G[0][ChannelIDX] = pDM_Odm->NHM_cnt_0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): NHM_cnt_0 = %d \n", pDM_Odm->NHM_cnt_0));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", ChannelIDX, pACS->Channel_Info_2G[0][ChannelIDX], ChannelIDX, pACS->Channel_Info_2G[1][ChannelIDX]));
for(SearchIDX = 0; SearchIDX < ODM_MAX_CHANNEL_2G; SearchIDX++)
{
if(pACS->Channel_Info_2G[1][SearchIDX] != 0)
{
if(pACS->Channel_Info_2G[0][SearchIDX] >= MaxScore)
{
MaxScore = pACS->Channel_Info_2G[0][SearchIDX];
pACS->CleanChannel_2G = SearchIDX+1;
}
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_AutoChannelSelect(): 2G: CleanChannel_2G = %d, MaxScore = %d \n",
pACS->CleanChannel_2G, MaxScore));
}
else if(Channel >= 36)
{
// Need to do
pACS->CleanChannel_5G = Channel;
}
#endif
}

61
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_ACS.h
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@ -1,61 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMACS_H__
#define __PHYDMACS_H__
#define ACS_VERSION "1.0"
#define ODM_MAX_CHANNEL_2G 14
#define ODM_MAX_CHANNEL_5G 24
typedef struct _ACS_
{
BOOLEAN bForceACSResult;
u1Byte CleanChannel_2G;
u1Byte CleanChannel_5G;
u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times
u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G];
}ACS, *PACS;
VOID
odm_AutoChannelSelectInit(
IN PVOID pDM_VOID
);
VOID
odm_AutoChannelSelectReset(
IN PVOID pDM_VOID
);
VOID
odm_AutoChannelSelect(
IN PVOID pDM_VOID,
IN u1Byte Channel
);
u1Byte
ODM_GetAutoChannelSelectResult(
IN PVOID pDM_VOID,
IN u1Byte Band
);
#endif

2850
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_AntDiv.c
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217
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_AntDiv.h
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@ -1,217 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
#define ANTDIV_VERSION "1.0"
#define ANT1_2G 0 // = ANT2_5G
#define ANT2_2G 1 // = ANT1_5G
//Antenna Diversty Control Type
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define TX_BY_REG 0
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#define ODM_RTL8881A 0 //Just for windows driver to jointly use ODM-driver
#endif
#define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
#define ODM_OLD_IC_ANTDIV_SUPPORT (ODM_RTL8723A|ODM_RTL8192C|ODM_RTL8192D)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_ANTDIV_2G BIT0
#define ODM_ANTDIV_5G BIT1
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define INIT_ANTDIV_TIMMER 0
#define CANCEL_ANTDIV_TIMMER 1
#define RELEASE_ANTDIV_TIMMER 2
VOID
ODM_StopAntennaSwitchDm(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_SetAntConfig(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antSetting // 0=A, 1=B, 2=C, ....
);
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
VOID ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm);
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_UpdateRxIdleAnt(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant
);
VOID
odm_AntselStatistics(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antsel_tr_mux,
IN u4Byte MacId,
IN u4Byte RxPWDBAll
);
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
ODM_SW_AntDiv_Callback(
IN PRT_TIMER pTimer
);
VOID
ODM_SW_AntDiv_WorkitemCallback(
IN PVOID pContext
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
VOID
ODM_SW_AntDiv_Callback(void *FunctionContext);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_S0S1_SwAntDivByCtrlFrame(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Step
);
VOID
odm_AntselStatisticsOfCtrlFrame(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antsel_tr_mux,
IN u4Byte RxPWDBAll
);
VOID
odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
IN PDM_ODM_T pDM_Odm,
IN PODM_PHY_INFO_T pPhyInfo,
IN PODM_PACKET_INFO_T pPktinfo
);
#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#endif
#if(RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
VOID
odm_FastAntTraining(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingCallback(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingWorkItemCallback(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif
VOID
ODM_AntDivInit(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_AntDivReset(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_AntDiv(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_Process_RSSIForAntDiv(
IN OUT PDM_ODM_T pDM_Odm,
IN PODM_PHY_INFO_T pPhyInfo,
IN PODM_PACKET_INFO_T pPktinfo
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
ODM_SetTxAntByTxInfo(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
);
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo(
//IN PDM_ODM_T pDM_Odm,
struct rtl8192cd_priv *priv,
struct tx_desc *pdesc,
struct tx_insn *txcfg,
unsigned short aid
);
#endif
VOID
ODM_AntDiv_Config(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_UpdateRxIdleAnt_8723B(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant,
IN u4Byte DefaultAnt,
IN u4Byte OptionalAnt
);
VOID
ODM_AntDivTimers(
IN PDM_ODM_T pDM_Odm,
IN u1Byte state
);
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
#endif //#ifndef __ODMANTDIV_H__

1915
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_EdcaTurboCheck.c
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File diff suppressed because it is too large Load Diff

2362
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_HWConfig.c
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File diff suppressed because it is too large Load Diff

237
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_HWConfig.h
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@ -1,237 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
/*--------------------------Define -------------------------------------------*/
//#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
#define AGC_DIFF_CONFIG(ic, band) do {\
if (pDM_Odm->bIsMPChip)\
AGC_DIFF_CONFIG_MP(ic,band);\
else\
AGC_DIFF_CONFIG_TC(ic,band);\
} while(0)
//============================================================
// structure and define
//============================================================
typedef struct _Phy_Rx_AGC_Info
{
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte gain:7,trsw:1;
#else
u1Byte trsw:1,gain:7;
#endif
} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
typedef struct _Phy_Status_Rpt_8192cd
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_corr[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_rpt_b_ofdm_cfosho_b;
u1Byte rsvd_1;//ch_corr_msb;
u1Byte noise_power_db_msb;
s1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte noise_power_db_lsb;
u1Byte rsvd_2[3];
u1Byte stream_csi[2];
u1Byte stream_target_csi[2];
s1Byte sig_evm;
u1Byte rsvd_3;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u1Byte sgi_en:1;
u1Byte rxsc:2;
u1Byte idle_long:1;
u1Byte r_ant_train_en:1;
u1Byte ant_sel_b:1;
u1Byte ant_sel:1;
#else // _BIG_ENDIAN_
u1Byte ant_sel:1;
u1Byte ant_sel_b:1;
u1Byte r_ant_train_en:1;
u1Byte idle_long:1;
u1Byte rxsc:2;
u1Byte sgi_en:1;
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
#endif
} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
typedef struct _Phy_Status_Rpt_8812
{
#if 0
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_num[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_bb_pwr_ofdm_cfosho_b;
u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
u1Byte rsvd_1;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte rsvd_2[2];
u1Byte stream_snr[2];
u1Byte stream_csi[2];
u1Byte rsvd_3[2];
s1Byte sig_evm;
u1Byte rsvd_4;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte rsvd_5:2;
#else // _BIG_ENDIAN_
u1Byte rsvd_5:2;
u1Byte antidx_antb:3;
u1Byte antidx_anta:3;
#endif
#endif
//2012.05.24 LukeLee: This structure should take big/little endian in consideration later.....
//DWORD 0
u1Byte gain_trsw[2];
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u2Byte chl_num:10;
u2Byte sub_chnl:4;
u2Byte r_RFMOD:2;
#else // _BIG_ENDIAN_
u2Byte r_RFMOD:2;
u2Byte sub_chnl:4;
u2Byte chl_num:10;
#endif
//DWORD 1
u1Byte pwdb_all;
u1Byte cfosho[4]; // DW 1 byte 1 DW 2 byte 0
//DWORD 2
s1Byte cfotail[4]; // DW 2 byte 1 DW 3 byte 0
//DWORD 3
s1Byte rxevm[2]; // DW 3 byte 1 DW 3 byte 2
s1Byte rxsnr[2]; // DW 3 byte 3 DW 4 byte 0
//DWORD 4
u1Byte PCTS_MSK_RPT[2];
u1Byte pdsnr[2]; // DW 4 byte 3 DW 5 Byte 0
//DWORD 5
u1Byte csi_current[2];
u1Byte rx_gain_c;
//DWORD 6
u1Byte rx_gain_d;
s1Byte sigevm;
u1Byte resvd_0;
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte resvd_1:2;
} PHY_STATUS_RPT_8812_T,*PPHY_STATUS_RPT_8812_T;
VOID
odm_Init_RSSIForDM(
IN OUT PDM_ODM_T pDM_Odm
);
VOID
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
);
VOID
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN BOOLEAN bPacketMatchBSSID,
IN BOOLEAN bPacketToSelf,
IN BOOLEAN bPacketBeacon
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP))
HAL_STATUS
ODM_ConfigRFWithTxPwrTrackHeaderFile(
IN PDM_ODM_T pDM_Odm
);
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_Config_Type ConfigType,
IN ODM_RF_RADIO_PATH_E eRFPath
);
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
);
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
);
HAL_STATUS
ODM_ConfigFWWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_FW_Config_Type ConfigType,
OUT u1Byte *pFirmware,
OUT u4Byte *pSize
);
u4Byte
ODM_GetHWImgVersion(
IN PDM_ODM_T pDM_Odm
);
s4Byte
odm_SignalScaleMapping(
IN OUT PDM_ODM_T pDM_Odm,
IN s4Byte CurrSig
);
#endif
#endif

49
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_NoiseMonitor.h
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@ -1,49 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
*****************************************************************************/
#ifndef __ODMNOISEMONITOR_H__
#define __ODMNOISEMONITOR_H__
#define ODM_MAX_CHANNEL_NUM 38//14+24
struct noise_level
{
//u1Byte value_a, value_b;
u1Byte value[MAX_RF_PATH];
//s1Byte sval_a, sval_b;
s1Byte sval[MAX_RF_PATH];
//s4Byte noise_a=0, noise_b=0,sum_a=0, sum_b=0;
//s4Byte noise[ODM_RF_PATH_MAX];
s4Byte sum[MAX_RF_PATH];
//u1Byte valid_cnt_a=0, valid_cnt_b=0,
u1Byte valid[MAX_RF_PATH];
u1Byte valid_cnt[MAX_RF_PATH];
};
typedef struct _ODM_NOISE_MONITOR_
{
s1Byte noise[MAX_RF_PATH];
s2Byte noise_all;
}ODM_NOISE_MONITOR;
s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time);
#endif

1595
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_RaInfo.c
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167
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_RaInfo.h
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@ -1,167 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMRAINFO_H__
#define __PHYDMRAINFO_H__
#define RAINFO_VERSION "1.0"
#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit
#define DM_RATR_STA_INIT 0
#define DM_RATR_STA_HIGH 1
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#define DM_RATR_STA_ULTRA_LOW 4
#endif
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
typedef struct _Rate_Adaptive_Table_{
u1Byte firstconnect;
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
BOOLEAN PT_collision_pre;
#endif
}RA_T, *pRA_T;
#endif
typedef struct _ODM_RATE_ADAPTIVE
{
u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC
BOOLEAN bLowerRtsRate;
#endif
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
u1Byte RtsThres;
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
BOOLEAN bUseLdpc;
#else
u1Byte UltraLowRSSIThresh;
u4Byte LastRATR; // RATR Register Content
#endif
} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
VOID
odm_RSSIMonitorInit(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorCheck(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
VOID
odm_RSSIDumpToRegister(
IN PVOID pDM_VOID
);
#endif
VOID
odm_RSSIMonitorCheckMP(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorCheckCE(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorCheckAP(
IN PVOID pDM_VOID
);
VOID
odm_RateAdaptiveMaskInit(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMask(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMaskMP(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMaskCE(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMaskAPADSL(
IN PVOID pDM_VOID
);
BOOLEAN
ODM_RAStateCheck(
IN PVOID pDM_VOID,
IN s4Byte RSSI,
IN BOOLEAN bForceUpdate,
OUT pu1Byte pRATRState
);
VOID
odm_RefreshBasicRateMask(
IN PVOID pDM_VOID
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
ODM_DynamicARFBSelect(
IN PVOID pDM_VOID,
IN u1Byte rate,
IN BOOLEAN Collision_State
);
VOID
ODM_RateAdaptiveStateApInit(
IN PVOID PADAPTER_VOID,
IN PRT_WLAN_STA pEntry
);
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
u4Byte
ODM_Get_Rate_Bitmap(
IN PVOID pDM_VOID,
IN u4Byte macid,
IN u4Byte ra_mask,
IN u1Byte rssi_level
);
#endif
#endif //#ifndef __ODMRAINFO_H__

873
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_debug.c
View File

@ -1,873 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
PHYDM_InitDebugSetting(
IN PDM_ODM_T pDM_Odm
)
{
pDM_Odm->DebugLevel = ODM_DBG_TRACE;
pDM_Odm->DebugComponents =
\
#if DBG
//BB Functions
// ODM_COMP_DIG |
// ODM_COMP_RA_MASK |
// ODM_COMP_DYNAMIC_TXPWR |
// ODM_COMP_FA_CNT |
// ODM_COMP_RSSI_MONITOR |
// ODM_COMP_CCK_PD |
// ODM_COMP_ANT_DIV |
// ODM_COMP_PWR_SAVE |
// ODM_COMP_PWR_TRAIN |
// ODM_COMP_RATE_ADAPTIVE |
// ODM_COMP_PATH_DIV |
// ODM_COMP_DYNAMIC_PRICCA |
// ODM_COMP_RXHP |
// ODM_COMP_MP |
// ODM_COMP_CFO_TRACKING |
// ODM_COMP_ACS |
// PHYDM_COMP_ADAPTIVITY |
//MAC Functions
// ODM_COMP_EDCA_TURBO |
// ODM_COMP_EARLY_MODE |
//RF Functions
// ODM_COMP_TX_PWR_TRACK |
// ODM_COMP_RX_GAIN_TRACK |
// ODM_COMP_CALIBRATION |
//Common
// ODM_COMP_COMMON |
// ODM_COMP_INIT |
// ODM_COMP_PSD |
#endif
0;
}
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
static u1Byte BbDbgBuf[BB_TMP_BUF_SIZE];
VOID
phydm_BB_Debug_Info(IN PDM_ODM_T pDM_Odm)
{
u1Byte RX_HT_BW, RX_VHT_BW, RXSC, RX_HT, RX_BW;
static u1Byte vRX_BW ;
u4Byte value32, value32_1, value32_2, value32_3;
s4Byte SFO_A, SFO_B, SFO_C, SFO_D;
s4Byte LFO_A, LFO_B, LFO_C, LFO_D;
static u1Byte MCSS,Tail,Parity,rsv,vrsv,idx,smooth,htsound,agg,stbc,vstbc,fec,fecext,sgi,sgiext,htltf,vgid,vNsts,vtxops,vrsv2,vbrsv,bf,vbcrc;
static u2Byte HLength,htcrc8,Length;
static u2Byte vpaid;
static u2Byte vLength,vhtcrc8,vMCSS,vTail,vbTail;
static u1Byte HMCSS,HRX_BW;
u1Byte pwDB;
s1Byte RXEVM_0, RXEVM_1, RXEVM_2 ;
u1Byte RF_gain_pathA, RF_gain_pathB, RF_gain_pathC, RF_gain_pathD;
u1Byte RX_SNR_pathA, RX_SNR_pathB, RX_SNR_pathC, RX_SNR_pathD;
s4Byte sig_power;
const char *RXHT_table[] = {"legacy", "HT", "VHT"};
const char *BW_table[] = {"20M", "40M", "80M"};
const char *RXSC_table[] = {"duplicate/full bw", "usc20-1", "lsc20-1", "usc20-2", "lsc20-2", "usc40", "lsc40"};
const char *L_rate[]={"6M","9M","12M","18M","24M","36M","48M","54M"};
/*
const double evm_comp_20M = 0.579919469776867; //10*log10(64.0/56.0)
const double evm_comp_40M = 0.503051183113957; //10*log10(128.0/114.0)
const double evm_comp_80M = 0.244245993314183; //10*log10(256.0/242.0)
const double evm_comp_160M = 0.244245993314183; //10*log10(512.0/484.0)
*/
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
return;
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s \n", "BB Report Info");
DCMD_Printf(BbDbgBuf);
//BW & Mode Detection
///////////////////////////////////////////////////////
value32 = ODM_GetBBReg(pDM_Odm, 0xf80 ,bMaskDWord);
value32_2 =value32;
RX_HT_BW = (u1Byte)(value32&0x1) ;
RX_VHT_BW = (u1Byte)((value32>>1)&0x3);
RXSC = (u1Byte)(value32&0x78);
value32_1= (value32&0x180)>>7;
RX_HT = (u1Byte)(value32_1);
/*
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "F80", value32_2);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "RX_HT_BW", RX_HT_BW);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "RX_VHT_BW", RX_VHT_BW);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "RX_SC", RXSC);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "RX_HT", RX_HT);
DCMD_Printf(BbDbgBuf);
*/
//rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n RX_HT:%s ", RXHT_table[RX_HT]);
//DCMD_Printf(BbDbgBuf);
RX_BW = 0;
if(RX_HT == 2)
{
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n Mode: VHT Mode");
DCMD_Printf(BbDbgBuf);
if(RX_VHT_BW==0)
{
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, " BW=20M");
DCMD_Printf(BbDbgBuf);
}
else if(RX_VHT_BW==1)
{
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, " BW=40M");
DCMD_Printf(BbDbgBuf);
}
else
{
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, " BW=80M");
DCMD_Printf(BbDbgBuf);
}
RX_BW = RX_VHT_BW;
}
else if(RX_HT == 1)
{
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n Mode: HT Mode");
DCMD_Printf(BbDbgBuf);
if(RX_HT_BW==0)
{
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, " BW=20M");
DCMD_Printf(BbDbgBuf);
}
else if(RX_HT_BW==1)
{
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, " BW=40M");
DCMD_Printf(BbDbgBuf);
}
RX_BW = RX_HT_BW;
}
else
{
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n Mode: Legeacy Mode");
DCMD_Printf(BbDbgBuf);
}
if(RX_HT !=0)
{
if(RXSC==0)
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n duplicate/full bw");
else if(RXSC==1)
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n usc20-1");
else if(RXSC==2)
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n lsc20-1");
else if(RXSC==3)
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n usc20-2");
else if(RXSC==4)
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n lsc20-2");
else if(RXSC==9)
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n usc40");
else if(RXSC==10)
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n lsc40");
DCMD_Printf(BbDbgBuf);
}
/*
if(RX_HT == 2){
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, " BW:%s", BW_table[RX_VHT_BW]);
RX_BW = RX_VHT_BW;
}
else if(RX_HT == 1){
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, " BW:%s", BW_table[RX_HT_BW]);
RX_BW = RX_HT_BW;
}
else
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "");
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, " RXSC:%s", RXSC_table[RXSC]);
DCMD_Printf(BbDbgBuf);
*/
///////////////////////////////////////////////////////
// rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "dB Conversion: 10log(65)", ODM_PWdB_Conversion(65,10,0));
// DCMD_Printf(BbDbgBuf);
// RX signal power and AGC related info
///////////////////////////////////////////////////////
value32 = ODM_GetBBReg(pDM_Odm, 0xF90 ,bMaskDWord);
pwDB = (u1Byte) ((value32 & bMaskByte1) >> 8);
pwDB=pwDB>>1;
sig_power = -110+pwDB;
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power);
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xd14 ,bMaskDWord);
RX_SNR_pathA = (u1Byte)(value32&0xFF)>>1;
RF_gain_pathA = (s1Byte) ((value32 & bMaskByte1) >> 8);
RF_gain_pathA *=2;
value32 = ODM_GetBBReg(pDM_Odm, 0xd54 ,bMaskDWord);
RX_SNR_pathB = (u1Byte)(value32&0xFF)>>1;
RF_gain_pathB = (s1Byte) ((value32 & bMaskByte1) >> 8);
RF_gain_pathB *=2;
value32 = ODM_GetBBReg(pDM_Odm, 0xd94 ,bMaskDWord);
RX_SNR_pathC = (u1Byte)(value32&0xFF)>>1;
RF_gain_pathC = (s1Byte) ((value32 & bMaskByte1) >> 8);
RF_gain_pathC *=2;
value32 = ODM_GetBBReg(pDM_Odm, 0xdd4 ,bMaskDWord);
RX_SNR_pathD = (u1Byte)(value32&0xFF)>>1;
RF_gain_pathD = (s1Byte) ((value32 & bMaskByte1) >> 8);
RF_gain_pathD *=2;
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", RF_gain_pathA, RF_gain_pathA, RF_gain_pathC, RF_gain_pathD);
DCMD_Printf(BbDbgBuf);
///////////////////////////////////////////////////////
// RX Counter related info
///////////////////////////////////////////////////////
value32 = ODM_GetBBReg(pDM_Odm, 0xF08 ,bMaskDWord);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "OFDM CCA Counter", ((value32&0xFFFF0000)>>16));
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xFD0 ,bMaskDWord);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "OFDM SBD Fail Counter", value32&0xFFFF);
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xFC4 ,bMaskDWord);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail Counter", value32&0xFFFF, ((value32&0xFFFF0000)>>16));
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xFCC ,bMaskDWord);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "CCK CCA Counter", value32&0xFFFF);
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xFBC ,bMaskDWord);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d", "LSIG (\"Parity Fail\"/\"Rate Illegal\") Counter", value32&0xFFFF, ((value32&0xFFFF0000)>>16));
DCMD_Printf(BbDbgBuf);
value32_1 = ODM_GetBBReg(pDM_Odm, 0xFC8 ,bMaskDWord);
value32_2 = ODM_GetBBReg(pDM_Odm, 0xFC0 ,bMaskDWord);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT counter", ((value32_2&0xFFFF0000)>>16), value32_1&0xFFFF);
DCMD_Printf(BbDbgBuf);
///////////////////////////////////////////////////////
// PostFFT related info
///////////////////////////////////////////////////////
value32 = ODM_GetBBReg(pDM_Odm, 0xF8c ,bMaskDWord);
RXEVM_0 = (s1Byte) ((value32 & bMaskByte2) >> 16);
RXEVM_0 /=2;
if(RXEVM_0 < -63)
RXEVM_0=0;
DCMD_Printf(BbDbgBuf);
RXEVM_1 = (s1Byte) ((value32 & bMaskByte3) >> 24);
RXEVM_1 /=2;
value32 = ODM_GetBBReg(pDM_Odm, 0xF88 ,bMaskDWord);
RXEVM_2 = (s1Byte) ((value32 & bMaskByte2) >> 16);
RXEVM_2 /=2;
if(RXEVM_1 < -63)
RXEVM_1=0;
if(RXEVM_2 < -63)
RXEVM_2=0;
/*
if(RX_BW == 0){
RXEVM_0 -= evm_comp_20M;
RXEVM_1 -= evm_comp_20M;
RXEVM_2 -= evm_comp_20M;
}
else if(RX_BW == 1){
RXEVM_0 -= evm_comp_40M;
RXEVM_1 -= evm_comp_40M;
RXEVM_2 -= evm_comp_40M;
}
else if (RX_BW == 2){
RXEVM_0 -= evm_comp_80M;
RXEVM_1 -= evm_comp_80M;
RXEVM_2 -= evm_comp_80M;
}
*/
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", RXEVM_0, RXEVM_1, RXEVM_2);
DCMD_Printf(BbDbgBuf);
// value32 = ODM_GetBBReg(pDM_Odm, 0xD14 ,bMaskDWord);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", RX_SNR_pathA, RX_SNR_pathB, RX_SNR_pathC, RX_SNR_pathD);
DCMD_Printf(BbDbgBuf);
// rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "B_RXSNR", (value32&0xFF00)>>9);
// DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xF8C ,bMaskDWord);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32&0xFFFF, ((value32&0xFFFF0000)>>16));
DCMD_Printf(BbDbgBuf);
///////////////////////////////////////////////////////
//BW & Mode Detection
//Reset Page F Counter
ODM_SetBBReg(pDM_Odm, 0xB58 ,BIT0, 1);
ODM_SetBBReg(pDM_Odm, 0xB58 ,BIT0, 0);
//CFO Report Info
//Short CFO
value32 = ODM_GetBBReg(pDM_Odm, 0xd0c ,bMaskDWord);
value32_1 = ODM_GetBBReg(pDM_Odm, 0xd4c ,bMaskDWord);
value32_2 = ODM_GetBBReg(pDM_Odm, 0xd8c ,bMaskDWord);
value32_3 = ODM_GetBBReg(pDM_Odm, 0xdcc ,bMaskDWord);
SFO_A=(s4Byte)(value32&bMask12Bits);
SFO_B=(s4Byte)(value32_1&bMask12Bits);
SFO_C=(s4Byte)(value32_2&bMask12Bits);
SFO_D=(s4Byte)(value32_3&bMask12Bits);
LFO_A=(s4Byte)(value32>>16);
LFO_B=(s4Byte)(value32_1>>16);
LFO_C=(s4Byte)(value32_2>>16);
LFO_D=(s4Byte)(value32_3>>16);
//SFO 2's to dec
if(SFO_A >2047)
{
SFO_A=SFO_A-4096;
}
SFO_A=(SFO_A*312500)/2048;
if(SFO_B >2047)
{
SFO_B=SFO_B-4096;
}
SFO_B=(SFO_B*312500)/2048;
if(SFO_C >2047)
{
SFO_C=SFO_C-4096;
}
SFO_C=(SFO_C*312500)/2048;
if(SFO_D >2047)
{
SFO_D=SFO_D-4096;
}
SFO_D=(SFO_D*312500)/2048;
//LFO 2's to dec
if(LFO_A >4095)
{
LFO_A=LFO_A-8192;
}
if(LFO_B >4095)
{
LFO_B=LFO_B-8192;
}
if(LFO_C>4095)
{
LFO_C=LFO_C-8192;
}
if(LFO_D >4095)
{
LFO_D=LFO_D-8192;
}
LFO_A=LFO_A*312500/4096;
LFO_B=LFO_B*312500/4096;
LFO_C=LFO_C*312500/4096;
LFO_D=LFO_D*312500/4096;
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "CFO Report Info");
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d/ %d/ %d", " Short CFO(Hz) <A/B/C/D>", SFO_A,SFO_B,SFO_C,SFO_D);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d/ %d/ %d", " Long CFO(Hz) <A/B/C/D>", LFO_A,LFO_B,LFO_C,LFO_D);
DCMD_Printf(BbDbgBuf);
//SCFO
value32 = ODM_GetBBReg(pDM_Odm, 0xd10 ,bMaskDWord);
value32_1 = ODM_GetBBReg(pDM_Odm, 0xd50 ,bMaskDWord);
value32_2 = ODM_GetBBReg(pDM_Odm, 0xd90 ,bMaskDWord);
value32_3 = ODM_GetBBReg(pDM_Odm, 0xdd0 ,bMaskDWord);
SFO_A=(s4Byte)(value32&0x7ff);
SFO_B=(s4Byte)(value32_1&0x7ff);
SFO_C=(s4Byte)(value32_2&0x7ff);
SFO_D=(s4Byte)(value32_3&0x7ff);
if(SFO_A >1023)
{
SFO_A=SFO_A-2048;
}
if(SFO_B >2047)
{
SFO_B=SFO_B-4096;
}
if(SFO_C >2047)
{
SFO_C=SFO_C-4096;
}
if(SFO_D >2047)
{
SFO_D=SFO_D-4096;
}
SFO_A=SFO_A*312500/1024;
SFO_B=SFO_B*312500/1024;
SFO_C=SFO_C*312500/1024;
SFO_D=SFO_D*312500/1024;
LFO_A=(s4Byte)(value32>>16);
LFO_B=(s4Byte)(value32_1>>16);
LFO_C=(s4Byte)(value32_2>>16);
LFO_D=(s4Byte)(value32_3>>16);
if(LFO_A >4095)
{
LFO_A=LFO_A-8192;
}
if(LFO_B >4095)
{
LFO_B=LFO_B-8192;
}
if(LFO_C>4095)
{
LFO_C=LFO_C-8192;
}
if(LFO_D >4095)
{
LFO_D=LFO_D-8192;
}
LFO_A=LFO_A*312500/4096;
LFO_B=LFO_B*312500/4096;
LFO_C=LFO_C*312500/4096;
LFO_D=LFO_D*312500/4096;
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d/ %d/ %d", " Value SCFO(Hz) <A/B/C/D>", SFO_A,SFO_B,SFO_C,SFO_D);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d/ %d/ %d", " ACQ CFO(Hz) <A/B/C/D>", LFO_A,LFO_B,LFO_C,LFO_D);
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xd14 ,bMaskDWord);
value32_1 = ODM_GetBBReg(pDM_Odm, 0xd54 ,bMaskDWord);
value32_2 = ODM_GetBBReg(pDM_Odm, 0xd94 ,bMaskDWord);
value32_3 = ODM_GetBBReg(pDM_Odm, 0xdd4 ,bMaskDWord);
LFO_A=(s4Byte)(value32>>16);
LFO_B=(s4Byte)(value32_1>>16);
LFO_C=(s4Byte)(value32_2>>16);
LFO_D=(s4Byte)(value32_3>>16);
if(LFO_A >4095)
{
LFO_A=LFO_A-8192;
}
if(LFO_B >4095)
{
LFO_B=LFO_B-8192;
}
if(LFO_C>4095)
{
LFO_C=LFO_C-8192;
}
if(LFO_D >4095)
{
LFO_D=LFO_D-8192;
}
LFO_A=LFO_A*312500/4096;
LFO_B=LFO_B*312500/4096;
LFO_C=LFO_C*312500/4096;
LFO_D=LFO_D*312500/4096;
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d/ %d/ %d", " End CFO(Hz) <A/B/C/D>", LFO_A,LFO_B,LFO_C,LFO_D);
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xf20 ,bMaskDWord); //L SIG
Tail=(u1Byte)((value32&0xfc0000)>>16);
Parity = (u1Byte)((value32&0x20000)>>16);
Length =(u2Byte)((value32&0x1ffe00)>>8);
rsv = (u1Byte)(value32&0x10);
MCSS=(u1Byte)(value32&0x0f);
switch(MCSS)
{
case 0x0b:
idx=0;
break;
case 0x0f:
idx=1;
break;
case 0x0a:
idx=2;
break;
case 0x0e:
idx=3;
break;
case 0x09:
idx=4;
break;
case 0x08:
idx=5;
break;
case 0x0c:
idx=6;
break;
default:
idx=6;
break;
}
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "L-SIG");
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n Rate:%s", L_rate[idx]);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x/ %x /%x", " Rsv/Length/Parity",rsv,RX_BW,Length);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "HT-SIG1");
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xf2c ,bMaskDWord); //HT SIG
if(RX_HT == 1)
{
HMCSS=(u1Byte)(value32&0x7F);
HRX_BW = (u1Byte)(value32&0x80);
HLength =(u2Byte)((value32>>8)&0xffff);
}
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x", " MCS/BW/Length",HMCSS,HRX_BW,HLength);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "HT-SIG2");
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xf30 ,bMaskDWord); //HT SIG
if(RX_HT == 1)
{
smooth = (u1Byte)(value32&0x01);
htsound = (u1Byte)(value32&0x02);
rsv=(u1Byte)(value32&0x04);
agg =(u1Byte)(value32&0x08);
stbc =(u1Byte)(value32&0x30);
fec=(u1Byte)(value32&0x40);
sgi=(u1Byte)(value32&0x80);
htltf=(u1Byte)((value32&0x300)>>8);
htcrc8=(u2Byte)((value32&0x3fc00)>>8);
Tail=(u1Byte)((value32&0xfc0000)>>16);
}
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x/ %x/ %x/ %x", " Smooth/NoSound/Rsv/Aggregate/STBC/LDPC",smooth,htsound,rsv,agg,stbc,fec);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x/ %x", " SGI/E-HT-LTFs/CRC/Tail",sgi,htltf,htcrc8,Tail);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "VHT-SIG-A1");
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xf2c ,bMaskDWord); //VHT SIG A1
if(RX_HT == 2)
{
//value32 = ODM_GetBBReg(pDM_Odm, 0xf2c ,bMaskDWord); //VHT SIG A1
vRX_BW=(u1Byte)(value32&0x03);
vrsv=(u1Byte)(value32&0x04);
vstbc =(u1Byte)(value32&0x08);
vgid = (u1Byte)((value32&0x3f0)>>4);
vNsts = (u1Byte)(((value32&0x1c00)>>8)+1);
vpaid = (u2Byte)(value32&0x3fe);
vtxops =(u1Byte)((value32&0x400000)>>20);
vrsv2 = (u1Byte)((value32&0x800000)>>20);
}
//rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x", "F2C", value32);
//DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x/ %x/ %x/ %x /%x /%x", " BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2",vRX_BW,vrsv,vstbc,vgid,vNsts,vpaid,vtxops,vrsv2);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "VHT-SIG-A2");
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xf30 ,bMaskDWord); //VHT SIG
if(RX_HT == 2)
{
//value32 = ODM_GetBBReg(pDM_Odm, 0xf30 ,bMaskDWord); //VHT SIG
//sgi=(u1Byte)(value32&0x01);
sgiext =(u1Byte)(value32&0x03);
//fec = (u1Byte)(value32&0x04);
fecext = (u1Byte)(value32&0x0C);
vMCSS =(u1Byte)(value32&0xf0);
bf = (u1Byte)((value32&0x100)>>8);
vrsv =(u1Byte)((value32&0x200)>>8);
vhtcrc8=(u2Byte)((value32&0x3fc00)>>8);
vTail=(u1Byte)((value32&0xfc0000)>>16);
}
//rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x", "F30", value32);
//DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x/ %x/ %x/ %x/ %x", " SGI/FEC/MCS/BF/Rsv/CRC/Tail",sgiext,fecext,vMCSS,bf,vrsv,vhtcrc8,vTail);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "VHT-SIG-B");
DCMD_Printf(BbDbgBuf);
value32 = ODM_GetBBReg(pDM_Odm, 0xf34 ,bMaskDWord); //VHT SIG
{
vLength=(u2Byte)(value32&0x1fffff);
vbrsv = (u1Byte)((value32&0x600000)>>20);
vbTail =(u2Byte)((value32&0x1f800000)>>20);
vbcrc = (u1Byte)((value32&0x80000000)>>28);
}
//rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x", "F34", value32);
//DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x/ %x/", " Length/Rsv/Tail/CRC",vLength,vbrsv,vbTail,vbcrc);
DCMD_Printf(BbDbgBuf);
}
VOID phydm_BasicProfile(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER Adapter = pDM_Odm->Adapter;
char* Cut = NULL;
char* ICType = NULL;
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n%-35s", "% Basic Profile %");
DCMD_Printf(BbDbgBuf);
if(pDM_Odm->SupportICType == ODM_RTL8192C)
ICType = "RTL8192C";
else if(pDM_Odm->SupportICType == ODM_RTL8192D)
ICType = "RTL8192D";
else if(pDM_Odm->SupportICType == ODM_RTL8723A)
ICType = "RTL8723A";
else if(pDM_Odm->SupportICType == ODM_RTL8188E)
ICType = "RTL8188E";
else if(pDM_Odm->SupportICType == ODM_RTL8812)
ICType = "RTL8812A";
else if(pDM_Odm->SupportICType == ODM_RTL8821)
ICType = "RTL8821A";
else if(pDM_Odm->SupportICType == ODM_RTL8192E)
ICType = "RTL8192E";
else if(pDM_Odm->SupportICType == ODM_RTL8723B)
ICType = "RTL8723B";
else if(pDM_Odm->SupportICType == ODM_RTL8814A)
ICType = "RTL8814A";
else if(pDM_Odm->SupportICType == ODM_RTL8881A)
ICType = "RTL8881A";
else if(pDM_Odm->SupportICType == ODM_RTL8821B)
ICType = "RTL8821B";
else if(pDM_Odm->SupportICType == ODM_RTL8822B)
ICType = "RTL8822B";
else if(pDM_Odm->SupportICType == ODM_RTL8703B)
ICType = "RTL8703B";
else if(pDM_Odm->SupportICType == ODM_RTL8195A)
ICType = "RTL8195A";
else if(pDM_Odm->SupportICType == ODM_RTL8188F)
ICType = "RTL8188F";
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s (MP Chip: %s)","IC Type", ICType, pDM_Odm->bIsMPChip?"Yes":"No");
DCMD_Printf(BbDbgBuf);
if(pDM_Odm->CutVersion==ODM_CUT_A)
Cut = "A";
else if(pDM_Odm->CutVersion==ODM_CUT_B)
Cut = "B";
else if(pDM_Odm->CutVersion==ODM_CUT_C)
Cut = "C";
else if(pDM_Odm->CutVersion==ODM_CUT_D)
Cut = "D";
else if(pDM_Odm->CutVersion==ODM_CUT_E)
Cut = "E";
else if(pDM_Odm->CutVersion==ODM_CUT_F)
Cut = "F";
else if(pDM_Odm->CutVersion==ODM_CUT_I)
Cut = "I";
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","Cut Version", Cut);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %d","PHY Parameter Version", ODM_GetHWImgVersion(pDM_Odm));
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %d (Subversion: %d)","FW Version", Adapter->MgntInfo.FirmwareVersion, Adapter->MgntInfo.FirmwareSubVersion);
DCMD_Printf(BbDbgBuf);
//1 PHY DM Version List
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n%-35s","% PHYDM Version %");
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","Adaptivity", ADAPTIVITY_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","DIG", DIG_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","Dynamic BB PowerSaving", DYNAMIC_BBPWRSAV_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","CFO Tracking", CFO_TRACKING_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","Antenna Diversity", ANTDIV_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","Power Tracking", POWRTRACKING_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","Dynamic TxPower", DYNAMIC_TXPWR_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","RA Info", RAINFO_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","Antenna Detection", ANTDECT_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","Auto Channel Selection", ACS_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","EDCA Turbo", EDCATURBO_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","Path Diversity", PATHDIV_VERSION);
DCMD_Printf(BbDbgBuf);
rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s: %s","RxHP", RXHP_VERSION);
DCMD_Printf(BbDbgBuf);
}
#endif
VOID
phydm_BasicDbgMessage
(
IN PVOID pDM_VOID
)
{
#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT);
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_BasicDbgMsg==>\n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked = %d, RSSI_Min = %d, CurrentIGI = 0x%x \n",
pDM_Odm->bLinked, pDM_Odm->RSSI_Min, pDM_DigTable->CurIGValue) );
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("Cnt_Cck_fail = %d, Cnt_Ofdm_fail = %d, Total False Alarm = %d\n",
FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RxRate = 0x%x, RSSI_A = %d, RSSI_B = %d\n",
pDM_Odm->RxRate, pDM_Odm->RSSI_A, pDM_Odm->RSSI_B));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_C = %d, RSSI_D = %d\n", pDM_Odm->RSSI_C, pDM_Odm->RSSI_D));
#endif
}
#if( DM_ODM_SUPPORT_TYPE & ODM_CE)
struct _PHYDM_COMMAND {
char name[16];
u1Byte id;
};
enum PHYDM_CMD_ID {
PHYDM_ANTDIV,
};
struct _PHYDM_COMMAND phy_dm_ary[] = {
{"antdiv", PHYDM_ANTDIV},
};
s4Byte
PhyDM_Cmd(
IN PDM_ODM_T pDM_Odm,
IN char *input,
IN u4Byte in_len,
IN u1Byte flag,
OUT char *output,
IN u4Byte out_len
)
{
u4Byte used = 0;
if (flag == 0) {
if (out_len > used)
used += snprintf(output+used, out_len-used, "GET, nothing to print\n");
} else {
char *token;
u1Byte id = 0;
int var = 0;
token = strsep(&input, ", ");
if (token) {
int n, i;
n = sizeof(phy_dm_ary)/sizeof(struct _PHYDM_COMMAND);
for (i = 0; i < n; i++) {
if (strcmp(phy_dm_ary[i].name, token) == 0) {
id = phy_dm_ary[i].id;
break;
}
}
if (i == n) {
if (out_len > used)
used += snprintf(output+used, out_len-used, "SET, command not found!\n");
goto exit;
}
}
switch (id) {
case PHYDM_ANTDIV:
token = strsep(&input, ", ");
sscanf(token, "%d", &var);
if (out_len > used)
used += snprintf(output+used, out_len-used, "SET, old antdiv_select=%d\n", pDM_Odm->antdiv_select);
pDM_Odm->antdiv_select = var;
if (out_len > used)
used += snprintf(output+used, out_len-used, "SET, new antdiv_select=%d\n", pDM_Odm->antdiv_select);
break;
default:
if (out_len > used)
used += snprintf(output+used, out_len-used, "SET, unknown command!\n");
break;
}
}
exit:
return 0;
}
#endif

296
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_precomp.h
View File

@ -1,296 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_PRECOMP_H__
#define __ODM_PRECOMP_H__
#include "phydm_types.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting.
#else
#define TEST_FALG___ 1
#endif
//2 Config Flags and Structs - defined by each ODM Type
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "../8192cd_cfg.h"
#include "../odm_inc.h"
#include "../8192cd.h"
#include "../8192cd_util.h"
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#ifdef AP_BUILD_WORKAROUND
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
// Flags
#include "../8192cd_cfg.h" // OUTSRC needs ADSL config flags.
#include "../odm_inc.h" // OUTSRC needs some extra flags.
// Data Structure
#include "../common_types.h" // OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0.
#include "../8192cd.h" // OUTSRC needs basic ADSL struct definition.
#include "../8192cd_util.h" // OUTSRC needs basic I/O function.
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#ifdef ADSL_AP_BUILD_WORKAROUND
// NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14.
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE)
//#include <drv_conf.h>
//#include <basic_types.h>
//#include <osdep_service.h>
//#include <drv_types.h>
//#include <rtw_byteorder.h>
//#include <hal_intf.h>
#define BEAMFORMING_SUPPORT 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Mp_Precomp.h"
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
//2 Hardware Parameter Files
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/Hal8192CEFWImg_AP.h"
#include "rtl8192c/Hal8192CEPHYImg_AP.h"
#include "rtl8192c/Hal8192CEMACImg_AP.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/Hal8192CEFWImg_ADSL.h"
#include "rtl8192c/Hal8192CEPHYImg_ADSL.h"
#include "rtl8192c/Hal8192CEMACImg_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#if(RTL8192CE_SUPPORT ==1)
#include "rtl8192c/Hal8192CEFWImg_CE.h"
#include "rtl8192c/Hal8192CEPHYImg_CE.h"
#include "rtl8192c/Hal8192CEMACImg_CE.h"
#endif
#if(RTL8192CU_SUPPORT ==1)
#include "rtl8192c/Hal8192CUFWImg_CE.h"
#include "rtl8192c/Hal8192CUPHYImg_CE.h"
#include "rtl8192c/Hal8192CUMACImg_CE.h"
#endif
#if(RTL8192DE_SUPPORT ==1)
#include "rtl8192d/Hal8192DEFWImg_CE.h"
#include "rtl8192d/Hal8192DEPHYImg_CE.h"
#include "rtl8192d/Hal8192DEMACImg_CE.h"
#endif
#if(RTL8192DU_SUPPORT ==1)
#include "rtl8192d/Hal8192DUFWImg_CE.h"
#include "rtl8192d/Hal8192DUPHYImg_CE.h"
#include "rtl8192d/Hal8192DUMACImg_CE.h"
#endif
#if(RTL8723AS_SUPPORT==1)
#include "rtl8723a/Hal8723SHWImg_CE.h"
#endif
#if(RTL8723AU_SUPPORT==1)
#include "rtl8723a/Hal8723UHWImg_CE.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#endif
//2 OutSrc Header Files
#include "phydm.h"
#include "phydm_HWConfig.h"
#include "phydm_debug.h"
#include "phydm_RegDefine11AC.h"
#include "phydm_RegDefine11N.h"
#include "phydm_AntDiv.h"
#include "phydm_interface.h"
#include "phydm_reg.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_AP.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/HalDMOutSrc8192C_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
//#include "hal_com.h"
#include "HalPhyRf.h"
#if (RTL8192C_SUPPORT==1)
#ifdef CONFIG_INTEL_PROXIM
#include "../proxim/intel_proxim.h"
#endif
#include "rtl8192c/HalDMOutSrc8192C_CE.h"
#include <rtl8192c_hal.h>
#endif
#if (RTL8192D_SUPPORT==1)
#include "rtl8192d/HalDMOutSrc8192D_CE.h"
#include "rtl8192d_hal.h"
#endif
#if (RTL8723A_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_CE.h" //for IQK,LCK,Power-tracking
#include "rtl8723a_hal.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#include "rtl8188e_hal.h"
#endif
#if (RTL8192E_SUPPORT==1)
#include "rtl8192e/HalPhyRf_8192e.h"//for IQK,LCK,Power-tracking
#include "rtl8192e_hal.h"
#endif
#if (RTL8812A_SUPPORT==1)
#include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a_hal.h"
#endif
#if (RTL8821A_SUPPORT==1)
#include "rtl8821a/HalPhyRf_8821A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a_hal.h"
#include "rtl8821a/PhyDM_IQK_8821A.h"
#endif
#if (RTL8723B_SUPPORT==1)
#include "rtl8723b/HalPhyRf_8723B.h"//for IQK,LCK,Power-tracking
#include "rtl8723b_hal.h"
#endif
#endif
#if (RTL8192C_SUPPORT==1)
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "rtl8192c/Hal8192CHWImg_MAC.h"
#include "rtl8192c/Hal8192CHWImg_RF.h"
#include "rtl8192c/Hal8192CHWImg_BB.h"
#include "rtl8192c/Hal8192CHWImg_FW.h"
#endif
#include "rtl8192c/phydm_RTL8192C.h"
#endif
#if (RTL8192D_SUPPORT==1)
#include "rtl8192d/phydm_RTL8192D.h"
#endif
#if (RTL8723A_SUPPORT==1)
#include "rtl8723a/HalHWImg8723A_MAC.h"
#include "rtl8723a/HalHWImg8723A_RF.h"
#include "rtl8723a/HalHWImg8723A_BB.h"
#include "rtl8723a/HalHWImg8723A_FW.h"
#include "rtl8723a/phydm_RegConfig8723A.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/HalHWImg8188E_MAC.h"
#include "rtl8188e/HalHWImg8188E_RF.h"
#include "rtl8188e/HalHWImg8188E_BB.h"
#include "rtl8188e/HalHWImg8188E_FW.h"
#include "rtl8188e/Hal8188EReg.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#include "rtl8188e/HalPhyRf_8188e.h"
#endif
#if (TESTCHIP_SUPPORT == 1)
#include "rtl8188e/HalHWImg8188E_TestChip_MAC.h"
#include "rtl8188e/HalHWImg8188E_TestChip_RF.h"
#include "rtl8188e/HalHWImg8188E_TestChip_BB.h"
#endif
#include "rtl8188e/phydm_RegConfig8188E.h"
#include "rtl8188e/phydm_RTL8188E.h"
#endif
#if (RTL8192E_SUPPORT==1)
#include "rtl8192e/HalHWImg8192E_MAC.h"
#include "rtl8192e/HalHWImg8192E_RF.h"
#include "rtl8192e/HalHWImg8192E_BB.h"
#include "rtl8192e/HalHWImg8192E_FW.h"
#include "rtl8192e/Hal8192EReg.h"
#include "rtl8192e/phydm_RegConfig8192E.h"
#include "rtl8192e/phydm_RTL8192E.h"
#endif
#if (RTL8723B_SUPPORT==1)
#include "rtl8723b/HalHWImg8723B_MAC.h"
#include "rtl8723b/HalHWImg8723B_RF.h"
#include "rtl8723b/HalHWImg8723B_BB.h"
#include "rtl8723b/HalHWImg8723B_FW.h"
#include "rtl8723b/HalHWImg8723B_MP.h"
#include "rtl8723b/Hal8723BReg.h"
#include "rtl8723b/phydm_RTL8723B.h"
#include "rtl8723b/phydm_RegConfig8723B.h"
#endif
#if (RTL8812A_SUPPORT==1)
#include "rtl8812a/HalHWImg8812A_MAC.h"
#include "rtl8812a/HalHWImg8812A_RF.h"
#include "rtl8812a/HalHWImg8812A_BB.h"
#include "rtl8812a/HalHWImg8812A_FW.h"
#include "rtl8812a/phydm_RegConfig8812A.h"
#include "rtl8812a/phydm_RTL8812A.h"
#endif
#if (RTL8821A_SUPPORT==1)
#include "rtl8821a/HalHWImg8821A_MAC.h"
#include "rtl8821a/HalHWImg8821A_RF.h"
#include "rtl8821a/HalHWImg8821A_BB.h"
#include "rtl8821a/HalHWImg8821A_FW.h"
#include "rtl8821a/phydm_RegConfig8821A.h"
#include "rtl8821a/phydm_RTL8821A.h"
#endif
#endif // __ODM_PRECOMP_H__

409
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/phydm_types.h
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@ -1,409 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_TYPES_H__
#define __ODM_TYPES_H__
#define ODM_RATEMCS15_SG 0x1c
#define ODM_RATEMCS32 0x20
// CCK Rates, TxHT = 0
#define ODM_RATE1M 0x00
#define ODM_RATE2M 0x01
#define ODM_RATE5_5M 0x02
#define ODM_RATE11M 0x03
// OFDM Rates, TxHT = 0
#define ODM_RATE6M 0x04
#define ODM_RATE9M 0x05
#define ODM_RATE12M 0x06
#define ODM_RATE18M 0x07
#define ODM_RATE24M 0x08
#define ODM_RATE36M 0x09
#define ODM_RATE48M 0x0A
#define ODM_RATE54M 0x0B
// MCS Rates, TxHT = 1
#define ODM_RATEMCS0 0x0C
#define ODM_RATEMCS1 0x0D
#define ODM_RATEMCS2 0x0E
#define ODM_RATEMCS3 0x0F
#define ODM_RATEMCS4 0x10
#define ODM_RATEMCS5 0x11
#define ODM_RATEMCS6 0x12
#define ODM_RATEMCS7 0x13
#define ODM_RATEMCS8 0x14
#define ODM_RATEMCS9 0x15
#define ODM_RATEMCS10 0x16
#define ODM_RATEMCS11 0x17
#define ODM_RATEMCS12 0x18
#define ODM_RATEMCS13 0x19
#define ODM_RATEMCS14 0x1A
#define ODM_RATEMCS15 0x1B
#define ODM_RATEMCS16 0x1C
#define ODM_RATEMCS17 0x1D
#define ODM_RATEMCS18 0x1E
#define ODM_RATEMCS19 0x1F
#define ODM_RATEMCS20 0x20
#define ODM_RATEMCS21 0x21
#define ODM_RATEMCS22 0x22
#define ODM_RATEMCS23 0x23
#define ODM_RATEMCS24 0x24
#define ODM_RATEMCS25 0x25
#define ODM_RATEMCS26 0x26
#define ODM_RATEMCS27 0x27
#define ODM_RATEMCS28 0x28
#define ODM_RATEMCS29 0x29
#define ODM_RATEMCS30 0x2A
#define ODM_RATEMCS31 0x2B
#define ODM_RATEVHTSS1MCS0 0x2C
#define ODM_RATEVHTSS1MCS1 0x2D
#define ODM_RATEVHTSS1MCS2 0x2E
#define ODM_RATEVHTSS1MCS3 0x2F
#define ODM_RATEVHTSS1MCS4 0x30
#define ODM_RATEVHTSS1MCS5 0x31
#define ODM_RATEVHTSS1MCS6 0x32
#define ODM_RATEVHTSS1MCS7 0x33
#define ODM_RATEVHTSS1MCS8 0x34
#define ODM_RATEVHTSS1MCS9 0x35
#define ODM_RATEVHTSS2MCS0 0x36
#define ODM_RATEVHTSS2MCS1 0x37
#define ODM_RATEVHTSS2MCS2 0x38
#define ODM_RATEVHTSS2MCS3 0x39
#define ODM_RATEVHTSS2MCS4 0x3A
#define ODM_RATEVHTSS2MCS5 0x3B
#define ODM_RATEVHTSS2MCS6 0x3C
#define ODM_RATEVHTSS2MCS7 0x3D
#define ODM_RATEVHTSS2MCS8 0x3E
#define ODM_RATEVHTSS2MCS9 0x3F
#define ODM_RATEVHTSS3MCS0 0x40
#define ODM_RATEVHTSS3MCS1 0x41
#define ODM_RATEVHTSS3MCS2 0x42
#define ODM_RATEVHTSS3MCS3 0x43
#define ODM_RATEVHTSS3MCS4 0x44
#define ODM_RATEVHTSS3MCS5 0x45
#define ODM_RATEVHTSS3MCS6 0x46
#define ODM_RATEVHTSS3MCS7 0x47
#define ODM_RATEVHTSS3MCS8 0x48
#define ODM_RATEVHTSS3MCS9 0x49
#define ODM_RATEVHTSS4MCS0 0x4A
#define ODM_RATEVHTSS4MCS1 0x4B
#define ODM_RATEVHTSS4MCS2 0x4C
#define ODM_RATEVHTSS4MCS3 0x4D
#define ODM_RATEVHTSS4MCS4 0x4E
#define ODM_RATEVHTSS4MCS5 0x4F
#define ODM_RATEVHTSS4MCS6 0x50
#define ODM_RATEVHTSS4MCS7 0x51
#define ODM_RATEVHTSS4MCS8 0x52
#define ODM_RATEVHTSS4MCS9 0x53
//
// Define Different SW team support
//
#define ODM_AP 0x01 //BIT0
#define ODM_ADSL 0x02 //BIT1
#define ODM_CE 0x04 //BIT2
#define ODM_WIN 0x08 //BIT3
#define DM_ODM_SUPPORT_TYPE ODM_CE
// Deifne HW endian support
#define ODM_ENDIAN_BIG 0
#define ODM_ENDIAN_LITTLE 1
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc)))
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv)))
#endif
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define RT_PCI_INTERFACE 1
#define RT_USB_INTERFACE 2
#define RT_SDIO_INTERFACE 3
#endif
typedef enum _HAL_STATUS{
HAL_STATUS_SUCCESS,
HAL_STATUS_FAILURE,
/*RT_STATUS_PENDING,
RT_STATUS_RESOURCE,
RT_STATUS_INVALID_CONTEXT,
RT_STATUS_INVALID_PARAMETER,
RT_STATUS_NOT_SUPPORT,
RT_STATUS_OS_API_FAILED,*/
}HAL_STATUS,*PHAL_STATUS;
#if( DM_ODM_SUPPORT_TYPE == ODM_AP)
#define MP_DRIVER 0
#endif
#if(DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define VISTA_USB_RX_REVISE 0
//
// Declare for ODM spin lock defintion temporarily fro compile pass.
//
typedef enum _RT_SPINLOCK_TYPE{
RT_TX_SPINLOCK = 1,
RT_RX_SPINLOCK = 2,
RT_RM_SPINLOCK = 3,
RT_CAM_SPINLOCK = 4,
RT_SCAN_SPINLOCK = 5,
RT_LOG_SPINLOCK = 7,
RT_BW_SPINLOCK = 8,
RT_CHNLOP_SPINLOCK = 9,
RT_RF_OPERATE_SPINLOCK = 10,
RT_INITIAL_SPINLOCK = 11,
RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30.
#if VISTA_USB_RX_REVISE
RT_USBRX_CONTEXT_SPINLOCK = 13,
RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR
#endif
//Shall we define Ndis 6.2 SpinLock Here ?
RT_PORT_SPINLOCK=16,
RT_VNIC_SPINLOCK=17,
RT_HVL_SPINLOCK=18,
RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09.
RT_BTData_SPINLOCK=25,
RT_WAPI_OPTION_SPINLOCK=26,
RT_WAPI_RX_SPINLOCK=27,
// add for 92D CCK control issue
RT_CCK_PAGEA_SPINLOCK = 28,
RT_BUFFER_SPINLOCK = 29,
RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
RT_GEN_TEMP_BUF_SPINLOCK = 31,
RT_AWB_SPINLOCK = 32,
RT_FW_PS_SPINLOCK = 33,
RT_HW_TIMER_SPIN_LOCK = 34,
RT_MPT_WI_SPINLOCK = 35,
RT_P2P_SPIN_LOCK = 36, // Protect P2P context
RT_DBG_SPIN_LOCK = 37,
RT_IQK_SPINLOCK = 38,
RT_PENDED_OID_SPINLOCK = 39,
RT_CHNLLIST_SPINLOCK = 40,
RT_INDIC_SPINLOCK = 41, //protect indication
RT_RFD_SPINLOCK = 42,
RT_LAST_SPINLOCK,
}RT_SPINLOCK_TYPE;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define STA_INFO_T RT_WLAN_STA
#define PSTA_INFO_T PRT_WLAN_STA
// typedef unsigned long u4Byte,*pu4Byte;
#define CONFIG_HW_ANTENNA_DIVERSITY
#define CONFIG_SW_ANTENNA_DIVERSITY
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
#define ADSL_AP_BUILD_WORKAROUND
#define AP_BUILD_WORKAROUND
//2 [ Configure Antenna Diversity ]
#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH)
#define CONFIG_HW_ANTENNA_DIVERSITY
#define ODM_EVM_ENHANCE_ANTDIV
//----------
#if(!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
#define CONFIG_NO_2G_DIVERSITY
#endif
#ifdef CONFIG_NO_5G_DIVERSITY_8881A
#define CONFIG_NO_5G_DIVERSITY
#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
#define CONFIG_5G_CGCS_RX_DIVERSITY
#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
#define CONFIG_5G_CG_TRX_DIVERSITY
#endif
#if(!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
#define CONFIG_NO_5G_DIVERSITY
#endif
//----------
#if ( defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_NOT_SUPPORT_ANTDIV
#elif( !defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_2G_SUPPORT_ANTDIV
#elif( defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_5G_SUPPORT_ANTDIV
#elif( !defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_2G5G_SUPPORT_ANTDIV
#endif
//----------
#endif
#ifdef AP_BUILD_WORKAROUND
#include "../typedef.h"
#else
typedef void VOID,*PVOID;
typedef unsigned char BOOLEAN,*PBOOLEAN;
typedef unsigned char u1Byte,*pu1Byte;
typedef unsigned short u2Byte,*pu2Byte;
typedef unsigned int u4Byte,*pu4Byte;
typedef unsigned long long u8Byte,*pu8Byte;
#if 1
/* In ARM platform, system would use the type -- "char" as "unsigned char"
* And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/
typedef signed char s1Byte,*ps1Byte;
#else
typedef char s1Byte,*ps1Byte;
#endif
typedef short s2Byte,*ps2Byte;
typedef long s4Byte,*ps4Byte;
typedef long long s8Byte,*ps8Byte;
#endif
typedef struct rtl8192cd_priv *prtl8192cd_priv;
typedef struct stat_info STA_INFO_T,*PSTA_INFO_T;
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#ifdef CONFIG_PCI_HCI
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#endif
#define _TRUE 1
#define _FALSE 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
#define ADSL_AP_BUILD_WORKAROUND
#define ADSL_BUILD_WORKAROUND
//
typedef unsigned char BOOLEAN,*PBOOLEAN;
typedef unsigned char u1Byte,*pu1Byte;
typedef unsigned short u2Byte,*pu2Byte;
typedef unsigned int u4Byte,*pu4Byte;
typedef unsigned long long u8Byte,*pu8Byte;
#if 1
/* In ARM platform, system would use the type -- "char" as "unsigned char"
* And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/
typedef signed char s1Byte,*ps1Byte;
#else
typedef char s1Byte,*ps1Byte;
#endif
typedef short s2Byte,*ps2Byte;
typedef long s4Byte,*ps4Byte;
typedef long long s8Byte,*ps8Byte;
typedef struct rtl8192cd_priv *prtl8192cd_priv;
typedef struct stat_info STA_INFO_T,*PSTA_INFO_T;
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#define _TRUE 1
#define _FALSE 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include <drv_types.h>
#if 0
typedef u8 u1Byte, *pu1Byte;
typedef u16 u2Byte,*pu2Byte;
typedef u32 u4Byte,*pu4Byte;
typedef u64 u8Byte,*pu8Byte;
typedef s8 s1Byte,*ps1Byte;
typedef s16 s2Byte,*ps2Byte;
typedef s32 s4Byte,*ps4Byte;
typedef s64 s8Byte,*ps8Byte;
#else
#define u1Byte u8
#define pu1Byte u8*
#define u2Byte u16
#define pu2Byte u16*
#define u4Byte u32
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*
#define s1Byte s8
#define ps1Byte s8*
#define s2Byte s16
#define ps2Byte s16*
#define s4Byte s32
#define ps4Byte s32*
#define s8Byte s64
#define ps8Byte s64*
#endif
#ifdef CONFIG_USB_HCI
#define DEV_BUS_TYPE RT_USB_INTERFACE
#elif defined(CONFIG_PCI_HCI)
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#elif defined(CONFIG_SDIO_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#elif defined(CONFIG_GSPI_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#endif
#if defined(CONFIG_LITTLE_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#elif defined (CONFIG_BIG_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#endif
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define STA_INFO_T struct sta_info
#define PSTA_INFO_T struct sta_info *
#define TRUE _TRUE
#define FALSE _FALSE
#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
//define useless flag to avoid compile warning
#define USE_WORKITEM 0
#define FOR_BRAZIL_PRETEST 0
#define FPGA_TWO_MAC_VERIFICATION 0
#define RTL8881A_SUPPORT 0
#endif
#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
#define COND_ELSE 2
#define COND_ENDIF 3
#endif // __ODM_TYPES_H__

6981
drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/OUTSRC/rtl8723b/HalHWImg8723B_FW.c
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