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clk: rockchip: px30: Fix i2s out mclk

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Change-Id: I1f90747c780c867e172168e8c877915477a66e59
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2018-02-07 17:42:14 +08:00 committed by Tao Huang
parent dcc52ea50d
commit f6128506aa
1 changed files with 12 additions and 4 deletions
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16
drivers/clk/rockchip/clk-px30.c
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@ -640,9 +640,11 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
PX30_CLKGATE_CON(9), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", mux_i2s0_tx_out_p, 0,
COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0,
PX30_CLKSEL_CON(28), 14, 2, MFLAGS,
PX30_CLKGATE_CON(9), 15, GFLAGS),
GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK),
COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0,
PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS,
@ -654,9 +656,11 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
PX30_CLKGATE_CON(17), 2, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", mux_i2s0_rx_out_p, 0,
COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0,
PX30_CLKSEL_CON(58), 14, 2, MFLAGS,
PX30_CLKGATE_CON(17), 3, GFLAGS),
GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK),
COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0,
PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS,
@ -667,9 +671,11 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
&px30_i2s1_fracmux),
GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 2, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S1_OUT, "clk_i2s1_out", mux_i2s1_out_p, 0,
COMPOSITE_NODIV(SCLK_I2S1_OUT, "clk_i2s1_out_pre", mux_i2s1_out_p, 0,
PX30_CLKSEL_CON(30), 15, 1, MFLAGS,
PX30_CLKGATE_CON(10), 3, GFLAGS),
GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK),
COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0,
PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS,
@ -680,9 +686,11 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
&px30_i2s2_fracmux),
GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 6, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S2_OUT, "clk_i2s2_out", mux_i2s2_out_p, 0,
COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0,
PX30_CLKSEL_CON(32), 15, 1, MFLAGS,
PX30_CLKGATE_CON(10), 7, GFLAGS),
GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK),
COMPOSITE(0, "clk_uart1_src", mux_uart_src_p, 0,
PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS,