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arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus

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The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
As such, let's add the GE PHY node to the SoC dtsi.

The LDO controller found in the SoC must be enabled to provide constant
low voltages to the PHY. The mdio-ipq4019 driver already has support
for this, so adding the appropriate TCSR register offset.

In addition, the GE PHY outputs both the RX and TX clocks to the GCC
which gate controls them and routes them back to the PHY itself.
So let's create two DT fixed clocks and register them in the GCC node.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-3-01be06378c15@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
George Moussalem 2025-06-30 16:35:02 +04:00 committed by Bjorn Andersson
parent 1e2261a669
commit f5f2b835e3
1 changed files with 23 additions and 3 deletions
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26
arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@ -17,6 +17,18 @@ / {
#size-cells = <2>;
clocks {
gephy_rx_clk: gephy-rx-clk {
compatible = "fixed-clock";
clock-frequency = <125000000>;
#clock-cells = <0>;
};
gephy_tx_clk: gephy-tx-clk {
compatible = "fixed-clock";
clock-frequency = <125000000>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -187,7 +199,8 @@ pcie0_phy: phy@86000 {
mdio0: mdio@88000 {
compatible = "qcom,ipq5018-mdio";
reg = <0x00088000 0x64>;
reg = <0x00088000 0x64>,
<0x019475c4 0x4>;
#address-cells = <1>;
#size-cells = <0>;
@ -195,6 +208,13 @@ mdio0: mdio@88000 {
clock-names = "gcc_mdio_ahb_clk";
status = "disabled";
ge_phy: ethernet-phy@7 {
compatible = "ethernet-phy-id004d.d0c0";
reg = <7>;
resets = <&gcc GCC_GEPHY_MISC_ARES>;
};
};
mdio1: mdio@90000 {
@ -346,8 +366,8 @@ gcc: clock-controller@1800000 {
<&pcie0_phy>,
<&pcie1_phy>,
<0>,
<0>,
<0>,
<&gephy_rx_clk>,
<&gephy_tx_clk>,
<0>,
<0>;
#clock-cells = <1>;