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dt-bindings: display: msm: document DSI controller and phy on QCS8300

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Document DSI controller and phy on QCS8300 platform.

Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696787/
Link: https://lore.kernel.org/r/20260104134442.732876-4-quic_amakhija@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Ayushi Makhija 2026-01-04 19:14:40 +05:30 committed by Dmitry Baryshkov
parent c42973f929
commit f5aa414e5c
1 changed files with 101 additions and 1 deletions
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102
Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
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@ -53,13 +53,23 @@ patternProperties:
contains:
const: qcom,qcs8300-dp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,qcs8300-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,qcs8300-edp-phy
enum:
- qcom,qcs8300-dsi-phy-5nm
- qcom,qcs8300-edp-phy
required:
- compatible
@ -71,6 +81,7 @@ examples:
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@ -142,6 +153,13 @@ examples:
remote-endpoint = <&mdss_dp0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
};
mdp_opp_table: opp-table {
@ -169,6 +187,88 @@ examples:
};
};
dsi@ae94000 {
compatible = "qcom,qcs8300-dsi-ctrl",
"qcom,sa8775p-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0x0ae94000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
<&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
phys = <&mdss_dsi0_phy>;
operating-points-v2 = <&dsi0_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
vdda-supply = <&vreg_l5a>;
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss0_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss0_dsi0_out: endpoint { };
};
};
dsi0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
mdss_dsi0_phy: phy@ae94400 {
compatible = "qcom,qcs8300-dsi-phy-5nm",
"qcom,sa8775p-dsi-phy-5nm";
reg = <0x0ae94400 0x200>,
<0x0ae94600 0x280>,
<0x0ae94900 0x27c>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
vdds-supply = <&vreg_l4a>;
};
mdss_dp0_phy: phy@aec2a00 {
compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";