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drm/xe/topology: Simplify code for loading DSS mask

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Instead of passing registers using va_list we can keep them in
the static array and pass as such and also lower driver footprint:

  add/remove: 2/0 grow/shrink: 0/2 up/down: 24/-175 (-151)
  Function                                     old     new   delta
  geometry_regs                                  -      12     +12
  compute_regs                                   -      12     +12
  xe_gt_topology_init                          550     527     -23
  load_dss_mask                                449     297    -152

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20250604202908.769-2-michal.wajdeczko@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Michal Wajdeczko 2025-06-04 22:29:06 +02:00 committed by Matt Roper
parent 678bb4d625
commit f574855a4c
1 changed files with 18 additions and 15 deletions
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33
drivers/gpu/drm/xe/xe_gt_topology.c
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@ -16,20 +16,17 @@
#include "xe_mmio.h"
#include "xe_wa.h"
static void
load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)
static void load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs,
const struct xe_reg regs[])
{
va_list argp;
u32 fuse_val[XE_MAX_DSS_FUSE_REGS] = {};
int i;
if (drm_WARN_ON(&gt_to_xe(gt)->drm, numregs > XE_MAX_DSS_FUSE_REGS))
numregs = XE_MAX_DSS_FUSE_REGS;
va_start(argp, numregs);
for (i = 0; i < numregs; i++)
fuse_val[i] = xe_mmio_read32(&gt->mmio, va_arg(argp, struct xe_reg));
va_end(argp);
fuse_val[i] = xe_mmio_read32(&gt->mmio, regs[i]);
bitmap_from_arr32(mask, fuse_val, numregs * 32);
}
@ -219,9 +216,19 @@ get_num_dss_regs(struct xe_device *xe, int *geometry_regs, int *compute_regs)
void
xe_gt_topology_init(struct xe_gt *gt)
{
static const struct xe_reg geometry_regs[] = {
XELP_GT_GEOMETRY_DSS_ENABLE,
XE2_GT_GEOMETRY_DSS_1,
XE2_GT_GEOMETRY_DSS_2,
};
static const struct xe_reg compute_regs[] = {
XEHP_GT_COMPUTE_DSS_ENABLE,
XEHPC_GT_COMPUTE_DSS_ENABLE_EXT,
XE2_GT_COMPUTE_DSS_2,
};
int num_geometry_regs, num_compute_regs;
struct xe_device *xe = gt_to_xe(gt);
struct drm_printer p;
int num_geometry_regs, num_compute_regs;
get_num_dss_regs(xe, &num_geometry_regs, &num_compute_regs);
@ -233,14 +240,10 @@ xe_gt_topology_init(struct xe_gt *gt)
drm_WARN_ON(&xe->drm, num_compute_regs > 3);
load_dss_mask(gt, gt->fuse_topo.g_dss_mask,
num_geometry_regs,
XELP_GT_GEOMETRY_DSS_ENABLE,
XE2_GT_GEOMETRY_DSS_1,
XE2_GT_GEOMETRY_DSS_2);
load_dss_mask(gt, gt->fuse_topo.c_dss_mask, num_compute_regs,
XEHP_GT_COMPUTE_DSS_ENABLE,
XEHPC_GT_COMPUTE_DSS_ENABLE_EXT,
XE2_GT_COMPUTE_DSS_2);
num_geometry_regs, geometry_regs);
load_dss_mask(gt, gt->fuse_topo.c_dss_mask,
num_compute_regs, compute_regs);
load_eu_mask(gt, gt->fuse_topo.eu_mask_per_dss, &gt->fuse_topo.eu_type);
load_l3_bank_mask(gt, gt->fuse_topo.l3_bank_mask);