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Merge branch 'there-are-some-bugfix-for-the-hns3-ethernet-driver'
Jijie Shao says: ==================== There are some bugfix for the HNS3 ethernet driver There's a series of bugfix that's been accepted: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/commit/?id=d80a3091308491455b6501b1c4b68698c4a7cd24 However, The series is making the driver poke into IOMMU internals instead of implementing appropriate IOMMU workarounds. After discussion, the series was reverted: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/commit/?id=249cfa318fb1b77eb726c2ff4f74c9685f04e568 But only two patches are related to the IOMMU. Other patches involve only the modification of the driver. This series resends other patches. v2*: https://lore.kernel.org/20241217010839.1742227-1-shaojijie@huawei.com v2: https://lore.kernel.org/20241216132346.1197079-1-shaojijie@huawei.com v1: https://lore.kernel.org/20241107133023.3813095-1-shaojijie@huawei.com ==================== Link: https://patch.msgid.link/20250106143642.539698-1-shaojijie@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
f552b3037d
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@ -916,9 +916,6 @@ struct hnae3_handle {
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u8 netdev_flags;
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struct dentry *hnae3_dbgfs;
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/* protects concurrent contention between debugfs commands */
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struct mutex dbgfs_lock;
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char **dbgfs_buf;
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/* Network interface message level enabled bits */
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u32 msg_enable;
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@ -1260,69 +1260,55 @@ static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data,
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static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer,
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size_t count, loff_t *ppos)
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{
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struct hns3_dbg_data *dbg_data = filp->private_data;
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char *buf = filp->private_data;
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return simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
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}
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static int hns3_dbg_open(struct inode *inode, struct file *filp)
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{
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struct hns3_dbg_data *dbg_data = inode->i_private;
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struct hnae3_handle *handle = dbg_data->handle;
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struct hns3_nic_priv *priv = handle->priv;
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ssize_t size = 0;
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char **save_buf;
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char *read_buf;
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u32 index;
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char *buf;
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int ret;
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if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
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test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
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return -EBUSY;
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ret = hns3_dbg_get_cmd_index(dbg_data, &index);
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if (ret)
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return ret;
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mutex_lock(&handle->dbgfs_lock);
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save_buf = &handle->dbgfs_buf[index];
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buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
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test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) {
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ret = -EBUSY;
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goto out;
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ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd,
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buf, hns3_dbg_cmd[index].buf_len);
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if (ret) {
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kvfree(buf);
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return ret;
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}
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if (*save_buf) {
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read_buf = *save_buf;
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} else {
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read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL);
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if (!read_buf) {
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ret = -ENOMEM;
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goto out;
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}
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filp->private_data = buf;
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return 0;
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}
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/* save the buffer addr until the last read operation */
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*save_buf = read_buf;
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/* get data ready for the first time to read */
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ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd,
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read_buf, hns3_dbg_cmd[index].buf_len);
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if (ret)
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goto out;
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}
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size = simple_read_from_buffer(buffer, count, ppos, read_buf,
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strlen(read_buf));
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if (size > 0) {
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mutex_unlock(&handle->dbgfs_lock);
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return size;
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}
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out:
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/* free the buffer for the last read operation */
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if (*save_buf) {
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kvfree(*save_buf);
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*save_buf = NULL;
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}
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mutex_unlock(&handle->dbgfs_lock);
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return ret;
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static int hns3_dbg_release(struct inode *inode, struct file *filp)
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{
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kvfree(filp->private_data);
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filp->private_data = NULL;
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return 0;
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}
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static const struct file_operations hns3_dbg_fops = {
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.owner = THIS_MODULE,
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.open = simple_open,
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.open = hns3_dbg_open,
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.read = hns3_dbg_read,
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.release = hns3_dbg_release,
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};
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static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd)
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@ -1379,13 +1365,6 @@ int hns3_dbg_init(struct hnae3_handle *handle)
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int ret;
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u32 i;
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handle->dbgfs_buf = devm_kcalloc(&handle->pdev->dev,
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ARRAY_SIZE(hns3_dbg_cmd),
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sizeof(*handle->dbgfs_buf),
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GFP_KERNEL);
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if (!handle->dbgfs_buf)
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return -ENOMEM;
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hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry =
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debugfs_create_dir(name, hns3_dbgfs_root);
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handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry;
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@ -1395,8 +1374,6 @@ int hns3_dbg_init(struct hnae3_handle *handle)
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debugfs_create_dir(hns3_dbg_dentry[i].name,
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handle->hnae3_dbgfs);
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mutex_init(&handle->dbgfs_lock);
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for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) {
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if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES &&
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ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) ||
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@ -1425,24 +1402,13 @@ int hns3_dbg_init(struct hnae3_handle *handle)
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out:
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debugfs_remove_recursive(handle->hnae3_dbgfs);
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handle->hnae3_dbgfs = NULL;
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mutex_destroy(&handle->dbgfs_lock);
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return ret;
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}
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void hns3_dbg_uninit(struct hnae3_handle *handle)
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{
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u32 i;
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debugfs_remove_recursive(handle->hnae3_dbgfs);
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handle->hnae3_dbgfs = NULL;
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for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++)
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if (handle->dbgfs_buf[i]) {
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kvfree(handle->dbgfs_buf[i]);
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handle->dbgfs_buf[i] = NULL;
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}
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mutex_destroy(&handle->dbgfs_lock);
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}
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void hns3_dbg_register_debugfs(const char *debugfs_dir_name)
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@ -2452,7 +2452,6 @@ static int hns3_nic_set_features(struct net_device *netdev,
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return ret;
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}
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netdev->features = features;
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return 0;
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}
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@ -6,6 +6,7 @@
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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@ -3574,6 +3575,17 @@ static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
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return ret;
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}
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static void hclge_set_reset_pending(struct hclge_dev *hdev,
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enum hnae3_reset_type reset_type)
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{
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/* When an incorrect reset type is executed, the get_reset_level
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* function generates the HNAE3_NONE_RESET flag. As a result, this
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* type do not need to pending.
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*/
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if (reset_type != HNAE3_NONE_RESET)
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set_bit(reset_type, &hdev->reset_pending);
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}
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static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
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{
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u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg;
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@ -3594,7 +3606,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
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*/
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if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
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dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
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set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
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hclge_set_reset_pending(hdev, HNAE3_IMP_RESET);
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set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
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*clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
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hdev->rst_stats.imp_rst_cnt++;
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@ -3604,7 +3616,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
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if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
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dev_info(&hdev->pdev->dev, "global reset interrupt\n");
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set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
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set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
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hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET);
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*clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
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hdev->rst_stats.global_rst_cnt++;
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return HCLGE_VECTOR0_EVENT_RST;
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@ -3759,7 +3771,7 @@ static int hclge_misc_irq_init(struct hclge_dev *hdev)
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snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
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HCLGE_NAME, pci_name(hdev->pdev));
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ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
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0, hdev->misc_vector.name, hdev);
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IRQF_NO_AUTOEN, hdev->misc_vector.name, hdev);
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if (ret) {
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hclge_free_vector(hdev, 0);
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dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
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@ -4052,7 +4064,7 @@ static void hclge_do_reset(struct hclge_dev *hdev)
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case HNAE3_FUNC_RESET:
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dev_info(&pdev->dev, "PF reset requested\n");
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/* schedule again to check later */
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set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
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hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET);
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hclge_reset_task_schedule(hdev);
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break;
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default:
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@ -4086,6 +4098,8 @@ static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
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clear_bit(HNAE3_FLR_RESET, addr);
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}
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clear_bit(HNAE3_NONE_RESET, addr);
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if (hdev->reset_type != HNAE3_NONE_RESET &&
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rst_level < hdev->reset_type)
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return HNAE3_NONE_RESET;
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@ -4227,7 +4241,7 @@ static bool hclge_reset_err_handle(struct hclge_dev *hdev)
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return false;
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} else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) {
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hdev->rst_stats.reset_fail_cnt++;
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set_bit(hdev->reset_type, &hdev->reset_pending);
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hclge_set_reset_pending(hdev, hdev->reset_type);
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dev_info(&hdev->pdev->dev,
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"re-schedule reset task(%u)\n",
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hdev->rst_stats.reset_fail_cnt);
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|
|
@ -4470,8 +4484,20 @@ static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
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static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
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enum hnae3_reset_type rst_type)
|
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{
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#define HCLGE_SUPPORT_RESET_TYPE \
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(BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \
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BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET))
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|
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struct hclge_dev *hdev = ae_dev->priv;
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if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) {
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/* To prevent reset triggered by hclge_reset_event */
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set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request);
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dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n",
|
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rst_type);
|
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return;
|
||||
}
|
||||
|
||||
set_bit(rst_type, &hdev->default_reset_request);
|
||||
}
|
||||
|
||||
|
|
@ -11881,9 +11907,6 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
|
|||
|
||||
hclge_init_rxd_adv_layout(hdev);
|
||||
|
||||
/* Enable MISC vector(vector0) */
|
||||
hclge_enable_vector(&hdev->misc_vector, true);
|
||||
|
||||
ret = hclge_init_wol(hdev);
|
||||
if (ret)
|
||||
dev_warn(&pdev->dev,
|
||||
|
|
@ -11896,6 +11919,10 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
|
|||
hclge_state_init(hdev);
|
||||
hdev->last_reset_time = jiffies;
|
||||
|
||||
/* Enable MISC vector(vector0) */
|
||||
enable_irq(hdev->misc_vector.vector_irq);
|
||||
hclge_enable_vector(&hdev->misc_vector, true);
|
||||
|
||||
dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n",
|
||||
HCLGE_DRIVER_NAME);
|
||||
|
||||
|
|
@ -12301,7 +12328,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
|
|||
|
||||
/* Disable MISC vector(vector0) */
|
||||
hclge_enable_vector(&hdev->misc_vector, false);
|
||||
synchronize_irq(hdev->misc_vector.vector_irq);
|
||||
disable_irq(hdev->misc_vector.vector_irq);
|
||||
|
||||
/* Disable all hw interrupts */
|
||||
hclge_config_mac_tnl_int(hdev, false);
|
||||
|
|
|
|||
|
|
@ -58,6 +58,9 @@ bool hclge_ptp_set_tx_info(struct hnae3_handle *handle, struct sk_buff *skb)
|
|||
struct hclge_dev *hdev = vport->back;
|
||||
struct hclge_ptp *ptp = hdev->ptp;
|
||||
|
||||
if (!ptp)
|
||||
return false;
|
||||
|
||||
if (!test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) ||
|
||||
test_and_set_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) {
|
||||
ptp->tx_skipped++;
|
||||
|
|
|
|||
|
|
@ -510,9 +510,9 @@ static int hclge_get_dfx_reg(struct hclge_dev *hdev, void *data)
|
|||
static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data,
|
||||
struct hnae3_knic_private_info *kinfo)
|
||||
{
|
||||
#define HCLGE_RING_REG_OFFSET 0x200
|
||||
#define HCLGE_RING_INT_REG_OFFSET 0x4
|
||||
|
||||
struct hnae3_queue *tqp;
|
||||
int i, j, reg_num;
|
||||
int data_num_sum;
|
||||
u32 *reg = data;
|
||||
|
|
@ -533,10 +533,11 @@ static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data,
|
|||
reg_num = ARRAY_SIZE(ring_reg_addr_list);
|
||||
for (j = 0; j < kinfo->num_tqps; j++) {
|
||||
reg += hclge_reg_get_tlv(HCLGE_REG_TAG_RING, reg_num, reg);
|
||||
tqp = kinfo->tqp[j];
|
||||
for (i = 0; i < reg_num; i++)
|
||||
*reg++ = hclge_read_dev(&hdev->hw,
|
||||
ring_reg_addr_list[i] +
|
||||
HCLGE_RING_REG_OFFSET * j);
|
||||
*reg++ = readl_relaxed(tqp->io_base -
|
||||
HCLGE_TQP_REG_OFFSET +
|
||||
ring_reg_addr_list[i]);
|
||||
}
|
||||
data_num_sum += (reg_num + HCLGE_REG_TLV_SPACE) * kinfo->num_tqps;
|
||||
|
||||
|
|
|
|||
|
|
@ -1393,6 +1393,17 @@ static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void hclgevf_set_reset_pending(struct hclgevf_dev *hdev,
|
||||
enum hnae3_reset_type reset_type)
|
||||
{
|
||||
/* When an incorrect reset type is executed, the get_reset_level
|
||||
* function generates the HNAE3_NONE_RESET flag. As a result, this
|
||||
* type do not need to pending.
|
||||
*/
|
||||
if (reset_type != HNAE3_NONE_RESET)
|
||||
set_bit(reset_type, &hdev->reset_pending);
|
||||
}
|
||||
|
||||
static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
|
||||
{
|
||||
#define HCLGEVF_RESET_WAIT_US 20000
|
||||
|
|
@ -1542,7 +1553,7 @@ static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
|
|||
hdev->rst_stats.rst_fail_cnt);
|
||||
|
||||
if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
|
||||
set_bit(hdev->reset_type, &hdev->reset_pending);
|
||||
hclgevf_set_reset_pending(hdev, hdev->reset_type);
|
||||
|
||||
if (hclgevf_is_reset_pending(hdev)) {
|
||||
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
|
||||
|
|
@ -1662,6 +1673,8 @@ static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr)
|
|||
clear_bit(HNAE3_FLR_RESET, addr);
|
||||
}
|
||||
|
||||
clear_bit(HNAE3_NONE_RESET, addr);
|
||||
|
||||
return rst_level;
|
||||
}
|
||||
|
||||
|
|
@ -1671,14 +1684,15 @@ static void hclgevf_reset_event(struct pci_dev *pdev,
|
|||
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
|
||||
struct hclgevf_dev *hdev = ae_dev->priv;
|
||||
|
||||
dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
|
||||
|
||||
if (hdev->default_reset_request)
|
||||
hdev->reset_level =
|
||||
hclgevf_get_reset_level(&hdev->default_reset_request);
|
||||
else
|
||||
hdev->reset_level = HNAE3_VF_FUNC_RESET;
|
||||
|
||||
dev_info(&hdev->pdev->dev, "received reset request from VF enet, reset level is %d\n",
|
||||
hdev->reset_level);
|
||||
|
||||
/* reset of this VF requested */
|
||||
set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
|
||||
hclgevf_reset_task_schedule(hdev);
|
||||
|
|
@ -1689,8 +1703,20 @@ static void hclgevf_reset_event(struct pci_dev *pdev,
|
|||
static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
|
||||
enum hnae3_reset_type rst_type)
|
||||
{
|
||||
#define HCLGEVF_SUPPORT_RESET_TYPE \
|
||||
(BIT(HNAE3_VF_RESET) | BIT(HNAE3_VF_FUNC_RESET) | \
|
||||
BIT(HNAE3_VF_PF_FUNC_RESET) | BIT(HNAE3_VF_FULL_RESET) | \
|
||||
BIT(HNAE3_FLR_RESET) | BIT(HNAE3_VF_EXP_RESET))
|
||||
|
||||
struct hclgevf_dev *hdev = ae_dev->priv;
|
||||
|
||||
if (!(BIT(rst_type) & HCLGEVF_SUPPORT_RESET_TYPE)) {
|
||||
/* To prevent reset triggered by hclge_reset_event */
|
||||
set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request);
|
||||
dev_info(&hdev->pdev->dev, "unsupported reset type %d\n",
|
||||
rst_type);
|
||||
return;
|
||||
}
|
||||
set_bit(rst_type, &hdev->default_reset_request);
|
||||
}
|
||||
|
||||
|
|
@ -1847,14 +1873,14 @@ static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
|
|||
*/
|
||||
if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
|
||||
/* prepare for full reset of stack + pcie interface */
|
||||
set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
|
||||
hclgevf_set_reset_pending(hdev, HNAE3_VF_FULL_RESET);
|
||||
|
||||
/* "defer" schedule the reset task again */
|
||||
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
|
||||
} else {
|
||||
hdev->reset_attempts++;
|
||||
|
||||
set_bit(hdev->reset_level, &hdev->reset_pending);
|
||||
hclgevf_set_reset_pending(hdev, hdev->reset_level);
|
||||
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
|
||||
}
|
||||
hclgevf_reset_task_schedule(hdev);
|
||||
|
|
@ -1977,7 +2003,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
|
|||
rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
|
||||
dev_info(&hdev->pdev->dev,
|
||||
"receive reset interrupt 0x%x!\n", rst_ing_reg);
|
||||
set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
|
||||
hclgevf_set_reset_pending(hdev, HNAE3_VF_RESET);
|
||||
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
|
||||
set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
|
||||
*clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
|
||||
|
|
@ -2287,6 +2313,8 @@ static void hclgevf_state_init(struct hclgevf_dev *hdev)
|
|||
clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
|
||||
|
||||
INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);
|
||||
/* timer needs to be initialized before misc irq */
|
||||
timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0);
|
||||
|
||||
mutex_init(&hdev->mbx_resp.mbx_mutex);
|
||||
sema_init(&hdev->reset_sem, 1);
|
||||
|
|
@ -2986,7 +3014,6 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
|
|||
HCLGEVF_DRIVER_NAME);
|
||||
|
||||
hclgevf_task_schedule(hdev, round_jiffies_relative(HZ));
|
||||
timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -123,10 +123,10 @@ int hclgevf_get_regs_len(struct hnae3_handle *handle)
|
|||
void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
|
||||
void *data)
|
||||
{
|
||||
#define HCLGEVF_RING_REG_OFFSET 0x200
|
||||
#define HCLGEVF_RING_INT_REG_OFFSET 0x4
|
||||
|
||||
struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
|
||||
struct hnae3_queue *tqp;
|
||||
int i, j, reg_um;
|
||||
u32 *reg = data;
|
||||
|
||||
|
|
@ -147,10 +147,11 @@ void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
|
|||
reg_um = ARRAY_SIZE(ring_reg_addr_list);
|
||||
for (j = 0; j < hdev->num_tqps; j++) {
|
||||
reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_RING, reg_um, reg);
|
||||
tqp = &hdev->htqp[j].q;
|
||||
for (i = 0; i < reg_um; i++)
|
||||
*reg++ = hclgevf_read_dev(&hdev->hw,
|
||||
ring_reg_addr_list[i] +
|
||||
HCLGEVF_RING_REG_OFFSET * j);
|
||||
*reg++ = readl_relaxed(tqp->io_base -
|
||||
HCLGEVF_TQP_REG_OFFSET +
|
||||
ring_reg_addr_list[i]);
|
||||
}
|
||||
|
||||
reg_um = ARRAY_SIZE(tqp_intr_reg_addr_list);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user