From 8c4caab05ff162e2dd9b66a72a21d9605fb143cf Mon Sep 17 00:00:00 2001 From: Khairul Anuar Romli Date: Wed, 3 Dec 2025 07:47:35 +0800 Subject: [PATCH 01/12] arm64: dts: socfpga: agilex5: Add dma-coherent property Add the `dma-coherent` property to these device nodes to inform the kernel and DMA subsystem that the devices support hardware-managed cache coherence. Changes: - Add `dma-coherent` to `cdns,hp-nfc` - Add `dma-coherent` to both `snps,axi-dma-1.01a` instances (dmac0, dmac1) This aligns the Agilex5 device tree with the coherent DMA-capable devices accordingly. Signed-off-by: Khairul Anuar Romli Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index a5c2025a616e..89a2ff59554b 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -312,6 +312,7 @@ nand: nand-controller@10b80000 { clock-names = "nf_clk"; cdns,board-delay-ps = <4830>; iommus = <&smmu 4>; + dma-coherent; status = "disabled"; }; @@ -339,6 +340,7 @@ dmac0: dma-controller@10db0000 { snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; iommus = <&smmu 8>; + dma-coherent; }; dmac1: dma-controller@10dc0000 { @@ -357,6 +359,7 @@ dmac1: dma-controller@10dc0000 { snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; iommus = <&smmu 9>; + dma-coherent; }; rst: rstmgr@10d11000 { From 2bd42d859b093e3a4c71258767c3cac298265993 Mon Sep 17 00:00:00 2001 From: Niravkumar L Rabara Date: Tue, 2 Dec 2025 18:16:51 +0800 Subject: [PATCH 02/12] dt-bindings: intel: Add Agilex5 SoCFPGA modular board Add compatible for Agilex5 SoCFPGA modular board. Signed-off-by: Niravkumar L Rabara Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index c918837bd41c..6b2d88947352 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -32,6 +32,7 @@ properties: - enum: - intel,socfpga-agilex5-socdk - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-modular - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 From ebb6a68a4857107f3574ef058f2b83f3288d0d08 Mon Sep 17 00:00:00 2001 From: Niravkumar L Rabara Date: Tue, 2 Dec 2025 18:16:52 +0800 Subject: [PATCH 03/12] arm64: dts: socfpga: agilex5: add support for modular board The Agilex5 Modular board consists of a compute module (Agilex5 SoCFPGA) attached to a carrier board that provides PCIe and additional system interfaces. Signed-off-by: Niravkumar L Rabara Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/Makefile | 1 + .../intel/socfpga_agilex5_socdk_modular.dts | 109 ++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index a117268267ee..b15e9c5083b6 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex3_socdk.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex5_socdk_013b.dtb \ + socfpga_agilex5_socdk_modular.dtb \ socfpga_agilex5_socdk_nand.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts new file mode 100644 index 000000000000..1831402d8808 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, Altera Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 SoCDK - Modular development kit"; + compatible = "intel,socfpga-agilex5-socdk-modular", "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "hps_led0"; + gpios = <&porta 0x0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0be00000>; + }; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; From 67c1d7894766d3a503e6c48c729f17a9a9dea32c Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Wed, 3 Dec 2025 18:29:00 -0800 Subject: [PATCH 04/12] arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes To enable SMMU integration, populate the iommus property to the ethernet device-tree node. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 89a2ff59554b..db8d5c426821 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -568,6 +568,7 @@ gmac0: ethernet@10810000 { snps,tso; altr,sysmgr-syscon = <&sysmgr 0x44 0>; snps,clk-csr = <0>; + iommus = <&smmu 1>; status = "disabled"; stmmac_axi_emac0_setup: stmmac-axi-config { @@ -680,6 +681,7 @@ gmac1: ethernet@10820000 { snps,tso; altr,sysmgr-syscon = <&sysmgr 0x48 0>; snps,clk-csr = <0>; + iommus = <&smmu 2>; status = "disabled"; stmmac_axi_emac1_setup: stmmac-axi-config { @@ -792,6 +794,7 @@ gmac2: ethernet@10830000 { snps,tso; altr,sysmgr-syscon = <&sysmgr 0x4c 0>; snps,clk-csr = <0>; + iommus = <&smmu 3>; status = "disabled"; stmmac_axi_emac2_setup: stmmac-axi-config { From 1cb8486ac5f3adc0a4f38e8b59962c2314fc2ca5 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 10 Dec 2025 21:59:39 -0600 Subject: [PATCH 05/12] dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml For all SoCFPGA platforms, whether it has the "intel" or "altr" vendor prefix are referring to the same business unit that is responsible for the platform. And now that Altera has spun off to be a separate corporate entity from Intel, it would make sense to have the device bindings documentation in the same file. Move the Intel AgileX board binding documentations into the same file that contains the Altera ones. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/arm/altera.yaml | 26 ++++++++++++ .../bindings/arm/intel,socfpga.yaml | 41 ------------------- 2 files changed, 26 insertions(+), 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/intel,socfpga.yaml diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index db61537b7115..26ab75bc6ed3 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -9,6 +9,9 @@ title: Altera's SoCFPGA platform maintainers: - Dinh Nguyen +description: + Altera/Intel boards with ARM 32/64 bits cores + properties: $nodename: const: "/" @@ -81,6 +84,29 @@ properties: - altr,socfpga-stratix10-swvp - const: altr,socfpga-stratix10 + - description: AgileX boards + items: + - enum: + - intel,n5x-socdk + - intel,socfpga-agilex-n6000 + - intel,socfpga-agilex-socdk + - const: intel,socfpga-agilex + + - description: Agilex3 boards + items: + - enum: + - intel,socfpga-agilex3-socdk + - const: intel,socfpga-agilex3 + - const: intel,socfpga-agilex5 + + - description: Agilex5 boards + items: + - enum: + - intel,socfpga-agilex5-socdk + - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-nand + - const: intel,socfpga-agilex5 + - description: SoCFPGA VT items: - const: altr,socfpga-vt diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml deleted file mode 100644 index 6b2d88947352..000000000000 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ /dev/null @@ -1,41 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel SoCFPGA platform - -maintainers: - - Dinh Nguyen - -properties: - $nodename: - const: "/" - compatible: - oneOf: - - description: AgileX boards - items: - - enum: - - intel,n5x-socdk - - intel,socfpga-agilex-n6000 - - intel,socfpga-agilex-socdk - - const: intel,socfpga-agilex - - description: Agilex3 boards - items: - - enum: - - intel,socfpga-agilex3-socdk - - const: intel,socfpga-agilex3 - - const: intel,socfpga-agilex5 - - description: Agilex5 boards - items: - - enum: - - intel,socfpga-agilex5-socdk - - intel,socfpga-agilex5-socdk-013b - - intel,socfpga-agilex5-socdk-modular - - intel,socfpga-agilex5-socdk-nand - - const: intel,socfpga-agilex5 - -additionalProperties: true - -... From 5acb925409e2f089e6e25212ae64d13dea6b464a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:24:45 +0100 Subject: [PATCH 06/12] arm64: dts: altera: Use lowercase hex The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../boot/dts/altera/socfpga_stratix10.dtsi | 2 +- .../dts/altera/socfpga_stratix10_socdk.dts | 2 +- .../altera/socfpga_stratix10_socdk_nand.dts | 4 +- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 48 +++++++++---------- .../boot/dts/intel/socfpga_agilex_socdk.dts | 2 +- .../boot/dts/intel/socfpga_n5x_socdk.dts | 4 +- 6 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 657e986e5dba..0d9cad0c0351 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -382,7 +382,7 @@ pdma: dma-controller@ffda0000 { pinctrl0: pinctrl@ffd13000 { compatible = "pinctrl-single"; - reg = <0xffd13000 0xA0>; + reg = <0xffd13000 0xa0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x0000000f>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 58f776e411fc..4ae18a013bbe 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -192,7 +192,7 @@ qspi_boot: partition@0 { root: partition@4200000 { label = "Root Filesystem - UBIFS"; - reg = <0x04200000 0x0BE00000>; + reg = <0x04200000 0x0be00000>; }; }; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index 92954c5beb54..7951ce46ae1f 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -174,12 +174,12 @@ partitions { qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; + reg = <0x0 0x03fe0000>; }; qspi_rootfs: partition@3fe0000 { label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; + reg = <0x03fe0000 0x0c020000>; }; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index db8d5c426821..a98bd23c3fa2 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -622,31 +622,31 @@ queue0 { snps,dcb-algorithm; }; queue1 { - snps,weight = <0x0A>; + snps,weight = <0x0a>; snps,dcb-algorithm; }; queue2 { - snps,weight = <0x0B>; + snps,weight = <0x0b>; snps,coe-unsupported; snps,dcb-algorithm; }; queue3 { - snps,weight = <0x0C>; + snps,weight = <0x0c>; snps,coe-unsupported; snps,dcb-algorithm; }; queue4 { - snps,weight = <0x0D>; + snps,weight = <0x0d>; snps,coe-unsupported; snps,dcb-algorithm; }; queue5 { - snps,weight = <0x0E>; + snps,weight = <0x0e>; snps,coe-unsupported; snps,dcb-algorithm; }; queue6 { - snps,weight = <0x0F>; + snps,weight = <0x0f>; snps,coe-unsupported; snps,dcb-algorithm; }; @@ -735,31 +735,31 @@ queue0 { snps,dcb-algorithm; }; queue1 { - snps,weight = <0x0A>; + snps,weight = <0x0a>; snps,dcb-algorithm; }; queue2 { - snps,weight = <0x0B>; + snps,weight = <0x0b>; snps,coe-unsupported; snps,dcb-algorithm; }; queue3 { - snps,weight = <0x0C>; + snps,weight = <0x0c>; snps,coe-unsupported; snps,dcb-algorithm; }; queue4 { - snps,weight = <0x0D>; + snps,weight = <0x0d>; snps,coe-unsupported; snps,dcb-algorithm; }; queue5 { - snps,weight = <0x0E>; + snps,weight = <0x0e>; snps,coe-unsupported; snps,dcb-algorithm; }; queue6 { - snps,weight = <0x0F>; + snps,weight = <0x0f>; snps,coe-unsupported; snps,dcb-algorithm; }; @@ -848,31 +848,31 @@ queue0 { snps,dcb-algorithm; }; queue1 { - snps,weight = <0x0A>; + snps,weight = <0x0a>; snps,dcb-algorithm; }; queue2 { - snps,weight = <0x0B>; + snps,weight = <0x0b>; snps,coe-unsupported; snps,dcb-algorithm; }; queue3 { - snps,weight = <0x0C>; + snps,weight = <0x0c>; snps,coe-unsupported; snps,dcb-algorithm; }; queue4 { - snps,weight = <0x0D>; + snps,weight = <0x0d>; snps,coe-unsupported; snps,dcb-algorithm; }; queue5 { - snps,weight = <0x0E>; + snps,weight = <0x0e>; snps,coe-unsupported; snps,dcb-algorithm; }; queue6 { - snps,weight = <0x0F>; + snps,weight = <0x0f>; snps,coe-unsupported; snps,dcb-algorithm; }; @@ -918,24 +918,24 @@ pmu0_tbu2: pmu@16082000 { pmu0_tbu3: pmu@160a2000 { compatible = "arm,smmu-v3-pmcg"; - reg = <0x160A2000 0x1000>, - <0x160B2000 0x1000>; + reg = <0x160a2000 0x1000>, + <0x160b2000 0x1000>; interrupt-parent = <&intc>; interrupts = ; }; pmu0_tbu4: pmu@160c2000 { compatible = "arm,smmu-v3-pmcg"; - reg = <0x160C2000 0x1000>, - <0x160D2000 0x1000>; + reg = <0x160c2000 0x1000>, + <0x160d2000 0x1000>; interrupt-parent = <&intc>; interrupts = ; }; pmu0_tbu5: pmu@160e2000 { compatible = "arm,smmu-v3-pmcg"; - reg = <0x160E2000 0x1000>, - <0x160F2000 0x1000>; + reg = <0x160e2000 0x1000>, + <0x160f2000 0x1000>; interrupt-parent = <&intc>; interrupts = ; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 9ee312bae8d2..8f8a5423ba02 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -131,7 +131,7 @@ qspi_boot: partition@0 { root: partition@4200000 { label = "Root Filesystem - UBIFS"; - reg = <0x04200000 0x0BE00000>; + reg = <0x04200000 0x0be00000>; }; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 0034a4897220..d7d500f50a07 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -103,12 +103,12 @@ partitions { qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; + reg = <0x0 0x03fe0000>; }; qspi_rootfs: partition@3fe0000 { label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; + reg = <0x03fe0000 0x0c020000>; }; }; }; From 42918d28cb47f1907daa843a68c2abb801f57761 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 26 Dec 2025 07:05:40 -0600 Subject: [PATCH 07/12] dt-bindings: altera: document syscon as fallback for sys-mgr For 32-bit Altera SoCFPGA parts, the sys-mgr uses the syscon as a fallback. This change addresses this warning from dtbs_check: sysmgr@ffd08000 (altr,sys-mgr): compatible: 'oneOf' conditional failed, one must be fixed: ['altr,sys-mgr', 'syscon'] is too long 'altr,sys-mgr-s10' was expected 'altr,sys-mgr' was expected from schema $id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/soc/altera/altr,sys-mgr.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml b/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml index d56ff4c05ae5..2dd3395f3f63 100644 --- a/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml +++ b/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml @@ -13,7 +13,9 @@ properties: compatible: oneOf: - description: Cyclone5/Arria5/Arria10 - const: altr,sys-mgr + items: + - const: altr,sys-mgr + - const: syscon - description: Stratix10 SoC items: - const: altr,sys-mgr-s10 @@ -45,7 +47,7 @@ additionalProperties: false examples: - | sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; + compatible = "altr,sys-mgr", "syscon"; reg = <0xffd08000 0x1000>; cpu1-start-addr = <0xffd080c4>; }; From 6ba5f9b4241b83dd57fe20a63fd66b6273aa95b1 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 26 Dec 2025 15:31:16 -0600 Subject: [PATCH 08/12] ARM: dts: socfpga: add #address-cells and #size-cells for sram node Add #address-cells and #size-cells for sram node to fix below DTB_CHECK warnings: socfpga_arria5_socdk.dtb: sram@ffff0000 (mmio-sram): '#size-cells' is a required property from schema $id: http://devicetree.org/schemas/sram/sram.yaml Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 3 +++ arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi index 35be14150f41..58d9fd0c34f0 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -785,6 +785,9 @@ nand0: nand-controller@ff900000 { ocram: sram@ffff0000 { compatible = "mmio-sram"; reg = <0xffff0000 0x10000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; }; qspi: spi@ff705000 { diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index b108265e9bde..4df2b98a3e59 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -686,6 +686,9 @@ nand: nand-controller@ffb90000 { ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; }; eccmgr: eccmgr { From e0f489a52a1a5f9a9ce745feec95d0b517b8d6e9 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sat, 27 Dec 2025 16:14:08 -0600 Subject: [PATCH 09/12] ARM: dts: socfpga: fix dtbs_check warning for fpga-region soc (simple-bus): base_fpga_region: 'ranges' is a required property from schema $id: http://devicetree.org/schemas/simple-bus.yaml base_fpga_region (fpga-region): $nodename:0: 'base_fpga_region' does not match '^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$' from schema $id: http://devicetree.org/schemas/fpga/fpga-region.yaml Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 3 ++- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi index 58d9fd0c34f0..5dc8d33e8ad7 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -87,12 +87,13 @@ pdma: pdma@ffe01000 { }; }; - base_fpga_region { + base_fpga_region: fpga-region { compatible = "fpga-region"; fpga-mgr = <&fpgamgr0>; #address-cells = <0x1>; #size-cells = <0x1>; + ranges; }; can0: can@ffc00000 { diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 4df2b98a3e59..a53a94678df2 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -80,12 +80,13 @@ pdma: pdma@ffda1000 { }; }; - base_fpga_region { + base_fpga_region: fpga-region { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "fpga-region"; fpga-mgr = <&fpga_mgr>; + ranges; }; clkmgr@ffd04000 { From 4e6e93dfd501a16650806e7a39aa7b5203867276 Mon Sep 17 00:00:00 2001 From: Khairul Anuar Romli Date: Mon, 29 Dec 2025 11:49:02 +0800 Subject: [PATCH 10/12] arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node Move dma-controller node under simple-bus node to allow bus node specific property able to be properly defined. This is require to fulfill Agilex5 bus limitation that is limited to 40-addressable-bit. Update the compatible string for the DMA controller nodes in the Agilex5 device tree from the generic "snps,axi-dma-1.01a" to the platform-specific "altr,agilex5-axi-dma". Add fallback capability to ensure driver is able to initialize properly. This change enables the use of platform-specific features and constraints in the driver, such as setting a 40-bit DMA addressable mask through dma-ranges, which is required for Agilex5. It also aligns with the updated device tree bindings and driver support for this compatible string. Signed-off-by: Khairul Anuar Romli Signed-off-by: Dinh Nguyen --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 78 ++++++++++--------- 1 file changed, 43 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index a98bd23c3fa2..352c96d144a8 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -324,42 +324,50 @@ ocram: sram@0 { #size-cells = <1>; }; - dmac0: dma-controller@10db0000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x10db0000 0x500>; - clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, - <&clkmgr AGILEX5_L4_MP_CLK>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = ; - #dma-cells = <1>; - dma-channels = <4>; - snps,dma-masters = <1>; - snps,data-width = <2>; - snps,block-size = <32767 32767 32767 32767>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <8>; - iommus = <&smmu 8>; - dma-coherent; - }; + dma: dma-bus@10db0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <2>; + ranges = <0x00 0x10db0000 0x00 0x20000>; + dma-ranges = <0x00 0x00 0x100 0x00>; - dmac1: dma-controller@10dc0000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x10dc0000 0x500>; - clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, - <&clkmgr AGILEX5_L4_MP_CLK>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = ; - #dma-cells = <1>; - dma-channels = <4>; - snps,dma-masters = <1>; - snps,data-width = <2>; - snps,block-size = <32767 32767 32767 32767>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <8>; - iommus = <&smmu 9>; - dma-coherent; + dmac0: dma-controller@0 { + compatible = "altr,agilex5-axi-dma", + "snps,axi-dma-1.01a"; + reg = <0x0 0x0 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = ; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + iommus = <&smmu 8>; + }; + + dmac1: dma-controller@10000 { + compatible = "altr,agilex5-axi-dma", + "snps,axi-dma-1.01a"; + reg = <0x10000 0x0 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = ; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + iommus = <&smmu 9>; + }; }; rst: rstmgr@10d11000 { From 95cc767d6f54e48629b593edc2ccbd154ec65d95 Mon Sep 17 00:00:00 2001 From: Ng Tze Yee Date: Sun, 25 Jan 2026 22:42:05 -0800 Subject: [PATCH 11/12] arm64: dts: socfpga: agilex: add emmc support The Agilex devkit supports a separate eMMC daughter card. The eMMC daughter card replaces the SDMMC slot that is on the default daughter card and thus requires a separate board dts file. Signed-off-by: Ng Tze Yee Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/Makefile | 1 + .../dts/intel/socfpga_agilex_socdk_emmc.dts | 105 ++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index b15e9c5083b6..33fcc55d0cb9 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ + socfpga_agilex_socdk_emmc.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_agilex3_socdk.dtb \ socfpga_agilex5_socdk.dtb \ diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts new file mode 100644 index 000000000000..1d3a2d7d48c0 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Altera Corporation + */ +#include "socfpga_agilex.dtsi" + +/ { + model = "SoCFPGA Agilex SoCDK eMMC daughter board"; + compatible = "intel,socfpga-agilex-socdk-emmc", "intel,socfpga-agilex"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + led0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + led2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac2 { + status = "okay"; + /* PHY delays is configured via skew properties */ + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@4 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; From 4d904af4d6ce29b9240ebecd35e31458d08cd577 Mon Sep 17 00:00:00 2001 From: Ng Tze Yee Date: Fri, 30 Jan 2026 09:46:57 -0600 Subject: [PATCH 12/12] dt-bindings: intel: Add Agilex eMMC support Agilex devkit support a separate eMMC daughter card. Document Agilex eMMC daughter board compatible. [dinguyen] becauce of patch 1cb8486ac5f3 ("dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml"), I moved the change to altera.yaml file. Acked-by: Krzysztof Kozlowski Signed-off-by: Ng Tze Yee Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 26ab75bc6ed3..13a3a9696821 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -90,6 +90,7 @@ properties: - intel,n5x-socdk - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk + - intel,socfpga-agilex-socdk-emmc - const: intel,socfpga-agilex - description: Agilex3 boards