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arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700
Add support for Grinn GenioSBC-700. The Grinn GenioSBC-700 is a single-board computer based on the MediaTek Genio 700 SoC. Its device tree is split into separate SoM (.dtsi) and SBC (.dtsi) files, which are combined in the SoC-specific .dts file. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Mateusz Koza
AngeloGioacchino Del Regno
parent
6bb220964d
commit
f4d1eace54
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@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo
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20
arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts
Normal file
20
arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts
Normal file
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@ -0,0 +1,20 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2025 Grinn sp. z o.o.
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* Author: Mateusz Koza <mateusz.koza@grinn-global.com>
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*/
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/dts-v1/;
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#include "mt8188.dtsi"
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#include "mt8390-grinn-genio-som.dtsi"
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#include "mt8390-grinn-genio-sbc.dtsi"
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/ {
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model = "Grinn GenioSBC-700";
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compatible = "grinn,genio-700-sbc", "mediatek,mt8390", "mediatek,mt8188";
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 1 0x00000000>;
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};
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};
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538
arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi
Normal file
538
arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi
Normal file
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@ -0,0 +1,538 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2025 Grinn sp. z o.o.
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* Author: Mateusz Koza <mateusz.koza@grinn-global.com>
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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chassis-type = "embedded";
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aliases {
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ethernet0 = ð
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i2c0 = &i2c0;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:921600n8";
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/*
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* 12 MiB reserved for OP-TEE (BL32)
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* +-----------------------+ 0x43e0_0000
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* | SHMEM 2MiB |
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* +-----------------------+ 0x43c0_0000
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* | | TA_RAM 8MiB |
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* + TZDRAM +--------------+ 0x4340_0000
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* | | TEE_RAM 2MiB |
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* +-----------------------+ 0x4320_0000
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*/
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optee_reserved: optee@43200000 {
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no-map;
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reg = <0 0x43200000 0 0x00c00000>;
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};
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scp_mem: memory@50000000 {
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compatible = "shared-dma-pool";
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reg = <0 0x50000000 0 0x2900000>;
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no-map;
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};
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/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
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bl31_secmon_reserved: memory@54600000 {
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no-map;
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reg = <0 0x54600000 0x0 0x200000>;
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};
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apu_mem: memory@55000000 {
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compatible = "shared-dma-pool";
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reg = <0 0x55000000 0 0x1400000>; /* 20 MB */
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};
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vpu_mem: memory@57000000 {
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compatible = "shared-dma-pool";
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reg = <0 0x57000000 0 0x1400000>; /* 20 MB */
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};
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adsp_mem: memory@60000000 {
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compatible = "shared-dma-pool";
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reg = <0 0x60000000 0 0xf00000>;
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no-map;
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};
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afe_dma_mem: memory@60f00000 {
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compatible = "shared-dma-pool";
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reg = <0 0x60f00000 0 0x100000>;
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no-map;
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};
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adsp_dma_mem: memory@61000000 {
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compatible = "shared-dma-pool";
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reg = <0 0x61000000 0 0x100000>;
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no-map;
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};
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};
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reg_sbc_vsys: regulator-vsys {
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compatible = "regulator-fixed";
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regulator-name = "vsys";
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regulator-always-on;
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regulator-boot-on;
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};
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reg_fixed_5v: regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-5v0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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regulator-always-on;
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vin-supply = <®_sbc_vsys>;
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};
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reg_fixed_4v2: regulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-4v2";
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regulator-min-microvolt = <4200000>;
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regulator-max-microvolt = <4200000>;
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enable-active-high;
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regulator-always-on;
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vin-supply = <®_sbc_vsys>;
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};
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reg_fixed_3v3: regulator-2 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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regulator-always-on;
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vin-supply = <®_sbc_vsys>;
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};
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};
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&pio {
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gpio-line-names =
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/* 0 - 4 */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4",
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/* 5 - 9 */ "", "RPI_GPIO6", "", "", "RPI_GPIO9",
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/* 10 - 14 */ "RPI_GPIO10", "RPI_GPIO11", "", "", "",
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/* 15 - 19 */ "", "", "", "", "",
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/* 20 - 24 */ "", "RPI_GPIO21", "", "RPI_GPIO23", "",
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/* 25 - 29 */ "", "", "", "", "",
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/* 30 - 34 */ "RPI_GPIO30", "", "", "", "",
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/* 35 - 39 */ "RPI_GPIO35", "RPI_GPIO36", "", "", "",
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/* 40 - 44 */ "", "", "", "", "",
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/* 45 - 49 */ "", "", "", "", "",
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/* 50 - 54 */ "", "", "", "", "",
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/* 55 - 59 */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59",
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/* 60 - 64 */ "RPI_GPIO60", "", "", "", "",
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/* 65 - 69 */ "", "", "", "", "RPI_GPIO69",
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/* 70 - 74 */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74",
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/* 75 - 79 */ "", "", "", "", "RPI_GPIO79",
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/* 80 - 84 */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "",
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/* 85 - 89 */ "", "", "", "", "",
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/* 90 - 94 */ "", "", "", "", "",
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/* 95 - 99 */ "", "", "", "", "",
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/*100 - 104 */ "", "", "", "", "",
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/*105 - 109 */ "", "", "", "", "",
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/*110 - 114 */ "", "", "", "", "",
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/*115 - 119 */ "", "", "", "", "",
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/*120 - 124 */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPIO124";
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i2c0_pins: i2c0-pins {
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pins {
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pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
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<PINMUX_GPIO55__FUNC_B1_SCL0>;
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bias-pull-up = <MTK_PULL_SET_RSEL_011>;
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drive-strength-microamp = <1000>;
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};
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};
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i2c2_pins: i2c2-pins {
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pins {
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pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
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<PINMUX_GPIO59__FUNC_B1_SCL2>;
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bias-pull-up = <MTK_PULL_SET_RSEL_011>;
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drive-strength-microamp = <1000>;
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};
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};
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i2c3_pins: i2c3-pins {
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pins {
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pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
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<PINMUX_GPIO61__FUNC_B1_SCL3>;
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bias-pull-up = <MTK_PULL_SET_RSEL_011>;
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drive-strength-microamp = <1000>;
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};
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};
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i2c5_pins: i2c5-pins {
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pins {
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pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
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<PINMUX_GPIO65__FUNC_B1_SCL5>;
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bias-pull-up = <MTK_PULL_SET_RSEL_011>;
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drive-strength-microamp = <1000>;
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};
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};
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i2c6_pins: i2c6-pins {
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pins {
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pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
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<PINMUX_GPIO67__FUNC_B1_SCL6>;
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bias-pull-up = <MTK_PULL_SET_RSEL_011>;
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drive-strength-microamp = <1000>;
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};
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};
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uart0_pins: uart0-pins {
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pins {
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pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
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<PINMUX_GPIO32__FUNC_I1_URXD0>;
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bias-pull-up;
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};
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};
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uart1_pins: uart1-pins {
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pins {
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pinmux = <PINMUX_GPIO86__FUNC_O_UTXD1>,
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<PINMUX_GPIO87__FUNC_I1_URXD1>;
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bias-pull-up;
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};
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};
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uart2_pins: uart2-pins {
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pins {
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pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>,
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<PINMUX_GPIO36__FUNC_I1_URXD2>;
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bias-pull-up;
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};
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};
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pcie_pins_default: pcie-default {
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mux {
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pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
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<PINMUX_GPIO48__FUNC_O_PERSTN>,
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<PINMUX_GPIO49__FUNC_B1_CLKREQN>;
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bias-pull-up;
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};
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};
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eth_default_pins: eth-default-pins {
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pins-cc {
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pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>,
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<PINMUX_GPIO140__FUNC_I0_GBE_RXC>,
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<PINMUX_GPIO141__FUNC_I0_GBE_RXDV>,
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<PINMUX_GPIO142__FUNC_O_GBE_TXEN>;
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drive-strength = <8>;
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};
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pins-mdio {
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pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>,
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<PINMUX_GPIO144__FUNC_B1_GBE_MDIO>;
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drive-strength = <8>;
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input-enable;
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};
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pins-power {
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pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>,
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<PINMUX_GPIO146__FUNC_B_GPIO146>;
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output-high;
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};
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pins-rxd {
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pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>,
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<PINMUX_GPIO136__FUNC_I0_GBE_RXD2>,
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<PINMUX_GPIO137__FUNC_I0_GBE_RXD1>,
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<PINMUX_GPIO138__FUNC_I0_GBE_RXD0>;
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drive-strength = <8>;
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};
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pins-txd {
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pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>,
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<PINMUX_GPIO132__FUNC_O_GBE_TXD2>,
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<PINMUX_GPIO133__FUNC_O_GBE_TXD1>,
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<PINMUX_GPIO134__FUNC_O_GBE_TXD0>;
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drive-strength = <8>;
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};
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};
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eth_sleep_pins: eth-sleep-pins {
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pins-cc {
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pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>,
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<PINMUX_GPIO140__FUNC_B_GPIO140>,
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<PINMUX_GPIO141__FUNC_B_GPIO141>,
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<PINMUX_GPIO142__FUNC_B_GPIO142>;
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};
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pins-mdio {
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pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>,
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<PINMUX_GPIO144__FUNC_B_GPIO144>;
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input-disable;
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bias-disable;
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};
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pins-rxd {
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pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>,
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<PINMUX_GPIO136__FUNC_B_GPIO136>,
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<PINMUX_GPIO137__FUNC_B_GPIO137>,
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<PINMUX_GPIO138__FUNC_B_GPIO138>;
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};
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pins-txd {
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pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>,
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<PINMUX_GPIO132__FUNC_B_GPIO132>,
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<PINMUX_GPIO133__FUNC_B_GPIO133>,
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<PINMUX_GPIO134__FUNC_B_GPIO134>;
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};
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};
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spi2_pins: spi2-pins {
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pins-spi {
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pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
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<PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
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<PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
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<PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
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bias-disable;
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};
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};
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audio_default_pins: audio-default-pins {
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pins-cmd-dat {
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pinmux = <PINMUX_GPIO121__FUNC_B0_PCM_CLK>,
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<PINMUX_GPIO122__FUNC_B0_PCM_SYNC>,
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<PINMUX_GPIO123__FUNC_O_PCM_DO>,
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<PINMUX_GPIO124__FUNC_I0_PCM_DI>;
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};
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};
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usb_default_pins: usb-default-pins {
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pins-valid {
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pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>;
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input-enable;
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};
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};
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};
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ð {
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <ð_default_pins>;
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pinctrl-1 = <ð_sleep_pins>;
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mediatek,mac-wol;
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mediatek,tx-delay-ps = <30>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 11000 200000>;
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snps,reset-gpio = <&pio 147 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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ð_mdio {
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ethernet_phy0: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>;
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eee-broken-1000t;
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};
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins>;
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c5 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_pins>;
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c6 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_pins>;
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clock-frequency = <400000>;
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status = "okay";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pciephy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_pins>;
|
||||
mediatek,pad-select = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u3phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u3phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u3phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xhci1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
vusb33-supply = <&mt6359_vusb_ldo_reg>;
|
||||
status = "okay";
|
||||
|
||||
hub_2_0: hub@1 {
|
||||
compatible = "usb451,8027";
|
||||
reg = <1>;
|
||||
peer-hub = <&hub_3_0>;
|
||||
reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
|
||||
vdd-supply = <®_fixed_3v3>;
|
||||
};
|
||||
|
||||
hub_3_0: hub@2 {
|
||||
compatible = "usb451,8025";
|
||||
reg = <2>;
|
||||
peer-hub = <&hub_2_0>;
|
||||
reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
|
||||
vdd-supply = <®_fixed_3v3>;
|
||||
};
|
||||
};
|
||||
|
||||
&xhci2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
vusb33-supply = <&mt6359_vusb_ldo_reg>;
|
||||
status = "okay";
|
||||
|
||||
hub@1 {
|
||||
compatible = "microchip,usb2513bi";
|
||||
reg = <1>;
|
||||
vdd-supply = <®_fixed_3v3>;
|
||||
};
|
||||
};
|
||||
|
||||
&ssusb0 {
|
||||
dr_mode = "peripheral";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_default_pins>;
|
||||
vusb33-supply = <&mt6359_vusb_ldo_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb1 {
|
||||
dr_mode = "host";
|
||||
maximum-speed = "super-speed";
|
||||
vusb33-supply = <&mt6359_vusb_ldo_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb2 {
|
||||
dr_mode = "host";
|
||||
maximum-speed = "high-speed";
|
||||
vusb33-supply = <&mt6359_vusb_ldo_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scp_cluster {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scp_c0 {
|
||||
memory-region = <&scp_mem>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&mt6359_vproc2_buck_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&adsp {
|
||||
memory-region = <&adsp_dma_mem>, <&adsp_mem>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&afe {
|
||||
memory-region = <&afe_dma_mem>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sound {
|
||||
compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb";
|
||||
model = "mt8390-evk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&audio_default_pins>;
|
||||
audio-routing =
|
||||
"Headphone", "Headphone L",
|
||||
"Headphone", "Headphone R",
|
||||
"AP DMIC", "AUDGLB",
|
||||
"AP DMIC", "MIC_BIAS_0",
|
||||
"AP DMIC", "MIC_BIAS_2",
|
||||
"DMIC_INPUT", "AP DMIC";
|
||||
|
||||
mediatek,adsp = <&adsp>;
|
||||
status = "okay";
|
||||
};
|
||||
210
arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi
Normal file
210
arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi
Normal file
|
|
@ -0,0 +1,210 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2025 Grinn sp. z o.o.
|
||||
* Author: Mateusz Koza <mateusz.koza@grinn-global.com>
|
||||
*/
|
||||
|
||||
#include "mt6359.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &mmc0;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mfg0 {
|
||||
domain-supply = <&mt6359_vproc2_buck_reg>;
|
||||
};
|
||||
|
||||
&mfg1 {
|
||||
domain-supply = <&mt6359_vsram_others_ldo_reg>;
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&mmc0_default_pins>;
|
||||
pinctrl-1 = <&mmc0_uhs_pins>;
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
supports-cqe;
|
||||
cap-mmc-hw-reset;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
hs400-ds-delay = <0x1481b>;
|
||||
vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
|
||||
vqmmc-supply = <&mt6359_vufs_ldo_reg>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
&mt6359_vbbck_ldo_reg {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mt6359_vcn18_ldo_reg {
|
||||
regulator-name = "vcn18_pmu";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mt6359_vcn33_2_bt_ldo_reg {
|
||||
regulator-name = "vcn33_2_pmu";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mt6359_vcore_buck_reg {
|
||||
regulator-name = "dvdd_proc_l";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mt6359_vgpu11_buck_reg {
|
||||
regulator-name = "dvdd_core";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mt6359_vpa_buck_reg {
|
||||
regulator-name = "vpa_pmu";
|
||||
regulator-max-microvolt = <3100000>;
|
||||
};
|
||||
|
||||
&mt6359_vproc2_buck_reg {
|
||||
/* The name "vgpu" is required by mtk-regulator-coupler */
|
||||
regulator-name = "vgpu";
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
|
||||
regulator-coupled-max-spread = <6250>;
|
||||
};
|
||||
|
||||
&mt6359_vpu_buck_reg {
|
||||
regulator-name = "dvdd_adsp";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mt6359_vrf12_ldo_reg {
|
||||
regulator-name = "va12_abb2_pmu";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mt6359_vsim1_ldo_reg {
|
||||
regulator-name = "vsim1_pmu";
|
||||
regulator-enable-ramp-delay = <480>;
|
||||
};
|
||||
|
||||
&mt6359_vsram_others_ldo_reg {
|
||||
/* The name "vsram_gpu" is required by mtk-regulator-coupler */
|
||||
regulator-name = "vsram_gpu";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-coupled-with = <&mt6359_vproc2_buck_reg>;
|
||||
regulator-coupled-max-spread = <6250>;
|
||||
};
|
||||
|
||||
&mt6359_vufs_ldo_reg {
|
||||
regulator-name = "vufs18_pmu";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&pio {
|
||||
|
||||
i2c1_pins: i2c1-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
|
||||
<PINMUX_GPIO57__FUNC_B1_SCL1>;
|
||||
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
|
||||
drive-strength-microamp = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_default_pins: mmc0-default-pins {
|
||||
pins-clk {
|
||||
pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
|
||||
drive-strength = <6>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins-cmd-dat {
|
||||
pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
|
||||
<PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
|
||||
<PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
|
||||
<PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
|
||||
<PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
|
||||
<PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
|
||||
<PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
|
||||
<PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
|
||||
<PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <6>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
pins-rst {
|
||||
pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
|
||||
drive-strength = <6>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_uhs_pins: mmc0-uhs-pins {
|
||||
pins-clk {
|
||||
pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
|
||||
drive-strength = <8>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins-cmd-dat {
|
||||
pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
|
||||
<PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
|
||||
<PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
|
||||
<PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
|
||||
<PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
|
||||
<PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
|
||||
<PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
|
||||
<PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
|
||||
<PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <8>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
pins-ds {
|
||||
pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>;
|
||||
drive-strength = <8>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins-rst {
|
||||
pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
|
||||
drive-strength = <8>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmic {
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
keys {
|
||||
compatible = "mediatek,mt6359-keys";
|
||||
mediatek,long-press-mode = <1>;
|
||||
power-off-time-sec = <0>;
|
||||
|
||||
power-key {
|
||||
linux,keycodes = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user