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fbdev: remove s3c2410 framebuffer
The s3c24xx platform was removed, so the framebuffer driver is no longer needed. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
014e79d7ec
commit
f48fd50b03
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@ -1896,19 +1896,17 @@ config FB_TMIO_ACCELL
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config FB_S3C
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tristate "Samsung S3C framebuffer support"
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depends on FB && HAVE_CLK && HAS_IOMEM
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depends on (CPU_S3C2416 || ARCH_S3C64XX) || COMPILE_TEST
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depends on ARCH_S3C64XX || COMPILE_TEST
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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help
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Frame buffer driver for the built-in FB controller in the Samsung
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SoC line from the S3C2443 onwards, including the S3C2416, S3C2450,
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and the S3C64XX series such as the S3C6400 and S3C6410.
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SoC line such as the S3C6400 and S3C6410.
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These chips all have the same basic framebuffer design with the
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actual capabilities depending on the chip. For instance the S3C6400
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and S3C6410 support 4 hardware windows whereas the S3C24XX series
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currently only have two.
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actual capabilities depending on the chip. The S3C6400
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and S3C6410 support 4 hardware windows.
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Currently the support is only for the S3C6400 and S3C6410 SoCs.
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@ -1918,29 +1916,6 @@ config FB_S3C_DEBUG_REGWRITE
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help
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Show all register writes via pr_debug()
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config FB_S3C2410
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tristate "S3C2410 LCD framebuffer support"
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depends on FB && ARCH_S3C24XX
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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help
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Frame buffer driver for the built-in LCD controller in the Samsung
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S3C2410 processor.
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This driver is also available as a module ( = code which can be
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inserted and removed from the running kernel whenever you want). The
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module will be called s3c2410fb. If you want to compile it as a module,
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say M here and read <file:Documentation/kbuild/modules.rst>.
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If unsure, say N.
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config FB_S3C2410_DEBUG
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bool "S3C2410 lcd debug messages"
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depends on FB_S3C2410
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help
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Turn on debugging messages. Note that you can set/unset at run time
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through sysfs
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config FB_SM501
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tristate "Silicon Motion SM501 framebuffer support"
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depends on FB && MFD_SM501
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@ -100,7 +100,6 @@ obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
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obj-$(CONFIG_FB_SH7760) += sh7760fb.o
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obj-$(CONFIG_FB_IMX) += imxfb.o
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obj-$(CONFIG_FB_S3C) += s3c-fb.o
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obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
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obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o
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obj-$(CONFIG_FB_COBALT) += cobalt_lcdfb.o
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obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o
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@ -1,143 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*/
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#ifndef ___ASM_ARCH_REGS_LCD_H
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#define ___ASM_ARCH_REGS_LCD_H
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/*
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* a couple of values are used as platform data in
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* include/linux/platform_data/fb-s3c2410.h and not
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* duplicated here.
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*/
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#include <linux/platform_data/fb-s3c2410.h>
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#define S3C2410_LCDREG(x) (x)
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/* LCD control registers */
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#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00)
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#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04)
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#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08)
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#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C)
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#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10)
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#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
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#define S3C2410_LCDCON1_MMODE (1<<7)
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#define S3C2410_LCDCON1_DSCAN4 (0<<5)
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#define S3C2410_LCDCON1_STN4 (1<<5)
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#define S3C2410_LCDCON1_STN8 (2<<5)
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#define S3C2410_LCDCON1_TFT (3<<5)
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#define S3C2410_LCDCON1_STN1BPP (0<<1)
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#define S3C2410_LCDCON1_STN2GREY (1<<1)
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#define S3C2410_LCDCON1_STN4GREY (2<<1)
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#define S3C2410_LCDCON1_STN8BPP (3<<1)
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#define S3C2410_LCDCON1_STN12BPP (4<<1)
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#define S3C2410_LCDCON1_ENVID (1)
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#define S3C2410_LCDCON1_MODEMASK 0x1E
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#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
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#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
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#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
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#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
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#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
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#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
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#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
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#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
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#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
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#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
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#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
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#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
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#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
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#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
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/* LDCCON4 changes for STN mode on the S3C2412 */
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#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
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#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
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#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
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#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
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/* framebuffer start addressed */
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#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14)
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#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18)
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#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C)
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#define S3C2410_LCDBANK(x) ((x) << 21)
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#define S3C2410_LCDBASEU(x) (x)
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#define S3C2410_OFFSIZE(x) ((x) << 11)
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#define S3C2410_PAGEWIDTH(x) (x)
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/* colour lookup and miscellaneous controls */
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#define S3C2410_REDLUT S3C2410_LCDREG(0x20)
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#define S3C2410_GREENLUT S3C2410_LCDREG(0x24)
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#define S3C2410_BLUELUT S3C2410_LCDREG(0x28)
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#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
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#define S3C2410_TPAL S3C2410_LCDREG(0x50)
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#define S3C2410_TPAL_EN (1<<24)
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/* interrupt info */
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#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
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#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
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#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
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#define S3C2410_LCDINT_FIWSEL (1<<2)
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#define S3C2410_LCDINT_FRSYNC (1<<1)
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#define S3C2410_LCDINT_FICNT (1<<0)
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/* s3c2442 extra stn registers */
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#define S3C2442_REDLUT S3C2410_LCDREG(0x20)
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#define S3C2442_GREENLUT S3C2410_LCDREG(0x24)
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#define S3C2442_BLUELUT S3C2410_LCDREG(0x28)
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#define S3C2442_DITHMODE S3C2410_LCDREG(0x20)
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#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
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#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
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/* S3C2412 registers */
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#define S3C2412_TPAL S3C2410_LCDREG(0x20)
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#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24)
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#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28)
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#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C)
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#define S3C2412_TCONSEL S3C2410_LCDREG(0x30)
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#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34)
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#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38)
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#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C)
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#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40)
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#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4))
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#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
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#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4))
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#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
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/* general registers */
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/* base of the LCD registers, where INTPND, INTSRC and then INTMSK
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* are available. */
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#define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54)
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#define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24)
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#define S3C24XX_LCDINTPND (0x00)
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#define S3C24XX_LCDSRCPND (0x04)
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#define S3C24XX_LCDINTMSK (0x08)
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#endif /* ___ASM_ARCH_REGS_LCD_H */
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File diff suppressed because it is too large
Load Diff
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@ -1,48 +0,0 @@
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/*
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* linux/drivers/video/s3c2410fb.h
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* Copyright (c) 2004 Arnaud Patard
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*
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* S3C2410 LCD Framebuffer Driver
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*
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*/
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#ifndef __S3C2410FB_H
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#define __S3C2410FB_H
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enum s3c_drv_type {
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DRV_S3C2410,
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DRV_S3C2412,
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};
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struct s3c2410fb_info {
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struct device *dev;
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struct clk *clk;
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struct resource *mem;
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void __iomem *io;
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void __iomem *irq_base;
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enum s3c_drv_type drv_type;
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struct s3c2410fb_hw regs;
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unsigned long clk_rate;
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unsigned int palette_ready;
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#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
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struct notifier_block freq_transition;
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#endif
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/* keep these registers in case we need to re-write palette */
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u32 palette_buffer[256];
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u32 pseudo_pal[16];
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};
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#define PALETTE_BUFF_CLEAR (0x80000000) /* entry is clear/invalid */
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int s3c2410fb_init(void);
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#endif
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@ -1,99 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
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*
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* Inspired by pxafb.h
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*/
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#ifndef __ASM_PLAT_FB_S3C2410_H
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#define __ASM_PLAT_FB_S3C2410_H __FILE__
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#include <linux/compiler_types.h>
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struct s3c2410fb_hw {
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unsigned long lcdcon1;
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unsigned long lcdcon2;
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unsigned long lcdcon3;
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unsigned long lcdcon4;
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unsigned long lcdcon5;
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};
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/* LCD description */
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struct s3c2410fb_display {
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/* LCD type */
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unsigned type;
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#define S3C2410_LCDCON1_DSCAN4 (0<<5)
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#define S3C2410_LCDCON1_STN4 (1<<5)
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#define S3C2410_LCDCON1_STN8 (2<<5)
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#define S3C2410_LCDCON1_TFT (3<<5)
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#define S3C2410_LCDCON1_TFT1BPP (8<<1)
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#define S3C2410_LCDCON1_TFT2BPP (9<<1)
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#define S3C2410_LCDCON1_TFT4BPP (10<<1)
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#define S3C2410_LCDCON1_TFT8BPP (11<<1)
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#define S3C2410_LCDCON1_TFT16BPP (12<<1)
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#define S3C2410_LCDCON1_TFT24BPP (13<<1)
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/* Screen size */
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unsigned short width;
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unsigned short height;
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/* Screen info */
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unsigned short xres;
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unsigned short yres;
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unsigned short bpp;
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unsigned pixclock; /* pixclock in picoseconds */
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unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */
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unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
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unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */
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unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */
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unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */
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unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */
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/* lcd configuration registers */
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unsigned long lcdcon5;
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#define S3C2410_LCDCON5_BPP24BL (1<<12)
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#define S3C2410_LCDCON5_FRM565 (1<<11)
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#define S3C2410_LCDCON5_INVVCLK (1<<10)
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#define S3C2410_LCDCON5_INVVLINE (1<<9)
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#define S3C2410_LCDCON5_INVVFRAME (1<<8)
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#define S3C2410_LCDCON5_INVVD (1<<7)
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#define S3C2410_LCDCON5_INVVDEN (1<<6)
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#define S3C2410_LCDCON5_INVPWREN (1<<5)
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#define S3C2410_LCDCON5_INVLEND (1<<4)
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#define S3C2410_LCDCON5_PWREN (1<<3)
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#define S3C2410_LCDCON5_ENLEND (1<<2)
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#define S3C2410_LCDCON5_BSWP (1<<1)
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#define S3C2410_LCDCON5_HWSWP (1<<0)
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};
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struct s3c2410fb_mach_info {
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struct s3c2410fb_display *displays; /* attached displays info */
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unsigned num_displays; /* number of defined displays */
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unsigned default_display;
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/* GPIOs */
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unsigned long gpcup;
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unsigned long gpcup_mask;
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unsigned long gpccon;
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unsigned long gpccon_mask;
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unsigned long gpdup;
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unsigned long gpdup_mask;
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unsigned long gpdcon;
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unsigned long gpdcon_mask;
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void __iomem * gpccon_reg;
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void __iomem * gpcup_reg;
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void __iomem * gpdcon_reg;
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void __iomem * gpdup_reg;
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/* lpc3600 control register */
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unsigned long lpcsel;
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};
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extern void s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
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#endif /* __ASM_PLAT_FB_S3C2410_H */
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