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arm64: dts: imx93-phyboard-nash: Add PEB-WLBT-07 overlay

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Add overlay to support PHYTEC PEB-WLBT-07 WiFi/Bluetooth evaluation
adapter on phyBOARD-Nash-i.MX93 board. Adapter uses the u-blox MAYA-W2
module (IW612 chipset) which is capable of Wi-Fi 6 and Bluetooth 5.4 LE.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Primoz Fiser 2025-07-08 06:22:06 +02:00 committed by Shawn Guo
parent 6696cc94f3
commit f478e7ae18
2 changed files with 90 additions and 0 deletions
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2
arch/arm64/boot/dts/freescale/Makefile
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@ -333,9 +333,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
imx93-phyboard-nash-peb-wlbt-07-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-peb-wlbt-07.dtbo
imx93-phyboard-segin-peb-eval-01-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-eval-01.dtbo
imx93-phyboard-segin-peb-wlbt-05-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-wlbt-05.dtbo
imx93-phycore-rpmsg-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-segin.dtb imx93-phycore-rpmsg.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-peb-wlbt-07.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-eval-01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-wlbt-05.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb

88
arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso Normal file
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@ -0,0 +1,88 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Primoz Fiser <primoz.fiser@norik.com>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx93-pinfunc.h"
&{/} {
usdhc3_pwrseq: usdhc3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
};
};
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
/*
* NOTE: When uSDHC3 port is multiplexed on GPIO_IO[27:22] pads, it only
* supports 50 MHz mode, due to introduction of potential variations in
* trace impedance, drive strength, and timing skew. Refer to i.MX 93
* Application Processors Data Sheet, Rev. 3, page 60 for more details.
*/
&usdhc3 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wlbt>;
pinctrl-1 = <&pinctrl_usdhc3_sleep>, <&pinctrl_wlbt>;
mmc-pwrseq = <&usdhc3_pwrseq>;
bus-width = <4>;
keep-power-in-suspend;
non-removable;
wakeup-source;
status = "okay";
};
&iomuxc {
pinctrl_uart5: uart5grp {
fsl,pins = <
MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX93_PAD_GPIO_IO22__USDHC3_CLK 0x179e
MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000178e
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e
>;
};
pinctrl_usdhc3_sleep: usdhc3sleepgrp {
fsl,pins = <
MX93_PAD_GPIO_IO22__USDHC3_CLK 0x31e
MX93_PAD_SD3_CMD__USDHC3_CMD 0x31e
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x31e
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x31e
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x31e
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x31e
>;
};
pinctrl_wlbt: wlbtgrp {
fsl,pins = <
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e /* WAKE_DEV */
MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e /* WAKE_HOST */
MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e /* PDn */
>;
};
};