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drm/amdgpu: Use correct gfx deferred error count

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In the case of parsing GFX deferred error from SMU corrected error
channel, the error count should be set to 1 instead of parsing from
MISC0 register, which is 0.

Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiang Liu 2025-03-21 20:47:23 +08:00 committed by Alex Deucher
parent 704bc361e3
commit f3f05a0ec5
1 changed files with 4 additions and 3 deletions
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7
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
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@ -872,9 +872,10 @@ static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle,
break;
case ACA_SMU_TYPE_CE:
bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank);
ret = aca_error_cache_log_bank_error(handle, &info,
bank->aca_err_type,
ACA_REG__MISC0__ERRCNT(misc0));
ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,
(bank->aca_err_type == ACA_ERROR_TYPE_CE) ?
ACA_REG__MISC0__ERRCNT(misc0) :
1);
break;
default:
return -EINVAL;