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RDMA/irdma: Add support for GEN4 hardware
GEN4 hardware is similar to GEN3 and requires only a few special cases. Signed-off-by: Jacob Moroni <jmoroni@google.com> Signed-off-by: Tatyana Nikolova <tatyana.e.nikolova@intel.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
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@ -6465,6 +6465,7 @@ static inline void irdma_sc_init_hw(struct irdma_sc_dev *dev)
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icrdma_init_hw(dev);
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break;
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case IRDMA_GEN_3:
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case IRDMA_GEN_4:
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ig3rdma_init_hw(dev);
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break;
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}
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@ -1082,6 +1082,7 @@ static int irdma_create_cqp(struct irdma_pci_f *rf)
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cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2;
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break;
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case IRDMA_GEN_3:
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case IRDMA_GEN_4:
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cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_3;
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cqp_init_info.ts_override = 1;
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break;
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@ -1508,7 +1509,7 @@ static int irdma_create_aeq(struct irdma_pci_f *rf)
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hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
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aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size);
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/* GEN_3 does not support virtual AEQ. Cap at max Kernel alloc size */
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if (rf->rdma_ver == IRDMA_GEN_3)
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if (rf->rdma_ver >= IRDMA_GEN_3)
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aeq_size = min(aeq_size, (u32)((PAGE_SIZE << MAX_PAGE_ORDER) /
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sizeof(struct irdma_sc_aeqe)));
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aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size,
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@ -1518,7 +1519,7 @@ static int irdma_create_aeq(struct irdma_pci_f *rf)
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GFP_KERNEL | __GFP_NOWARN);
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if (aeq->mem.va)
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goto skip_virt_aeq;
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else if (rf->rdma_ver == IRDMA_GEN_3)
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else if (rf->rdma_ver >= IRDMA_GEN_3)
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return -ENOMEM;
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/* physically mapped aeq failed. setup virtual aeq */
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@ -2192,8 +2193,13 @@ u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf)
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set_bit(2, rf->allocated_pds);
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INIT_LIST_HEAD(&rf->mc_qht_list.list);
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/* stag index mask has a minimum of 14 bits */
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mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14);
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if (rf->rdma_ver >= IRDMA_GEN_4)
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mrdrvbits = 24 - max(get_count_order(rf->max_mr), 16);
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else
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/* stag index mask has a minimum of 14 bits */
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mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14);
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rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits));
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return 0;
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@ -113,7 +113,6 @@ void ig3rdma_init_hw(struct irdma_sc_dev *dev)
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dev->irq_ops = &ig3rdma_irq_ops;
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dev->hw_stats_map = ig3rdma_hw_stat_map;
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dev->hw_attrs.uk_attrs.hw_rev = IRDMA_GEN_3;
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dev->hw_attrs.uk_attrs.max_hw_wq_frags = IG3RDMA_MAX_WQ_FRAGMENT_COUNT;
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dev->hw_attrs.uk_attrs.max_hw_read_sges = IG3RDMA_MAX_SGE_RD;
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dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR;
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@ -119,6 +119,7 @@ enum irdma_vers {
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IRDMA_GEN_1,
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IRDMA_GEN_2,
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IRDMA_GEN_3,
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IRDMA_GEN_4,
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IRDMA_GEN_NEXT,
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IRDMA_GEN_MAX = IRDMA_GEN_NEXT-1
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};
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