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ARM: RK: add initial support for RK3026

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This commit is contained in:
黄涛 2013-07-15 18:08:00 +08:00
parent 81ad528222
commit f3cea814bf
58 changed files with 694 additions and 85 deletions
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15
arch/arm/Kconfig
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@ -883,6 +883,21 @@ config ARCH_RK2928
help
Support for Rockchip's RK2928 SoCs.
config ARCH_RK3026
bool "Rockchip RK3026/RK3028A"
select PLAT_RK
select CPU_V7
select ARM_GIC
select RK_PL330_DMA
select RK_TIMER
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select ARM_ERRATA_754322
select ARM_ERRATA_764369
help
Support for Rockchip's RK3026/RK3028A SoCs.
config ARCH_RK30
bool "Rockchip RK30xx/RK3108/RK3168"
select PLAT_RK

1
arch/arm/Makefile
View File

@ -173,6 +173,7 @@ machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_RK29) := rk29
machine-$(CONFIG_ARCH_RK2928) := rk2928
machine-$(CONFIG_ARCH_RK3026) := rk3026
machine-$(CONFIG_ARCH_RK30) := rk30
machine-$(CONFIG_ARCH_RK3188) := rk3188
machine-$(CONFIG_ARCH_RPC) := rpc

132
arch/arm/mach-rk2928/common.c
View File

@ -16,8 +16,10 @@
#include <mach/loader.h>
#include <mach/ddr.h>
#include <mach/cpu.h>
#include <mach/cpu_axi.h>
#include <mach/debug_uart.h>
#ifdef CONFIG_ARCH_RK2928
static void __init rk2928_cpu_axi_init(void)
{
writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0088); // cpu0
@ -32,6 +34,23 @@ static void __init rk2928_cpu_axi_init(void)
writel_relaxed(0x3f, RK2928_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency
dsb();
}
#define cpu_axi_init rk2928_cpu_axi_init
#else
static void __init rk3026_cpu_axi_init(void)
{
CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU0);
CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1R);
CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1W);
CPU_AXI_SET_QOS_PRIORITY(0, 0, PERI);
CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC0);
CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC1);
CPU_AXI_SET_QOS_PRIORITY(2, 1, GPU);
writel_relaxed(0x3f, RK2928_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency
dsb();
}
#define cpu_axi_init rk3026_cpu_axi_init
#endif
#define L2_LY_SP_OFF (0)
#define L2_LY_SP_MSK (0x7)
@ -43,20 +62,25 @@ static void __init rk2928_cpu_axi_init(void)
#define L2_LY_WR_MSK (0x7)
#define L2_LY_SET(ly,off) (((ly)-1)<<(off))
#define L2_LATENCY(setup_cycles, read_cycles, write_cycles) \
L2_LY_SET(setup_cycles, L2_LY_SP_OFF) | \
L2_LY_SET(read_cycles, L2_LY_RD_OFF) | \
L2_LY_SET(write_cycles, L2_LY_WR_OFF)
static void __init rk2928_l2_cache_init(void)
{
#ifdef CONFIG_CACHE_L2X0
u32 aux_ctrl, aux_ctrl_mask;
writel_relaxed(L2_LY_SET(1,L2_LY_SP_OFF)
|L2_LY_SET(1,L2_LY_RD_OFF)
|L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(L2_LY_SET(2,L2_LY_SP_OFF)
|L2_LY_SET(3,L2_LY_RD_OFF)
|L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
writel_relaxed(L2_LATENCY(1, 1, 1), RK2928_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(L2_LATENCY(2, 3, 1), RK2928_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
/* L2X0 Prefetch Control */
#ifdef CONFIG_ARCH_RK2928
writel_relaxed(0x30000000, RK2928_L2C_BASE + L2X0_PREFETCH_CTRL);
#else
writel_relaxed(0x70000003, RK2928_L2C_BASE + L2X0_PREFETCH_CTRL);
#endif
/* L2X0 Power Control */
writel_relaxed(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, RK2928_L2C_BASE + L2X0_POWER_CTRL);
@ -86,16 +110,51 @@ static void __init rk2928_l2_cache_init(void)
}
static int boot_mode;
static const char *boot_flag_name(u32 flag)
{
flag -= SYS_KERNRL_REBOOT_FLAG;
switch (flag) {
case BOOT_NORMAL: return "NORMAL";
case BOOT_LOADER: return "LOADER";
case BOOT_MASKROM: return "MASKROM";
case BOOT_RECOVER: return "RECOVER";
case BOOT_NORECOVER: return "NORECOVER";
case BOOT_SECONDOS: return "SECONDOS";
case BOOT_WIPEDATA: return "WIPEDATA";
case BOOT_WIPEALL: return "WIPEALL";
case BOOT_CHECKIMG: return "CHECKIMG";
case BOOT_FASTBOOT: return "FASTBOOT";
default: return "";
}
}
static const char *boot_mode_name(u32 mode)
{
switch (mode) {
case BOOT_MODE_NORMAL: return "NORMAL";
case BOOT_MODE_FACTORY2: return "FACTORY2";
case BOOT_MODE_RECOVERY: return "RECOVERY";
case BOOT_MODE_CHARGE: return "CHARGE";
case BOOT_MODE_POWER_TEST: return "POWER_TEST";
case BOOT_MODE_OFFMODE_CHARGING: return "OFFMODE_CHARGING";
case BOOT_MODE_REBOOT: return "REBOOT";
case BOOT_MODE_PANIC: return "PANIC";
case BOOT_MODE_WATCHDOG: return "WATCHDOG";
default: return "";
}
}
static void __init rk2928_boot_mode_init(void)
{
u32 boot_flag = (readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG4) | (readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG5) << 16)) - SYS_KERNRL_REBOOT_FLAG;
u32 boot_flag = readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG4) | (readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG5) << 16);
boot_mode = readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG6);
if (boot_flag == BOOT_RECOVER) {
if (boot_flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER)) {
boot_mode = BOOT_MODE_RECOVERY;
}
if (boot_mode || boot_flag)
printk("Boot mode: %d flag: %d\n", boot_mode, boot_flag);
if (boot_mode || ((boot_flag & 0xff) && ((boot_flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(boot_mode), boot_mode, boot_flag_name(boot_flag), boot_flag);
}
int board_boot_mode(void)
@ -111,7 +170,7 @@ void __init rk2928_init_irq(void)
rk_fiq_init();
#endif
rk30_gpio_init();
soc_gpio_init();
soc_gpio_init();
}
static unsigned int __initdata ddr_freq = DDR_FREQ;
@ -122,42 +181,47 @@ static int __init ddr_freq_setup(char *str)
}
early_param("ddr_freq", ddr_freq_setup);
void __init rk2928_map_io(void)
static void usb_uart_init(void)
{
rk2928_map_common_io();
#ifdef DEBUG_UART_BASE
#ifdef CONFIG_RK_USB_UART
writel_relaxed(0x04000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
if(!(readl_relaxed(RK2928_GRF_BASE + 0x014c) & (1<<10)))//detect id
{
writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
}
else
{
if(!(readl_relaxed(RK2928_GRF_BASE + 0x014c) & (1<<7)))//detect vbus
{
writel_relaxed(0x10001000, RK2928_GRF_BASE + GRF_UOC0_CON0);
writel_relaxed(0x007f0055, RK2928_GRF_BASE + GRF_UOC0_CON5);
writel_relaxed(0x34003000, RK2928_GRF_BASE + GRF_UOC1_CON4);
}
else
{
writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
}
}
if(!(readl_relaxed(RK2928_GRF_BASE + 0x014c) & (1<<7)))//detect vbus
{
writel_relaxed(0x10001000, RK2928_GRF_BASE + GRF_UOC0_CON0);
writel_relaxed(0x007f0055, RK2928_GRF_BASE + GRF_UOC0_CON5);
writel_relaxed(0x34003000, RK2928_GRF_BASE + GRF_UOC1_CON4);
}
else
{
writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
}
}
#else
writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
#endif
writel_relaxed(0x07, DEBUG_UART_BASE + 0x88);
writel_relaxed(0x07, DEBUG_UART_BASE + 0x88);
writel_relaxed(0x00, DEBUG_UART_BASE + 0x04);
writel_relaxed(0x83, DEBUG_UART_BASE + 0x0c);
writel_relaxed(0x0d, DEBUG_UART_BASE + 0x00);
writel_relaxed(0x00, DEBUG_UART_BASE + 0x04);
writel_relaxed(0x03, DEBUG_UART_BASE + 0x0c);
writel_relaxed(0x07, DEBUG_UART_BASE + 0x88);
writel_relaxed(0x07, DEBUG_UART_BASE + 0x88);
writel_relaxed(0x00, DEBUG_UART_BASE + 0x04);
writel_relaxed(0x83, DEBUG_UART_BASE + 0x0c);
writel_relaxed(0x0d, DEBUG_UART_BASE + 0x00);
writel_relaxed(0x00, DEBUG_UART_BASE + 0x04);
writel_relaxed(0x03, DEBUG_UART_BASE + 0x0c);
#endif
}
void __init rk2928_map_io(void)
{
rk2928_map_common_io();
usb_uart_init();
rk29_setup_early_printk();
rk2928_cpu_axi_init();
cpu_axi_init();
rk29_sram_init();
board_clock_init();
rk2928_l2_cache_init();

21
arch/arm/mach-rk2928/devices.c
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@ -724,17 +724,26 @@ static void __init rk2928_init_sdmmc(void)
#endif
}
static struct resource resource_arm_pmu = {
.start = IRQ_ARM_PMU,
.end = IRQ_ARM_PMU,
.flags = IORESOURCE_IRQ,
static struct resource resource_arm_pmu[] = {
{
.start = IRQ_ARM_PMU,
.end = IRQ_ARM_PMU,
.flags = IORESOURCE_IRQ,
},
#if defined(CONFIG_ARCH_RK3026)
{
.start = IRQ_ARM_PMU + 1,
.end = IRQ_ARM_PMU + 1,
.flags = IORESOURCE_IRQ,
},
#endif
};
struct platform_device device_arm_pmu = {
.name = "arm-pmu",
.id = ARM_PMU_DEVICE_CPU,
.num_resources = 1,
.resource = &resource_arm_pmu,
.num_resources = ARRAY_SIZE(resource_arm_pmu),
.resource = resource_arm_pmu,
};
static int __init rk2928_init_devices(void)

18
arch/arm/mach-rk2928/include/mach/cpu_axi.h Normal file
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@ -0,0 +1,18 @@
#ifndef __MACH_CPU_AXI_H
#define __MACH_CPU_AXI_H
#include <plat/cpu_axi.h>
#define CPU_AXI_BUS_BASE RK2928_CPU_AXI_BUS_BASE
#define CPU_AXI_CPU0_QOS_BASE (CPU_AXI_BUS_BASE + 0x0080)
#define CPU_AXI_CPU1R_QOS_BASE (CPU_AXI_BUS_BASE + 0x0180)
#define CPU_AXI_CPU1W_QOS_BASE (CPU_AXI_BUS_BASE + 0x0380)
#define CPU_AXI_PERI_QOS_BASE (CPU_AXI_BUS_BASE + 0x4000)
#define CPU_AXI_GPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x5000)
#define CPU_AXI_VPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x6000)
#define CPU_AXI_LCDC0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7000)
#define CPU_AXI_CIF0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7200)
#define CPU_AXI_RGA_QOS_BASE (CPU_AXI_BUS_BASE + 0x7280)
#endif

21
arch/arm/mach-rk2928/include/mach/io.h
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@ -25,16 +25,25 @@
#define RK2928_GPU_SIZE SZ_64K
#define RK2928_ROM_PHYS 0x10100000
#define RK2928_ROM_BASE RK2928_IO_TO_VIRT0(RK2928_ROM_PHYS)
#define RK2928_ROM_SIZE SZ_16K
#define RK2928_VCODEC_PHYS 0x10104000
#define RK2928_VCODEC_SIZE SZ_16K
#define RK3026_IEP_PHYS 0x10108000
#define RK3026_IEP_SIZE SZ_8K
#define RK2928_CIF_PHYS 0x1010a000
#define RK2928_CIF_SIZE SZ_8K
#define RK2928_RGA_PHYS 0x1010c000
#define RK2928_RGA_SIZE SZ_8K
#define RK2928_LCDC_PHYS 0x1010e000
#define RK2928_LCDC_SIZE SZ_8K
#define RK3026_LCDC0_PHYS RK2928_LCDC_PHYS
#define RK3026_LCDC0_SIZE RK2928_LCDC_SIZE
#define RK3026_LCDC1_PHYS 0x10110000
#define RK3026_LCDC1_SIZE SZ_8K
#define RK3026_EBC_PHYS 0x10114000
#define RK3026_EBC_SIZE SZ_16K
#define RK2928_CPU_AXI_BUS_PHYS 0x10128000
#define RK2928_CPU_AXI_BUS_BASE RK2928_IO_TO_VIRT0(RK2928_CPU_AXI_BUS_PHYS)
@ -67,6 +76,8 @@
#define RK2928_USBOTG20_SIZE SZ_256K
#define RK2928_USBHOST20_PHYS 0x101c0000
#define RK2928_USBHOST20_SIZE SZ_256K
#define RK3026_CRYPTO_PHYS 0x10200000
#define RK3026_CRYPTO_SIZE SZ_16K
#define RK2928_SDMMC_PHYS 0x10214000
#define RK2928_SDMMC_SIZE SZ_16K
@ -173,7 +184,13 @@
#define RK2928_EFUSE_PHYS 0x20090000
#define RK2928_EFUSE_SIZE SZ_4K
#define GIC_DIST_BASE RK2928_GICD_BASE
#define GIC_CPU_BASE RK2928_GICC_BASE
#define GIC_DIST_BASE RK2928_GICD_BASE
#define RK30_CRU_BASE RK2928_CRU_BASE
#define RK30_GRF_BASE RK2928_GRF_BASE
#define RK30_IMEM_BASE RK2928_IMEM_BASE
#define RK30_PTIMER_BASE RK2928_PTIMER_BASE
#define RK30_ROM_BASE RK2928_ROM_BASE
#define RK30_SCU_BASE RK2928_SCU_BASE
#endif

14
arch/arm/mach-rk2928/include/mach/irqs.h
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@ -45,13 +45,27 @@
#define IRQ_GPIO1 69
#define IRQ_GPIO2 70
#define IRQ_GPIO3 71
#define IRQ_CRYPTO 72
#ifdef CONFIG_ARCH_RK2928
#define IRQ_PERI_AHB_USB_ARBITER 74
#define IRQ_PERI_AHB_EMEM_ARBITER 75
#else
#define IRQ_PERI_AHB_USB_ARBITER 73
#define IRQ_PERI_AHB_EMEM_ARBITER 74
#endif
#define IRQ_LCDC1 75
#define IRQ_RGA 76
#define IRQ_HDMI 77
#define IRQ_SDMMC_DETECT 78
#define IRQ_SDIO_DETECT 79
#define IRQ_IEP 80
#define IRQ_EBC 81
#define IRQ_OTG0_ID 83
#define IRQ_OTG0_LINESTATE 84
#define IRQ_OTG1_LINESTATE 85
#define IRQ_SD_DETECTN 86
#define IRQ_ARM_PMU 118

14
arch/arm/mach-rk3026/Kconfig Normal file
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@ -0,0 +1,14 @@
choice
prompt "RK3026/RK3028A Board Type"
depends on ARCH_RK3026
config MACH_RK3026_FPGA
bool "RK3026 FPGA Board"
config MACH_RK3026_TB
bool "RK3026 Top Board"
config MACH_RK3028A_TB
bool "RK3028A Top Board"
endchoice

24
arch/arm/mach-rk3026/Makefile Normal file
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@ -0,0 +1,24 @@
ifneq ($(CONFIG_RK_FPGA),y)
obj-y += ../plat-rk/clock.o
obj-y += clock_data.o
obj-y += ../mach-rk2928/ddr.o
obj-y += ../mach-rk2928/reset.o
obj-$(CONFIG_PM) += ../mach-rk30/pm.o
endif
obj-y += ../mach-rk2928/common.o
CFLAGS_common.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
obj-y += ../mach-rk2928/devices.o
obj-y += ../mach-rk2928/io.o
obj-y += rk_timer.o
obj-$(CONFIG_SMP) += ../mach-rk30/platsmp.o ../mach-rk30/headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += ../mach-rk30/hotplug.o
obj-$(CONFIG_CPU_IDLE) += ../mach-rk30/cpuidle.o
obj-$(CONFIG_CPU_FREQ) += ../mach-rk3188/cpufreq.o
obj-$(CONFIG_DVFS) += dvfs.o
obj-$(CONFIG_RK30_I2C_INSRAM) += ../mach-rk30/i2c_sram.o
obj-y += board.o
board-$(CONFIG_MACH_RK3026_FPGA) += board-rk3026-fpga.o
board-$(CONFIG_MACH_RK3026_TB) += board-rk3026-tb.o
board-$(CONFIG_MACH_RK3028A_TB) += board-rk3028a-tb.o

1
arch/arm/mach-rk3026/Makefile.boot Normal file
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@ -0,0 +1 @@
include $(srctree)/arch/arm/mach-rk30/Makefile.boot

1
arch/arm/mach-rk3026/include/mach/board.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk2928/include/mach/board.h>

1
arch/arm/mach-rk3026/include/mach/clkdev.h Normal file
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@ -0,0 +1 @@
#include <plat/clkdev.h>

1
arch/arm/mach-rk3026/include/mach/clock.h Normal file
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@ -0,0 +1 @@
#include <plat/clock.h>

1
arch/arm/mach-rk3026/include/mach/config.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk2928/include/mach/config.h>

1
arch/arm/mach-rk3026/include/mach/cpu.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk2928/include/mach/cpu.h>

21
arch/arm/mach-rk3026/include/mach/cpu_axi.h Normal file
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@ -0,0 +1,21 @@
#ifndef __MACH_CPU_AXI_H
#define __MACH_CPU_AXI_H
#include <plat/cpu_axi.h>
#define CPU_AXI_BUS_BASE RK2928_CPU_AXI_BUS_BASE
#define CPU_AXI_CPU0_QOS_BASE (CPU_AXI_BUS_BASE + 0x1000)
#define CPU_AXI_CPU1W_QOS_BASE (CPU_AXI_BUS_BASE + 0x1080)
#define CPU_AXI_CPU1R_QOS_BASE (CPU_AXI_BUS_BASE + 0x1100)
#define CPU_AXI_PERI_QOS_BASE (CPU_AXI_BUS_BASE + 0x4000)
#define CPU_AXI_GPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x5000)
#define CPU_AXI_VPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x6000)
#define CPU_AXI_LCDC1_QOS_BASE (CPU_AXI_BUS_BASE + 0x7000)
#define CPU_AXI_EBC_QOS_BASE (CPU_AXI_BUS_BASE + 0x7080)
#define CPU_AXI_IEP_QOS_BASE (CPU_AXI_BUS_BASE + 0x7100)
#define CPU_AXI_LCDC0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7180)
#define CPU_AXI_CIF0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7200)
#define CPU_AXI_RGA_QOS_BASE (CPU_AXI_BUS_BASE + 0x7280)
#endif

1
arch/arm/mach-rk3026/include/mach/ddr.h Normal file
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@ -0,0 +1 @@
#include <plat/ddr.h>

1
arch/arm/mach-rk3026/include/mach/debug-macro.S Normal file
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@ -0,0 +1 @@
#include <plat/debug-macro.S>

1
arch/arm/mach-rk3026/include/mach/debug_uart.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk2928/include/mach/debug_uart.h>

1
arch/arm/mach-rk3026/include/mach/dma-pl330.h Normal file
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@ -0,0 +1 @@
#include <plat/dma-pl330.h>

6
arch/arm/mach-rk3026/include/mach/dvfs.h Normal file
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@ -0,0 +1,6 @@
#ifndef RK_MACH_DVFS_H
#define RK_MACH_DVFS_H
#include <plat/dvfs.h>
#endif

1
arch/arm/mach-rk3026/include/mach/entry-macro.S Normal file
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@ -0,0 +1 @@
#include <plat/entry-macro.S>

1
arch/arm/mach-rk3026/include/mach/fiq.h Normal file
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@ -0,0 +1 @@
#include <plat/fiq.h>

1
arch/arm/mach-rk3026/include/mach/gpio.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk2928/include/mach/gpio.h>

87
arch/arm/mach-rk3026/include/mach/grf.h Normal file
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@ -0,0 +1,87 @@
#ifndef __MACH_GRF_H
#define __MACH_GRF_H
#define GRF_GPIO0A_IOMUX 0x00a8
#define GRF_GPIO0B_IOMUX 0x00ac
#define GRF_GPIO0C_IOMUX 0x00b0
#define GRF_GPIO0D_IOMUX 0x00b4
#define GRF_GPIO1A_IOMUX 0x00b8
#define GRF_GPIO1B_IOMUX 0x00bc
#define GRF_GPIO1C_IOMUX 0x00c0
#define GRF_GPIO1D_IOMUX 0x00c4
#define GRF_GPIO2A_IOMUX 0x00c8
#define GRF_GPIO2B_IOMUX 0x00cc
#define GRF_GPIO2C_IOMUX 0x00d0
#define GRF_GPIO2D_IOMUX 0x00d4
#define GRF_GPIO3C_IOMUX 0x00e0
#define GRF_GPIO3D_IOMUX 0x00e4
#define GRF_GPIO_DS 0x0100
#define GRF_GPIO0L_PULL 0x0118
#define GRF_GPIO0H_PULL 0x011c
#define GRF_GPIO1L_PULL 0x0120
#define GRF_GPIO1H_PULL 0x0124
#define GRF_GPIO2L_PULL 0x0128
#define GRF_GPIO2H_PULL 0x012c
#define GRF_GPIO3L_PULL 0x0130
#define GRF_GPIO3H_PULL 0x0134
#define GRF_SOC_CON0 0x0140
#define GRF_SOC_CON1 0x0144
#define GRF_SOC_CON2 0x0148
#define GRF_SOC_STATUS0 0x014c
#define GRF_LVDS_CON0 0x0150
#define GRF_DMAC_CON0 0x015c
#define GRF_DMAC_CON1 0x0160
#define GRF_DMAC_CON2 0x0164
#define GRF_UOC0_CON0 0x017c
#define GRF_UOC1_CON0 0x0190
#define GRF_UOC1_CON1 0x0194
#define GRF_DDRC_STAT 0x019c
#define GRF_UOC_CON 0x01a0
#define GRF_CPU_CON0 0x01a8
#define GRF_CPU_CON1 0x01ac
#define GRF_CPU_CON2 0x01b0
#define GRF_CPU_CON3 0x01b4
#define GRF_CPU_CON4 0x01b8
#define GRF_CPU_CON5 0x01bc
#define GRF_CPU_STATUS0 0x01c0
#define GRF_CPU_STATUS1 0x01c4
#define GRF_OS_REG0 0x01c8
#define GRF_OS_REG1 0x01cc
#define GRF_OS_REG2 0x01d0
#define GRF_OS_REG3 0x01d4
#define GRF_OS_REG4 0x01d8
#define GRF_OS_REG5 0x01dc
#define GRF_OS_REG6 0x01e0
#define GRF_OS_REG7 0x01e4
#define GRF_DLL_CON0 0x0200
#define GRF_DLL_CON1 0x0204
#define GRF_DLL_CON2 0x0208
#define GRF_DLL_CON3 0x020c
#define GRF_DLL_STATUS 0x0210
#define GRF_DFI_WRNUM 0x0220
#define GRF_DFI_RDNUM 0x0224
#define GRF_DFI_ACTNUM 0x0228
#define GRF_DFI_TIMERVAL 0x022c
#define GRF_NIF_FIFO0 0x0230
#define GRF_NIF_FIFO1 0x0234
#define GRF_NIF_FIFO2 0x0238
#define GRF_NIF_FIFO3 0x023c
#define GRF_USBPHY0_CON0 0x0280
#define GRF_USBPHY0_CON1 0x0284
#define GRF_USBPHY0_CON2 0x0288
#define GRF_USBPHY0_CON3 0x028c
#define GRF_USBPHY0_CON4 0x0290
#define GRF_USBPHY0_CON5 0x0294
#define GRF_USBPHY0_CON6 0x0298
#define GRF_USBPHY0_CON7 0x029c
#define GRF_USBPHY1_CON0 0x02a0
#define GRF_USBPHY1_CON1 0x02a4
#define GRF_USBPHY1_CON2 0x02a8
#define GRF_USBPHY1_CON3 0x02ac
#define GRF_USBPHY1_CON4 0x02b0
#define GRF_USBPHY1_CON5 0x02b4
#define GRF_USBPHY1_CON6 0x02b8
#define GRF_USBPHY1_CON7 0x02bc
#define GRF_CHIP_TAG 0x0300
#endif

4
arch/arm/mach-rk3026/include/mach/hardware.h Normal file
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@ -0,0 +1,4 @@
#ifndef __MACH_HARDWARE_H
#define __MACH_HARDWARE_H
#endif

1
arch/arm/mach-rk3026/include/mach/io.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk2928/include/mach/io.h>

132
arch/arm/mach-rk3026/include/mach/iomux.h Normal file
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@ -0,0 +1,132 @@
#ifndef __MACH_IOMUX_H
#define __MACH_IOMUX_H
#include <mach/grf.h>
#include <plat/iomux.h>
#define GRF_IOMUX_BASE (RK2928_GRF_BASE + GRF_GPIO0A_IOMUX)
enum {
/* GPIO0_A */
GPIO0_A0 = 0x0a00, I2C0_SCL,
GPIO0_A1 = 0x0a10, I2C0_SDA,
GPIO0_A2 = 0x0a20, I2C1_SCL,
GPIO0_A3 = 0x0a30, I2C1_SDA,
GPIO0_A6 = 0x0a60, I2C3_SCL, HDMI_DDCSCL,
GPIO0_A7 = 0x0a70, I2C3_SDA, HDMI_DDCSDA,
/* GPIO0_B */
GPIO0_B0 = 0x0b00, MMC1_CMD,
GPIO0_B1 = 0x0b10, MMC1_CLKOUT,
GPIO0_B2 = 0x0b20, MMC1_DETN,
GPIO0_B3 = 0x0b30, MMC1_D0,
GPIO0_B4 = 0x0b40, MMC1_D1,
GPIO0_B5 = 0x0b50, MMC1_D2,
GPIO0_B6 = 0x0b60, MMC1_D3,
GPIO0_B7 = 0x0b70, HDMI_HOTPLUGIN,
/* GPIO0_C */
GPIO0_C0 = 0x0c00, UART0_SOUT,
GPIO0_C1 = 0x0c10, UART0_SIN,
GPIO0_C2 = 0x0c20, UART0_RTSN,
GPIO0_C3 = 0x0c30, UART0_CTSN,
GPIO0_C4 = 0x0c40, HDMI_CECSDA,
GPIO0_C7 = 0x0c70, NAND_CS1,
/* GPIO0_D */
GPIO0_D0 = 0x0d00, UART2_RTSN,
GPIO0_D1 = 0x0d10, UART2_CTSN,
GPIO0_D2 = 0x0d20, PWM0,
GPIO0_D3 = 0x0d30, PWM1,
GPIO0_D4 = 0x0d40, PWM2,
GPIO0_D5 = 0x0d50, MMC1_WRPRT,
GPIO0_D6 = 0x0d60, MMC1_PWREN,
GPIO0_D7 = 0x0d70, MMC1_BKEPWR,
/* GPIO1_A */
GPIO1_A0 = 0x1a00, I2S0_MCLK, I2S0_CLK = I2S0_MCLK,
GPIO1_A1 = 0x1a10, I2S0_SCLK,
GPIO1_A2 = 0x1a20, I2S0_LRCKRX, GPS_CLK, I2S0_LRCLKRX = I2S0_LRCKRX,
GPIO1_A3 = 0x1a30, I2S0_LRCKTX,
GPIO1_A4 = 0x1a40, I2S0_SDO, GPS_MAG,
GPIO1_A5 = 0x1a50, I2S0_SDI, GPS_SIGN, JTAG_TCK,
GPIO1_A6 = 0x1a60, MMC1_INTN,
GPIO1_A7 = 0x1a70, MMC0_WRPRT,
/* GPIO1_B */
GPIO1_B0 = 0x1b00, SPI0_CLK, UART1_CTSN,
GPIO1_B1 = 0x1b10, SPI0_TXD, UART1_SOUT,
GPIO1_B2 = 0x1b20, SPI0_RXD, UART1_SIN, JTAG_TMS,
GPIO1_B3 = 0x1b30, SPI0_CS0, UART1_RTSN,
GPIO1_B4 = 0x1b40, SPI0_CS1,
GPIO1_B5 = 0x1b50, MMC0_RSTNOUT,
GPIO1_B6 = 0x1b60, MMC0_PWREN,
GPIO1_B7 = 0x1b70, MMC0_CMD,
/* GPIO1_C */
GPIO1_C0 = 0x1c00, MMC0_CLKOUT,
GPIO1_C1 = 0x1c10, MMC0_DETN,
GPIO1_C2 = 0x1c20, MMC0_D0,
GPIO1_C3 = 0x1c30, MMC0_D1,
GPIO1_C4 = 0x1c40, MMC0_D2, /* JTAG_TCK when sdmmc0_detectn is invalid */
GPIO1_C5 = 0x1c50, MMC0_D3, /* JTAG_TMS when sdmmc0_detectn is invalid */
GPIO1_C6 = 0x1c60, NAND_CS2, EMMC_CMD,
GPIO1_C7 = 0x1c70, NAND_CS3, EMMC_RSTNOUT,
/* GPIO1_D */
GPIO1_D0 = 0x1d00, NAND_D0, EMMC_D0,
GPIO1_D1 = 0x1d10, NAND_D1, EMMC_D1,
GPIO1_D2 = 0x1d20, NAND_D2, EMMC_D2,
GPIO1_D3 = 0x1d30, NAND_D3, EMMC_D3,
GPIO1_D4 = 0x1d40, NAND_D4, EMMC_D4,
GPIO1_D5 = 0x1d50, NAND_D5, EMMC_D5,
GPIO1_D6 = 0x1d60, NAND_D6, EMMC_D6,
GPIO1_D7 = 0x1d70, NAND_D7, EMMC_D7,
/* GPIO2_A */
GPIO2_A0 = 0x2a00, NAND_ALE,
GPIO2_A1 = 0x2a10, NAND_CLE,
GPIO2_A2 = 0x2a20, NAND_WRN,
GPIO2_A3 = 0x2a30, NAND_RDN,
GPIO2_A4 = 0x2a40, NAND_RDY,
GPIO2_A5 = 0x2a50, NAND_WP, EMMC_PWREN,
GPIO2_A6 = 0x2a60, NAND_CS0,
GPIO2_A7 = 0x2a70, NAND_DQS, EMMC_CLKOUT,
/* GPIO2_B */
GPIO2_B0 = 0x2b00, LCDC0_DCLK, EBC_SDCLK,
GPIO2_B1 = 0x2b10, LCDC0_HSYNC, EBC_SDLE,
GPIO2_B2 = 0x2b20, LCDC0_VSYNC, EBC_SDOE,
GPIO2_B3 = 0x2b30, LCDC0_DEN, EBC_GDCLK,
GPIO2_B4 = 0x2b40, LCDC0_D10, EBC_SDCE2,
GPIO2_B5 = 0x2b50, LCDC0_D11, EBC_SDCE3,
GPIO2_B6 = 0x2b60, LCDC0_D12, EBC_SDCE4,
GPIO2_B7 = 0x2b70, LCDC0_D13, EBC_SDCE5,
/* GPIO2_C */
GPIO2_C0 = 0x2c00, LCDC0_D14, EBC_VCOM,
GPIO2_C1 = 0x2c10, LCDC0_D15, EBC_GDOE,
GPIO2_C2 = 0x2c20, LCDC0_D16, EBC_GDSP,
GPIO2_C3 = 0x2c30, LCDC0_D17, EBC_GDPWR0,
GPIO2_C4 = 0x2c40, LCDC0_D18, EBC_GDRL, I2C2_SDA,
GPIO2_C5 = 0x2c50, LCDC0_D19, EBC_SDSHR, I2C2_SCL,
GPIO2_C6 = 0x2c60, LCDC0_D20, EBC_BORDER0, UART2_SIN,
GPIO2_C7 = 0x2c70, LCDC0_D21, EBC_BORDER1, UART2_SOUT,
/* GPIO2_D */
GPIO2_D0 = 0x2d00, LCDC0_D22, EBC_GDPWR1,
GPIO2_D1 = 0x2d10, LCDC0_D23, EBC_GDPWR2,
/* GPIO3_A */
/* GPIO3_B */
/* GPIO3_C */
GPIO3_C1 = 0x3c10, OTG_DRV_VBUS,
/* GPIO3_D */
GPIO3_D7 = 0x3d70, TEST_CLK_OUT,
};
#define rk29_mux_api_set(name, mode) iomux_set(mode)
#define rk30_mux_api_set(name, mode) iomux_set(mode)
#endif

1
arch/arm/mach-rk3026/include/mach/irqs.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk2928/include/mach/irqs.h>

1
arch/arm/mach-rk3026/include/mach/loader.h Normal file
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@ -0,0 +1 @@
#include <plat/loader.h>

1
arch/arm/mach-rk3026/include/mach/memory.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk2928/include/mach/memory.h>

46
arch/arm/mach-rk3026/include/mach/pmu.h Normal file
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@ -0,0 +1,46 @@
#ifndef __MACH_PMU_H
#define __MACH_PMU_H
#include <mach/cru.h>
enum pmu_power_domain {
PD_A9_0 = 0,
PD_A9_1,
PD_ALIVE,
PD_RTC,
PD_SCU,
PD_CPU,
PD_PERI = 6,
PD_VIO,
PD_VIDEO,
PD_VCODEC = PD_VIDEO,
PD_GPU,
PD_DBG,
};
static inline bool pmu_power_domain_is_on(enum pmu_power_domain pd)
{
return true;
}
static inline void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
{
if (on && pd == PD_A9_1) {
cru_set_soft_reset(SOFT_RST_CORE1, true);
cru_set_soft_reset(SOFT_RST_CORE1, false);
}
}
enum pmu_idle_req {
IDLE_REQ_CPU = 0,
IDLE_REQ_PERI,
IDLE_REQ_GPU,
IDLE_REQ_VIDEO,
IDLE_REQ_VIO,
};
static inline void pmu_set_idle_request(enum pmu_idle_req req, bool idle)
{
}
#endif

1
arch/arm/mach-rk3026/include/mach/rk2928_camera.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk2928/include/mach/rk2928_camera.h>

1
arch/arm/mach-rk3026/include/mach/sram.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk30/include/mach/sram.h>

1
arch/arm/mach-rk3026/include/mach/system.h Normal file
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@ -0,0 +1 @@
#include <plat/system.h>

1
arch/arm/mach-rk3026/include/mach/timex.h Normal file
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@ -0,0 +1 @@
#include <plat/timex.h>

1
arch/arm/mach-rk3026/include/mach/uncompress.h Normal file
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@ -0,0 +1 @@
#include <plat/uncompress.h>

1
arch/arm/mach-rk3026/include/mach/vmalloc.h Normal file
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@ -0,0 +1 @@
#include <../../mach-rk30/include/mach/vmalloc.h>

82
arch/arm/mach-rk3026/rk_timer.c Normal file
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@ -0,0 +1,82 @@
#include <linux/clockchips.h>
#include <linux/platform_device.h>
#include <asm/mach/time.h>
#include <asm/localtimer.h>
#include <asm/smp_twd.h>
#include <mach/io.h>
#include <mach/irqs.h>
#define TIMER_NAME "rk_timer"
#define BASE RK2928_TIMER0_PHYS
#define OFFSET 0x20
static struct resource rk_timer_resources[] __initdata = {
{
.name = "cs_base",
.start = (unsigned long) BASE + 1 * OFFSET,
.flags = IORESOURCE_MEM,
}, {
.name = "cs_clk",
.start = (unsigned long) "timer1",
}, {
.name = "cs_pclk",
.start = (unsigned long) "pclk_timer0",
},
{
.name = "ce_base0",
.start = (unsigned long) BASE + 0 * OFFSET,
.flags = IORESOURCE_MEM,
}, {
.name = "ce_irq0",
.start = (unsigned long) IRQ_TIMER0,
.flags = IORESOURCE_IRQ,
}, {
.name = "ce_clk0",
.start = (unsigned long) "timer0",
}, {
.name = "ce_pclk0",
.start = (unsigned long) "pclk_timer0",
},
};
static struct platform_device rk_timer_device __initdata = {
.name = TIMER_NAME,
.id = 0,
.resource = rk_timer_resources,
.num_resources = ARRAY_SIZE(rk_timer_resources),
};
static struct platform_device *rk_timer_devices[] __initdata = {
&rk_timer_device,
};
static void __init rk_timer_init(void)
{
#ifdef CONFIG_HAVE_ARM_TWD
twd_base = RK30_PTIMER_BASE;
#endif
early_platform_add_devices(rk_timer_devices, ARRAY_SIZE(rk_timer_devices));
early_platform_driver_register_all(TIMER_NAME);
early_platform_driver_probe(TIMER_NAME, 1, 0);
}
struct sys_timer rk30_timer = {
.init = rk_timer_init
};
struct sys_timer rk2928_timer = {
.init = rk_timer_init
};
#ifdef CONFIG_LOCAL_TIMERS
/*
* Setup the local clock events for a CPU.
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
evt->irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
}
#endif

10
arch/arm/plat-rk/Kconfig
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@ -153,7 +153,7 @@ endchoice
config RK29_VPU
tristate "VPU (Video Processing Unit) service driver in kernel"
depends on ARCH_RK29 || ARCH_RK30 || ARCH_RK2928
depends on ARCH_RK29 || ARCH_RK30 || ARCH_RK2928 || ARCH_RK3026
default m
config RK29_LAST_LOG
@ -174,13 +174,13 @@ config RK_EARLY_PRINTK
config RK_DEBUG_UART
int "Debug UART"
default 1 if ARCH_RK29
default 2 if ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188
default 2 if ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026
help
Select a UART for debugging. -1 disable.
config RK_USB_UART
bool "Support USB UART Bypass Function"
depends on (ARCH_RK2928 || ARCH_RK3188) && (RK_DEBUG_UART = 2)
depends on (ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026) && (RK_DEBUG_UART = 2)
config RK_CONSOLE_THREAD
bool "Console write by thread"
@ -214,7 +214,7 @@ config RK_TIMER
config RK_USB_DETECT_BY_OTG_BVALID
bool "Wakeup system by OTG BVALID interrupt when USB OTG conneted"
depends on USB_GADGET && (ARCH_RK2928 || ARCH_RK3188)
default y if ARCH_RK2928 || ARCH_RK3188
depends on USB_GADGET && (ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026)
default y
endif

63
arch/arm/plat-rk/include/plat/cpu.h
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@ -33,7 +33,7 @@ static inline bool soc_is_rk2928l(void) { return false; }
static inline bool soc_is_rk2926(void) { return false; }
#endif
#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188)
#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK3026)
static inline bool cpu_is_rk30xx(void)
{
return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33303041
@ -54,21 +54,6 @@ static inline bool cpu_is_rk3066b(void)
&& readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313030);
}
static inline bool soc_is_rk3066b(void)
{
return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 0);
}
static inline bool soc_is_rk3108(void)
{
return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 1);
}
static inline bool soc_is_rk3168m(void)
{
return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 3);
}
static inline bool soc_is_rk3188(void)
{
return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33313042
@ -84,16 +69,41 @@ static inline bool soc_is_rk3188plus(void)
&& readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x30313331
&& readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313031;
}
static inline bool cpu_is_rk3026(void)
{
return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x32393243
&& readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303133
&& readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x30353239
&& readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313031;
}
#else
static inline bool cpu_is_rk30xx(void) { return false; }
static inline bool cpu_is_rk3066b(void) { return false; }
static inline bool soc_is_rk3188(void) { return false; }
static inline bool soc_is_rk3188plus(void) { return false; }
static inline bool cpu_is_rk3026(void) { return false; }
#endif
#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188)
static inline bool soc_is_rk3066b(void)
{
return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 0);
}
static inline bool soc_is_rk3108(void)
{
return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 1);
}
static inline bool soc_is_rk3168m(void)
{
return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 3);
}
#else
static inline bool soc_is_rk3066b(void) { return false; }
static inline bool soc_is_rk3108(void) { return false; }
static inline bool soc_is_rk3168m(void) { return false; }
static inline bool soc_is_rk3188(void) { return false; }
static inline bool soc_is_rk3188plus(void) { return false; }
#endif
static inline bool cpu_is_rk3188(void)
@ -128,4 +138,19 @@ static inline bool soc_is_rk3068(void) { return true; }
static inline bool soc_is_rk3068(void) { return false; }
#endif
#ifdef CONFIG_ARCH_RK3026
static inline bool soc_is_rk3026(void)
{
return cpu_is_rk3026() && ((readl_relaxed(RK2928_GPIO3_BASE + GPIO_EXT_PORT) & 7) == 4);
}
static inline bool soc_is_rk3028a(void)
{
return cpu_is_rk3026() && ((readl_relaxed(RK2928_GPIO3_BASE + GPIO_EXT_PORT) & 7) == 3);
}
#else
static inline bool soc_is_rk3026(void) { return false; }
static inline bool soc_is_rk3028a(void) { return false; }
#endif
#endif

2
arch/arm/plat-rk/include/plat/ddr.h
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@ -146,7 +146,7 @@
void __sramfunc ddr_suspend(void);
void __sramfunc ddr_resume(void);
//void __sramlocalfunc delayus(uint32_t us);
#if defined(CONFIG_ARCH_RK2928)
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
uint32_t __sramfunc ddr_change_freq(uint32_t nMHz);
#else
uint32_t ddr_change_freq(uint32_t nMHz);

4
arch/arm/plat-rk/pwm.c
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@ -24,7 +24,7 @@ struct clk *rk_pwm_get_clk(unsigned id)
return clk_get(NULL, "pwm01");
else if (id== 2 || id == 3)
return clk_get(NULL, "pwm23");
#elif defined(CONFIG_ARCH_RK2928)
#elif defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
if (id < 3)
return clk_get(NULL, "pwm01");
#endif
@ -44,7 +44,7 @@ void __iomem *rk_pwm_get_base(unsigned id)
return RK30_PWM01_BASE + id * 0x10;
else if (id== 2 || id == 3)
return RK30_PWM23_BASE + id * 0x10;
#elif defined(CONFIG_ARCH_RK2928)
#elif defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
if (id < 3)
return RK2928_PWM_BASE + id * 0x10;
#endif

4
arch/arm/plat-rk/sram.c
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@ -27,7 +27,7 @@ extern char __sram_data_start, __ssram_data, __esram_data;
#define SRAM_CACHED RK30_IMEM_BASE
#define SRAM_PHYS RK30_IMEM_PHYS
#define SRAM_SIZE RK30_IMEM_SIZE
#elif defined(CONFIG_ARCH_RK2928)
#elif defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
#define SRAM_NONCACHED RK2928_IMEM_NONCACHED
#define SRAM_CACHED RK2928_IMEM_BASE
#define SRAM_PHYS RK2928_IMEM_PHYS
@ -179,7 +179,7 @@ void __sramfunc sram_printhex(unsigned int hex)
}
struct sram_gpio_data __sramdata pmic_sleep,pmic_vsel;
#if defined(CONFIG_ARCH_RK2928)
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
static void __iomem *gpio_base[] = {RK2928_GPIO0_BASE, RK2928_GPIO1_BASE, RK2928_GPIO2_BASE, RK2928_GPIO3_BASE};
#elif defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
static void __iomem *gpio_base[] = {RK30_GPIO0_BASE, RK30_GPIO1_BASE, RK30_GPIO2_BASE, RK30_GPIO3_BASE};

4
drivers/adc/plat/Kconfig
View File

@ -5,7 +5,7 @@
choice
prompt "ADC hardware drivers"
default ADC_RK29 if ARCH_RK29
default ADC_RK30 if ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188
default ADC_RK30 if ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026
config ADC_NULL
bool "NULL"
@ -24,7 +24,7 @@ config ADC_RK29
config ADC_RK30
bool "RK30 adc interface"
depends on ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188
depends on ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026
help
This supports the use of the ADC interface on rk30 processors.
endchoice

1
drivers/gpio/Makefile
View File

@ -49,6 +49,7 @@ obj-$(CONFIG_ARCH_RK29) += gpio-rk29.o
obj-$(CONFIG_ARCH_RK2928) += gpio-rk30.o
obj-$(CONFIG_ARCH_RK30) += gpio-rk30.o
obj-$(CONFIG_ARCH_RK3188) += gpio-rk30.o
obj-$(CONFIG_ARCH_RK3026) += gpio-rk30.o
obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o
obj-$(CONFIG_GPIO_SX150X) += sx150x.o
obj-$(CONFIG_GPIO_VX855) += vx855_gpio.o

2
drivers/gpio/gpio-rk30.c
View File

@ -37,7 +37,7 @@
#define MAX_PIN RK30_PIN3_PD7
#elif defined(CONFIG_ARCH_RK30)
#define MAX_PIN RK30_PIN6_PB7
#elif defined(CONFIG_ARCH_RK2928)
#elif defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
#define MAX_PIN RK2928_PIN3_PD7
#define RK30_GPIO0_PHYS RK2928_GPIO0_PHYS
#define RK30_GPIO0_BASE RK2928_GPIO0_BASE

2
drivers/i2c/busses/Kconfig
View File

@ -908,7 +908,7 @@ if I2C_RK30
endif
config I2C4_RK30
bool "I2C4 Channel Support"
depends on !ARCH_RK2928
depends on !ARCH_RK2928 && !ARCH_RK3026
default y
help
This supports the use of the I2C4 channel on RK Soc.

2
drivers/i2c/busses/i2c-rk30.h
View File

@ -50,7 +50,7 @@
#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188)
#define GRF_I2C_CON_BASE (RK30_GRF_BASE + GRF_SOC_CON1)
#endif
#ifdef CONFIG_ARCH_RK2928
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
#define GRF_I2C_CON_BASE (RK2928_GRF_BASE + GRF_SOC_CON1)
#endif
#define I2C_ADAP_SEL_BIT(nr) ((nr) + 11)

6
drivers/media/video/Makefile
View File

@ -218,6 +218,12 @@ ifeq ($(CONFIG_ARCH_RK2928),y)
obj-$(CONFIG_VIDEO_RKCIF_WORK_ONEFRAME) += rk30_camera_oneframe.o
obj-$(CONFIG_VIDEO_RKCIF_WORK_PINGPONG) += rk30_camera_pingpong.o
endif
ifeq ($(CONFIG_ARCH_RK3026),y)
obj-$(CONFIG_VIDEO_RKCIF_WORK_ONEFRAME) += rk30_camera_oneframe.o
obj-$(CONFIG_VIDEO_RKCIF_WORK_PINGPONG) += rk30_camera_pingpong.o
endif
ifeq ($(CONFIG_ARCH_RK29),y)
obj-$(CONFIG_VIDEO_RKCIF_WORK_ONEFRAME) += rk29_camera_oneframe.o
obj-$(CONFIG_VIDEO_RKCIF_WORK_PINGPONG) += rk29_camera_pingpang.o

2
drivers/mmc/host/rk29_sdmmc.c
View File

@ -131,7 +131,7 @@ int debug_level = 5;
#endif
//use the new iomux-API
#if defined(CONFIG_ARCH_RK3066B)||defined(CONFIG_ARCH_RK3168)||defined(CONFIG_ARCH_RK3188)
#if defined(CONFIG_ARCH_RK3066B)||defined(CONFIG_ARCH_RK3168)||defined(CONFIG_ARCH_RK3188)||defined(CONFIG_ARCH_RK3026)
#define DRIVER_SDMMC_USE_NEW_IOMUX_API 1
#else
#define DRIVER_SDMMC_USE_NEW_IOMUX_API 0

2
drivers/spi/Kconfig
View File

@ -438,7 +438,7 @@ config SPIM0_RK29
config SPIM1_RK29
bool "RK SPI1 master controller"
depends on SPIM_RK29 && !ARCH_RK2928
depends on SPIM_RK29 && !ARCH_RK2928 && !ARCH_RK3026
help
enable SPI1 master controller for RK29

2
drivers/tty/serial/Kconfig
View File

@ -1567,7 +1567,7 @@ config UART2_DMA_RK29
3:both enable dma tx and rx
config UART3_RK29
bool "Serial port 3 support"
depends on SERIAL_RK29 && !ARCH_RK2928
depends on SERIAL_RK29 && !ARCH_RK2928 && !ARCH_RK3026
config UART3_CTS_RTS_RK29
bool "Serial port 3 CTS/RTS support"

2
drivers/video/rockchip/rga/Kconfig
View File

@ -1,5 +1,5 @@
menu "RGA"
depends on ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188
depends on ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026
config RGA_RK30
tristate "ROCKCHIP RK30 || RK2928 RGA"

2
drivers/video/rockchip/rga/rga.h
View File

@ -390,7 +390,7 @@ typedef struct rga_service_info {
#if defined(CONFIG_ARCH_RK2928)
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
#define RGA_BASE 0x1010c000
#elif defined(CONFIG_ARCH_RK30)
#define RGA_BASE 0x10114000

2
drivers/video/rockchip/rga/rga_drv.c
View File

@ -62,7 +62,7 @@
#define RGA_MAJOR 255
#if defined(CONFIG_ARCH_RK2928)
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
#define RK30_RGA_PHYS RK2928_RGA_PHYS
#define RK30_RGA_SIZE RK2928_RGA_SIZE
#endif

4
sound/soc/rk29/Kconfig
View File

@ -33,7 +33,7 @@ endif
config SND_RK29_SOC_I2S_2CH
bool "Soc RK29 I2S 2 Channel support(I2S1)"
depends on SND_RK29_SOC_I2S && !ARCH_RK2928
depends on SND_RK29_SOC_I2S && !ARCH_RK2928 && !ARCH_RK3026
default y if (ARCH_RK3066B || ARCH_RK3188)
help
This supports the use of the 2 Channel I2S interface on rk29 processors.
@ -53,7 +53,7 @@ endchoice
config SND_RK_SOC_I2S2_2CH
bool "Soc RK29 I2S 2 Channel support(I2S2)"
default n
depends on SND_RK29_SOC_I2S && ARCH_RK30 && !ARCH_RK2928 && !ARCH_RK3066B
depends on SND_RK29_SOC_I2S && ARCH_RK30 && !ARCH_RK2928 && !ARCH_RK3066B && !ARCH_RK3026
help
This supports the use of the 2 Channel I2S2 interface on rk30 processors.

2
sound/soc/rk29/rk30_i2s.c
View File

@ -644,7 +644,7 @@ static int __devinit rockchip_i2s_probe(struct platform_device *pdev)
i2s->dma_playback->dma_addr = RK30_I2S1_2CH_PHYS + I2S_TXR_BUFF;
break;
#endif
#ifdef CONFIG_ARCH_RK2928
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
case 0:
i2s->dma_capture->channel = DMACH_I2S0_8CH_RX;
i2s->dma_capture->dma_addr = RK2928_I2S_PHYS + I2S_RXR_BUFF;