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drm/rockchip: vop: add support vop global alpha

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Change-Id: Ifcd61468adcca8e109a3b43534febf4ee80c1d1f
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang 2018-01-02 11:54:18 +08:00 committed by Tao Huang
parent a7ef991a1f
commit f3cbfc89db
5 changed files with 46 additions and 8 deletions
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6
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View File

@ -1113,6 +1113,12 @@ static int rockchip_drm_create_properties(struct drm_device *dev)
return -ENOMEM;
private->color_space_prop = prop;
prop = drm_property_create_range(dev, DRM_MODE_PROP_ATOMIC,
"GLOBAL_ALPHA", 0, 255);
if (!prop)
return -ENOMEM;
private->global_alpha_prop = prop;
return drm_mode_create_tv_properties(dev, 0, NULL);
}

1
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View File

@ -175,6 +175,7 @@ struct rockchip_drm_private {
struct drm_property *cabc_calc_pixel_num_property;
struct drm_property *eotf_prop;
struct drm_property *color_space_prop;
struct drm_property *global_alpha_prop;
void *backlight;
struct drm_fb_helper *fbdev_helper;
struct drm_gem_object *fbdev_bo;

35
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@ -167,6 +167,7 @@ struct vop_plane_state {
int color_space;
unsigned int csc_mode;
bool enable;
int global_alpha;
};
struct vop_win {
@ -1539,7 +1540,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
const uint32_t *r2y_table = vop_plane_state->r2y_table;
int ymirror, xmirror;
uint32_t val;
bool rb_swap;
bool rb_swap, global_alpha_en;
/*
* can't update plane when vop is disabled.
@ -1594,15 +1595,26 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
rb_swap = has_rb_swapped(fb->pixel_format);
VOP_WIN_SET(vop, win, rb_swap, rb_swap);
if (is_alpha_support(fb->pixel_format) &&
global_alpha_en = (vop_plane_state->global_alpha == 0xff) ? 0 : 1;
if ((is_alpha_support(fb->pixel_format) || global_alpha_en) &&
(s->dsp_layer_sel & 0x3) != win->win_id) {
int src_bland_m0;
if (is_alpha_support(fb->pixel_format) && global_alpha_en)
src_bland_m0 = ALPHA_PER_PIX_GLOBAL;
else if (is_alpha_support(fb->pixel_format))
src_bland_m0 = ALPHA_PER_PIX;
else
src_bland_m0 = ALPHA_GLOBAL;
VOP_WIN_SET(vop, win, dst_alpha_ctl,
DST_FACTOR_M0(ALPHA_SRC_INVERSE));
val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
SRC_ALPHA_M0(ALPHA_STRAIGHT) |
SRC_BLEND_M0(ALPHA_PER_PIX) |
SRC_BLEND_M0(src_bland_m0) |
SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
SRC_FACTOR_M0(ALPHA_ONE);
SRC_FACTOR_M0(global_alpha_en ?
ALPHA_SRC_GLOBAL : ALPHA_ONE);
VOP_WIN_SET(vop, win, src_alpha_ctl, val);
VOP_WIN_SET(vop, win, alpha_mode, 1);
VOP_WIN_SET(vop, win, alpha_en, 1);
@ -1610,6 +1622,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
VOP_WIN_SET(vop, win, alpha_en, 0);
}
VOP_WIN_SET(vop, win, global_alpha_val, vop_plane_state->global_alpha);
VOP_WIN_SET(vop, win, csc_mode, vop_plane_state->csc_mode);
if (win->csc) {
@ -1648,6 +1661,7 @@ void vop_atomic_plane_reset(struct drm_plane *plane)
return;
vop_plane_state->zpos = win->win_id;
vop_plane_state->global_alpha = 0xff;
plane->state = &vop_plane_state->base;
plane->state->plane = plane;
}
@ -1718,6 +1732,11 @@ static int vop_atomic_plane_set_property(struct drm_plane *plane,
return 0;
}
if (property == private->global_alpha_prop) {
plane_state->global_alpha = val;
return 0;
}
DRM_ERROR("failed to set vop plane property\n");
return -EINVAL;
}
@ -1751,6 +1770,11 @@ static int vop_atomic_plane_get_property(struct drm_plane *plane,
return 0;
}
if (property == private->global_alpha_prop) {
*val = plane_state->global_alpha;
return 0;
}
DRM_ERROR("failed to get vop plane property\n");
return -EINVAL;
}
@ -3510,6 +3534,9 @@ static int vop_plane_init(struct vop *vop, struct vop_win *win,
drm_object_attach_property(&win->base.base, private->eotf_prop, 0);
drm_object_attach_property(&win->base.base,
private->color_space_prop, 0);
if (VOP_WIN_SUPPORT(vop, win, global_alpha_val))
drm_object_attach_property(&win->base.base,
private->global_alpha_prop, 0xff);
return 0;
}

1
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@ -379,6 +379,7 @@ struct vop_win_phy {
struct vop_reg src_alpha_ctl;
struct vop_reg alpha_mode;
struct vop_reg alpha_en;
struct vop_reg global_alpha_val;
struct vop_reg key_color;
struct vop_reg key_en;
};

11
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@ -119,7 +119,8 @@ static const struct vop_win_phy rk3288_win01_data = {
.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffff, 0),
.global_alpha_val = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 16),
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
.channel = VOP_REG_VER(RK3288_WIN0_CTRL2, 0xff, 0, 3, 8, 8),
};
@ -133,9 +134,10 @@ static const struct vop_win_phy rk3288_win23_data = {
.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
.yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffff, 0),
.yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
.src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xffffffff, 0),
.src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xffff, 0),
.global_alpha_val = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 16),
.dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xffffffff, 0),
};
@ -365,7 +367,8 @@ static const struct vop_win_phy rk3368_win23_data = {
.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
.src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xffffffff, 0),
.src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xffff, 0),
.global_alpha_val = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 16),
.dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xffffffff, 0),
};