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staging: media: atomisp: Remove braces for single statement blocks

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Fix checkpatch.pl warnings:

WARNING: braces {} are not necessary for single statement blocks
WARNING: braces {} are not necessary for any arm of this statement

Signed-off-by: Matt Wardle <matt@mattwardle.net>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
This commit is contained in:
Matt Wardle 2026-02-10 09:23:58 +00:00 committed by Sakari Ailus
parent c565afd284
commit f3c450f5f1
23 changed files with 53 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf.h
View File

@ -146,9 +146,8 @@ static inline uint8_t ia_css_circbuf_get_pos_at_offset(
OP___assert(cb->desc->size > 0);
/* step 1: adjudst the offset */
while (offset < 0) {
while (offset < 0)
offset += cb->desc->size;
}
/* step 2: shift and round by the upper limit */
dest = OP_std_modadd(base, offset, cb->desc->size);

3
drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf_desc.h
View File

@ -84,9 +84,8 @@ static inline uint8_t ia_css_circbuf_desc_get_pos_at_offset(
OP___assert(cb_desc->size > 0);
/* step 1: adjust the offset */
while (offset < 0) {
while (offset < 0)
offset += cb_desc->size;
}
/* step 2: shift and round by the upper limit */
dest = OP_std_modadd(base, offset, cb_desc->size);

3
drivers/staging/media/atomisp/pci/base/refcount/src/refcount.c
View File

@ -238,9 +238,8 @@ void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr)
hmm_free(entry->data);
}
if (entry->count != 0) {
if (entry->count != 0)
IA_CSS_WARNING("Ref count for entry %x is not zero!", entry->id);
}
assert(entry->count == 0);

9
drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_stagedesc.c
View File

@ -32,9 +32,8 @@ void ia_css_pipe_get_generic_stage_desc(
stage_desc->max_input_width = 0;
stage_desc->mode = binary->info->sp.pipeline.mode;
stage_desc->in_frame = in_frame;
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
stage_desc->out_frame[i] = out_frame[i];
}
stage_desc->vf_frame = vf_frame;
ERR:
IA_CSS_LEAVE_PRIVATE("");
@ -59,9 +58,8 @@ void ia_css_pipe_get_firmwares_stage_desc(
stage_desc->max_input_width = 0;
stage_desc->mode = mode;
stage_desc->in_frame = in_frame;
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
stage_desc->out_frame[i] = out_frame[i];
}
stage_desc->vf_frame = vf_frame;
}
@ -82,8 +80,7 @@ void ia_css_pipe_get_sp_func_stage_desc(
stage_desc->mode = (unsigned int)-1;
stage_desc->in_frame = NULL;
stage_desc->out_frame[0] = out_frame;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
stage_desc->out_frame[i] = NULL;
}
stage_desc->vf_frame = NULL;
}

3
drivers/staging/media/atomisp/pci/camera/pipe/src/pipe_util.c
View File

@ -26,9 +26,8 @@ void ia_css_pipe_util_create_output_frames(
unsigned int i;
assert(frames);
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
frames[i] = NULL;
}
}
void ia_css_pipe_util_set_output_frames(

3
drivers/staging/media/atomisp/pci/css_2401_system/host/isys_stream2mmio_private.h
View File

@ -41,9 +41,8 @@ STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_state(
* Get the values of the register-set per
* stream2mmio-controller sids.
*/
for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) {
for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++)
stream2mmio_get_sid_state(ID, i, &state->sid_state[i]);
}
}
/**

3
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/event_fifo_private.h
View File

@ -26,9 +26,8 @@ STORAGE_CLASS_EVENT_C void event_wait_for(const event_ID_t ID)
STORAGE_CLASS_EVENT_C void cnd_event_wait_for(const event_ID_t ID,
const bool cnd)
{
if (cnd) {
if (cnd)
event_wait_for(ID);
}
}
STORAGE_CLASS_EVENT_C hrt_data event_receive_token(const event_ID_t ID)

3
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_formatter.c
View File

@ -62,9 +62,8 @@ void input_formatter_rst(
* WICH USES THE STREAM2MEMRY BLOCK.
* MUST BE FIXED PROPERLY
*/
if (!HIVE_IF_BIN_COPY[ID]) {
if (!HIVE_IF_BIN_COPY[ID])
input_formatter_reg_store(ID, addr, rst);
}
return;
}

14
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_system.c
View File

@ -138,11 +138,10 @@ void receiver_port_enable(
hrt_data reg = receiver_port_reg_load(ID, port_ID,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
if (cnd) {
if (cnd)
reg |= 0x01;
} else {
else
reg &= ~0x01;
}
receiver_port_reg_store(ID, port_ID,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, reg);
@ -194,9 +193,8 @@ static void receiver_rst(
assert(ID < N_RX_ID);
// Disable all ports.
for (port_id = MIPI_PORT0_ID; port_id < N_MIPI_PORT_ID; port_id++) {
for (port_id = MIPI_PORT0_ID; port_id < N_MIPI_PORT_ID; port_id++)
receiver_port_enable(ID, port_id, false);
}
// AM: Additional actions for stopping receiver?
}
@ -830,15 +828,13 @@ input_system_err_t input_system_configuration_commit(void)
// The last configuration step is to configure the input buffer.
input_system_err_t error = input_buffer_configuration();
if (error != INPUT_SYSTEM_ERR_NO_ERROR) {
if (error != INPUT_SYSTEM_ERR_NO_ERROR)
return error;
}
// Translate the whole configuration into registers.
error = configuration_to_registers();
if (error != INPUT_SYSTEM_ERR_NO_ERROR) {
if (error != INPUT_SYSTEM_ERR_NO_ERROR)
return error;
}
// Translate the whole configuration into ctrl commands etc.

30
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq.c
View File

@ -55,9 +55,8 @@ void irq_clear_all(
assert(ID < N_IRQ_ID);
assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH);
if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH) {
if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH)
mask = ~((~(hrt_data)0) >> IRQ_N_CHANNEL[ID]);
}
irq_reg_store(ID,
_HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, mask);
@ -115,9 +114,9 @@ void irq_enable_pulse(
{
unsigned int edge_out = 0x0;
if (pulse) {
if (pulse)
edge_out = 0xffffffff;
}
/* output is given as edge, not pulse */
irq_reg_store(ID,
_HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX, edge_out);
@ -259,9 +258,9 @@ void virq_clear_all(void)
{
irq_ID_t irq_id;
for (irq_id = (irq_ID_t)0; irq_id < N_IRQ_ID; irq_id++) {
for (irq_id = (irq_ID_t)0; irq_id < N_IRQ_ID; irq_id++)
irq_clear_all(irq_id);
}
return;
}
@ -301,9 +300,9 @@ void virq_clear_info(struct virq_info *irq_info)
assert(irq_info);
for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++)
irq_info->irq_status_reg[ID] = 0;
}
return;
}
@ -324,20 +323,17 @@ enum hrt_isp_css_irq_status virq_get_channel_id(
break;
}
if (idx == IRQ_N_CHANNEL[IRQ0_ID]) {
if (idx == IRQ_N_CHANNEL[IRQ0_ID])
return hrt_isp_css_irq_status_error;
}
/* Check whether there are more bits set on device 0 */
if (irq_status != (1U << idx)) {
if (irq_status != (1U << idx))
status = hrt_isp_css_irq_status_more_irqs;
}
/* Check whether we have an IRQ on one of the nested devices */
for (ID = N_IRQ_ID - 1 ; ID > (irq_ID_t)0; ID--) {
if (IRQ_NESTING_ID[ID] == (enum virq_id)idx) {
if (IRQ_NESTING_ID[ID] == (enum virq_id)idx)
break;
}
}
/* If we have a nested IRQ, load that state, discard the device 0 state */
@ -350,9 +346,8 @@ enum hrt_isp_css_irq_status virq_get_channel_id(
break;
}
if (idx == IRQ_N_CHANNEL[ID]) {
if (idx == IRQ_N_CHANNEL[ID])
return hrt_isp_css_irq_status_error;
}
/* Alternatively check whether there are more bits set on this device */
if (irq_status != (1U << idx)) {
@ -408,9 +403,8 @@ static inline irq_ID_t virq_get_irq_id(
assert(channel_ID);
for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
if (irq_ID < IRQ_N_ID_OFFSET[ID + 1]) {
if (irq_ID < IRQ_N_ID_OFFSET[ID + 1])
break;
}
}
*channel_ID = (unsigned int)irq_ID - IRQ_N_ID_OFFSET[ID];

3
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/mmu.c
View File

@ -32,7 +32,6 @@ void mmu_invalidate_cache_all(void)
{
mmu_ID_t mmu_id;
for (mmu_id = (mmu_ID_t)0; mmu_id < N_MMU_ID; mmu_id++) {
for (mmu_id = (mmu_ID_t)0; mmu_id < N_MMU_ID; mmu_id++)
mmu_invalidate_cache(mmu_id);
}
}

4
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c
View File

@ -168,9 +168,9 @@ static void store_vector(
//load_vector (&v[1][0], &to[ISP_NWAY]); /* Fetch the next vector, since it will be overwritten. */
hive_uedge *data = (hive_uedge *)v;
for (i = 0; i < ISP_NWAY; i++) {
for (i = 0; i < ISP_NWAY; i++)
hive_sim_wide_pack(data, (hive_wide)&from[i], ISP_VEC_ELEMBITS, i);
}
assert(ISP_BAMEM_BASE[ID] != (hrt_address) - 1);
#if !defined(HRT_MEMORY_ACCESS)
ia_css_device_store(ISP_BAMEM_BASE[ID] + (unsigned long)to, &v, size);

3
drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_2/ia_css_anr2.host.c
View File

@ -22,9 +22,8 @@ ia_css_anr2_vmem_encode(
for (i = 0; i < ANR_PARAM_SIZE; i++) {
unsigned int j;
for (j = 0; j < ISP_VEC_NELEMS; j++) {
for (j = 0; j < ISP_VEC_NELEMS; j++)
to->data[i][j] = from->data[i * ISP_VEC_NELEMS + j];
}
}
}

6
drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ia_css_bnlm.host.c
View File

@ -125,14 +125,12 @@ ia_css_bnlm_vmem_encode(
bnlm_lut_encode(&to->div_lut, div_lut_nearests, div_lut_slopes,
BNLM_DIV_LUT_SIZE);
memset(to->div_lut_intercepts, 0, sizeof(to->div_lut_intercepts));
for (i = 0; i < BNLM_DIV_LUT_SIZE; i++) {
for (i = 0; i < BNLM_DIV_LUT_SIZE; i++)
to->div_lut_intercepts[0][i] = div_lut_intercepts[i];
}
memset(to->power_of_2, 0, sizeof(to->power_of_2));
for (i = 0; i < (ISP_VEC_ELEMBITS - 1); i++) {
for (i = 0; i < (ISP_VEC_ELEMBITS - 1); i++)
to->power_of_2[0][i] = 1 << i;
}
}
/* - Encodes BNLM public parameters into DMEM parameters */

7
drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc2/ia_css_ctc2.host.c
View File

@ -52,13 +52,12 @@ static int ctc2_slope(int y1, int y0, int x1, int x0)
/*the slope must lie within the range
(-max_slope-1) >= (dydx) >= (max_slope)
*/
if (slope <= -max_slope - 1) {
if (slope <= -max_slope - 1)
dydx = -max_slope - 1;
} else if (slope >= max_slope) {
else if (slope >= max_slope)
dydx = max_slope;
} else {
else
dydx = slope;
}
return dydx;
}

13
drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/ia_css_eed1_8.host.c
View File

@ -140,17 +140,14 @@ ia_css_eed1_8_vmem_encode(
assert(tcinv_x[0] == 0);
assert(fcinv_x[0] == 0);
for (j = 1; j < NUMBER_OF_CHGRINV_POINTS; j++) {
for (j = 1; j < NUMBER_OF_CHGRINV_POINTS; j++)
assert(chgrinv_x[j] > chgrinv_x[j - 1]);
}
for (j = 1; j < NUMBER_OF_TCINV_POINTS; j++) {
for (j = 1; j < NUMBER_OF_TCINV_POINTS; j++)
assert(tcinv_x[j] > tcinv_x[j - 1]);
}
for (j = 1; j < NUMBER_OF_FCINV_POINTS; j++) {
for (j = 1; j < NUMBER_OF_FCINV_POINTS; j++)
assert(fcinv_x[j] > fcinv_x[j - 1]);
}
/* The implementation of the calculating 1/x is based on the availability
* of the OP_vec_shuffle16 operation.
@ -260,9 +257,9 @@ ia_css_eed1_8_encode(
to->margin_neg_diff = (from->neg_margin1 - from->neg_margin0);
/* Encode DEWEnhance exp (e_dew_enh_asr) */
for (i = 0; i < (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1); i++) {
for (i = 0; i < (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1); i++)
min_exp = max(min_exp, from->dew_enhance_seg_exp[i]);
}
to->e_dew_enh_asr = 13 - clamp(min_exp, 0, 13);
to->dedgew_max = from->dedgew_max;

3
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
View File

@ -240,9 +240,8 @@ ia_css_s3a_hmem_decode(
/* Calculate sum of histogram of R,
which should not be less than count_for_3a */
sum_r = 0;
for (i = 0; i < HMEM_UNIT_SIZE; i++) {
for (i = 0; i < HMEM_UNIT_SIZE; i++)
sum_r += out_ptr[i].r;
}
if (sum_r < count_for_3a) {
/* histogram is invalid */
return;

6
drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.c
View File

@ -50,9 +50,8 @@ void ia_css_sdis_horicoef_vmem_encode(
assert(size % (IA_CSS_DVS_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof(
short)) == 0);
for (type = 0; type < IA_CSS_DVS_NUM_COEF_TYPES; type++) {
for (type = 0; type < IA_CSS_DVS_NUM_COEF_TYPES; type++)
fill_row(&private[type * stride], &public[type * width], width, padding);
}
}
void ia_css_sdis_vertcoef_vmem_encode(
@ -77,9 +76,8 @@ void ia_css_sdis_vertcoef_vmem_encode(
assert(size % (IA_CSS_DVS_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof(
short)) == 0);
for (type = 0; type < IA_CSS_DVS_NUM_COEF_TYPES; type++) {
for (type = 0; type < IA_CSS_DVS_NUM_COEF_TYPES; type++)
fill_row(&private[type * stride], &public[type * height], height, padding);
}
}
void ia_css_sdis_horiproj_encode(

3
drivers/staging/media/atomisp/pci/runtime/binary/src/binary.c
View File

@ -670,9 +670,8 @@ ia_css_binary_fill_info(const struct ia_css_binary_xinfo *xinfo,
err = ia_css_isp_param_allocate_isp_parameters(
&binary->mem_params, &binary->css_params,
&info->mem_initializers);
if (err) {
if (err)
return err;
}
}
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
{

6
drivers/staging/media/atomisp/pci/runtime/debug/src/ia_css_debug.c
View File

@ -1123,9 +1123,8 @@ ia_css_debug_pipe_graph_dump_prologue(void)
void ia_css_debug_pipe_graph_dump_epilogue(void)
{
if (strlen(ring_buffer) > 0) {
if (strlen(ring_buffer) > 0)
dtrace_dot(ring_buffer);
}
if (pg_inst.stream_format != N_ATOMISP_INPUT_FORMAT) {
/* An input stream format has been set so assume we have
@ -1778,9 +1777,8 @@ static void debug_dump_one_trace(enum TRACE_CORE_ID proc_id)
* When tid value is 111b, the data will be interpreted differently:
* tid val is ignored, major field contains 2 bits (msb) for format type
*/
if (tid_val == FIELD_TID_SEL_FORMAT_PAT) {
if (tid_val == FIELD_TID_SEL_FORMAT_PAT)
dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]);
}
}
switch (dump_format) {
case TRACE_DUMP_FORMAT_POINT:

3
drivers/staging/media/atomisp/pci/runtime/isys/src/virtual_isys.c
View File

@ -295,9 +295,8 @@ static bool create_input_system_channel(
if (!rc)
return false;
if (!acquire_sid(me->stream2mmio_id, &me->stream2mmio_sid_id)) {
if (!acquire_sid(me->stream2mmio_id, &me->stream2mmio_sid_id))
return false;
}
if (!acquire_ib_buffer(
metadata ? cfg->metadata.bits_per_pixel :

3
drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c
View File

@ -575,9 +575,8 @@ static int pipeline_stage_create(
binary = stage_desc->binary;
firmware = stage_desc->firmware;
vf_frame = stage_desc->vf_frame;
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_frame[i] = stage_desc->out_frame[i];
}
stage = kvzalloc_obj(*stage);
if (!stage) {

12
drivers/staging/media/atomisp/pci/sh_css_params.c
View File

@ -1928,9 +1928,8 @@ sh_css_set_per_frame_isp_config_on_pipe(
params = stream->per_frame_isp_params_configs;
/* update new ISP params object with the new config */
if (!sh_css_init_isp_params_from_global(stream, params, false, pipe)) {
if (!sh_css_init_isp_params_from_global(stream, params, false, pipe))
err1 = -EINVAL;
}
err2 = sh_css_init_isp_params_from_config(stream->pipes[0], params, config, pipe);
@ -2004,9 +2003,8 @@ sh_css_init_isp_params_from_config(struct ia_css_pipe *pipe,
* user. */
/* we do not exit from this point immediately to allow internal
* firmware feature testing. */
if (is_dp_10bpp) {
if (is_dp_10bpp)
err = -EINVAL;
}
} else {
err = -EINVAL;
goto exit;
@ -3034,9 +3032,8 @@ process_kernel_parameters(unsigned int pipe_id,
ia_css_ob_configure(&params->stream_configs.ob,
isp_pipe_version, raw_bit_depth);
}
if (params->config_changed[IA_CSS_S3A_ID]) {
if (params->config_changed[IA_CSS_S3A_ID])
ia_css_s3a_configure(raw_bit_depth);
}
/* Copy stage uds parameters to config, since they can differ per stage.
*/
params->crop_config.crop_pos = params->uds[stage->stage_num].crop_pos;
@ -3899,9 +3896,8 @@ sh_css_invalidate_params(struct ia_css_stream *stream)
params->isp_params_changed = true;
for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) {
for (j = 0; j < SH_CSS_MAX_STAGES; j++) {
for (mem = 0; mem < N_IA_CSS_MEMORIES; mem++) {
for (mem = 0; mem < N_IA_CSS_MEMORIES; mem++)
params->isp_mem_params_changed[i][j][mem] = true;
}
}
}