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riscv: dts: allwinner: d1: Add CPU thermal sensor and zone

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The sun20i THS (built in CPU thermal sensor) is supported in code, but
was never added to the device tree. So, add it to the device tree,
along with a thermal zone for the CPU.

Signed-off-by: Alex Studer <alex@studer.dev>

Changes since v1:
 - Move include before defines in sun20i-d1s.dtsi
 - Fix register size for thermal-sensor@2009400
 - Move thermal-sensor@2009400 in SoC to match register address sorting
 - Add thermal-zone for sun8i-t113s.dtsi and fix missing cooling-cells

Link: https://lore.kernel.org/r/20250218020629.1476126-1-alex@studer.dev
Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
Link: https://patch.msgid.link/20260113182951.1059690-1-lukas.schmid@netcube.li
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
This commit is contained in:
Alex Studer 2026-01-13 19:29:48 +01:00 committed by Chen-Yu Tsai
parent db5e9260be
commit f36e738549
3 changed files with 80 additions and 0 deletions
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33
arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
View File

@ -4,6 +4,7 @@
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <riscv/allwinner/sunxi-d1s-t113.dtsi>
#include <riscv/allwinner/sunxi-d1-t113.dtsi>
@ -20,6 +21,7 @@ cpu0: cpu@0 {
reg = <0>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
};
cpu1: cpu@1 {
@ -28,6 +30,7 @@ cpu1: cpu@1 {
reg = <1>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
};
};
@ -56,4 +59,34 @@ pmu {
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths>;
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};

31
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
View File

@ -1,6 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
#include <dt-bindings/thermal/thermal.h>
#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
#include "sunxi-d1s-t113.dtsi"
@ -115,4 +117,33 @@ pmu {
<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths>;
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};

16
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
View File

@ -229,6 +229,18 @@ gpadc: adc@2009000 {
#io-channel-cells = <1>;
};
ths: thermal-sensor@2009400 {
compatible = "allwinner,sun20i-d1-ths";
reg = <0x2009400 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_THS>;
clock-names = "bus";
resets = <&ccu RST_BUS_THS>;
nvmem-cells = <&ths_calibration>;
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <0>;
};
dmic: dmic@2031000 {
compatible = "allwinner,sun20i-d1-dmic",
"allwinner,sun50i-h6-dmic";
@ -489,6 +501,10 @@ sid: efuse@3006000 {
reg = <0x3006000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ths_calibration: thermal-sensor-calibration@14 {
reg = <0x14 0x8>;
};
};
crypto: crypto@3040000 {