dt-bindings: PCI: qcom-ep: Add SAR2130P compatible

Add support for using the PCI controller in the PCIe Endpoint mode on
the SAR2130P platform.

This is needed, as it is not possible to use a compatible fallback on
any other platform since SAR2130P uses slightly different set of clocks.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250221-sar2130p-pci-v3-5-61a0fdfb75b4@linaro.org
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2025-02-21 17:52:03 +02:00 committed by Krzysztof Wilczyński
parent f9d7bbd050
commit f325b07861
No known key found for this signature in database
GPG Key ID: 7C64768D3DE334E7

View File

@ -14,6 +14,7 @@ properties:
oneOf:
- enum:
- qcom,sa8775p-pcie-ep
- qcom,sar2130p-pcie-ep
- qcom,sdx55-pcie-ep
- qcom,sm8450-pcie-ep
- items:
@ -44,11 +45,11 @@ properties:
clocks:
minItems: 5
maxItems: 8
maxItems: 9
clock-names:
minItems: 5
maxItems: 8
maxItems: 9
qcom,perst-regs:
description: Reference to a syscon representing TCSR followed by the two
@ -132,6 +133,37 @@ required:
allOf:
- $ref: pci-ep.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sar2130p-pcie-ep
then:
properties:
clocks:
items:
- description: PCIe Auxiliary clock
- description: PCIe CFG AHB clock
- description: PCIe Master AXI clock
- description: PCIe Slave AXI clock
- description: PCIe Slave Q2A AXI clock
- description: PCIe DDRSS SF TBU clock
- description: PCIe AGGRE NOC AXI clock
- description: PCIe CFG NOC AXI clock
- description: PCIe QMIP AHB clock
clock-names:
items:
- const: aux
- const: cfg
- const: bus_master
- const: bus_slave
- const: slave_q2a
- const: ddrss_sf_tbu
- const: aggre_noc_axi
- const: cnoc_sf_axi
- const: qmip_pcie_ahb
- if:
properties:
compatible: