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drm/amdgpu: drop MES 10.1 support v3

Browse Source 
It was an enablement vehicle for MES 11 and was never
productized.  Remove it.

v2: drop additional checks in the GFX10 code.
v3: drop mes_api_def.h

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2024-05-02 16:50:39 -04:00
parent 04c1ea9d64
commit f2a1fbdd1f
8 changed files with 72 additions and 2021 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/amdgpu/Makefile
View File

@ -187,7 +187,6 @@ amdgpu-y += \
# add MES block
amdgpu-y += \
amdgpu_mes.o \
mes_v10_1.o \
mes_v11_0.o \
mes_v12_0.o

20
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
View File

@ -94,7 +94,6 @@
#include "vcn_v4_0_5.h"
#include "jpeg_v4_0_5.h"
#include "amdgpu_vkms.h"
#include "mes_v10_1.h"
#include "mes_v11_0.h"
#include "mes_v12_0.h"
#include "smuio_v11_0.h"
@ -2309,25 +2308,6 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
{
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 3):
case IP_VERSION(10, 1, 4):
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 3):
case IP_VERSION(10, 3, 4):
case IP_VERSION(10, 3, 5):
case IP_VERSION(10, 3, 6):
if (amdgpu_mes) {
amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
adev->enable_mes = true;
if (amdgpu_mes_kiq)
adev->enable_mes_kiq = true;
}
break;
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):

281
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
View File

@ -3733,14 +3733,8 @@ static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
enum amdgpu_unmap_queues_action action,
u64 gpu_addr, u64 seq)
{
struct amdgpu_device *adev = kiq_ring->adev;
uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
return;
}
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
PACKET3_UNMAP_QUEUES_ACTION(action) |
@ -3998,33 +3992,18 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
memset(&ib, 0, sizeof(ib));
if (ring->is_mes_queue) {
uint32_t padding, offset;
r = amdgpu_device_wb_get(adev, &index);
if (r)
return r;
offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
padding = amdgpu_mes_ctx_get_offs(ring,
AMDGPU_MES_CTX_PADDING_OFFS);
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
cpu_ptr = &adev->wb.wb[index];
ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
*cpu_ptr = cpu_to_le32(0xCAFEDEAD);
} else {
r = amdgpu_device_wb_get(adev, &index);
if (r)
return r;
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
cpu_ptr = &adev->wb.wb[index];
r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
if (r) {
DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
goto err1;
}
r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
if (r) {
DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
goto err1;
}
ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
@ -4051,12 +4030,10 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
else
r = -EINVAL;
err2:
if (!ring->is_mes_queue)
amdgpu_ib_free(adev, &ib, NULL);
amdgpu_ib_free(adev, &ib, NULL);
dma_fence_put(f);
err1:
if (!ring->is_mes_queue)
amdgpu_device_wb_free(adev, index);
amdgpu_device_wb_free(adev, index);
return r;
}
@ -4831,18 +4808,16 @@ static int gfx_v10_0_sw_init(void *handle)
}
}
if (!adev->enable_mes_kiq) {
r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
if (r) {
DRM_ERROR("Failed to init KIQ BOs!\n");
return r;
}
r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
if (r)
return r;
r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
if (r) {
DRM_ERROR("Failed to init KIQ BOs!\n");
return r;
}
r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
if (r)
return r;
r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
if (r)
return r;
@ -4896,10 +4871,8 @@ static int gfx_v10_0_sw_fini(void *handle)
amdgpu_gfx_mqd_sw_fini(adev, 0);
if (!adev->enable_mes_kiq) {
amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
amdgpu_gfx_kiq_fini(adev, 0);
}
amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
amdgpu_gfx_kiq_fini(adev, 0);
gfx_v10_0_pfp_fini(adev);
gfx_v10_0_ce_fini(adev);
@ -7103,10 +7076,7 @@ static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
return r;
}
if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
r = amdgpu_mes_kiq_hw_init(adev);
else
r = gfx_v10_0_kiq_resume(adev);
r = gfx_v10_0_kiq_resume(adev);
if (r)
return r;
@ -8427,45 +8397,17 @@ static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
uint32_t *wptr_saved;
uint32_t *is_queue_unmap;
uint64_t aggregated_db_index;
uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
uint64_t wptr_tmp;
if (ring->is_mes_queue) {
wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
sizeof(uint32_t));
aggregated_db_index =
amdgpu_mes_get_aggregated_doorbell_index(adev,
AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
wptr_tmp = ring->wptr & ring->buf_mask;
atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
*wptr_saved = wptr_tmp;
/* assume doorbell always being used by mes mapped queue */
if (*is_queue_unmap) {
WDOORBELL64(aggregated_db_index, wptr_tmp);
WDOORBELL64(ring->doorbell_index, wptr_tmp);
} else {
WDOORBELL64(ring->doorbell_index, wptr_tmp);
if (*is_queue_unmap)
WDOORBELL64(aggregated_db_index, wptr_tmp);
}
if (ring->use_doorbell) {
/* XXX check if swapping is necessary on BE */
atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
ring->wptr);
WDOORBELL64(ring->doorbell_index, ring->wptr);
} else {
if (ring->use_doorbell) {
/* XXX check if swapping is necessary on BE */
atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
ring->wptr);
WDOORBELL64(ring->doorbell_index, ring->wptr);
} else {
WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
lower_32_bits(ring->wptr));
WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
upper_32_bits(ring->wptr));
}
WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
lower_32_bits(ring->wptr));
WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
upper_32_bits(ring->wptr));
}
}
@ -8490,42 +8432,13 @@ static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
uint32_t *wptr_saved;
uint32_t *is_queue_unmap;
uint64_t aggregated_db_index;
uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
uint64_t wptr_tmp;
if (ring->is_mes_queue) {
wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
sizeof(uint32_t));
aggregated_db_index =
amdgpu_mes_get_aggregated_doorbell_index(adev,
AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
wptr_tmp = ring->wptr & ring->buf_mask;
atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
*wptr_saved = wptr_tmp;
/* assume doorbell always used by mes mapped queue */
if (*is_queue_unmap) {
WDOORBELL64(aggregated_db_index, wptr_tmp);
WDOORBELL64(ring->doorbell_index, wptr_tmp);
} else {
WDOORBELL64(ring->doorbell_index, wptr_tmp);
if (*is_queue_unmap)
WDOORBELL64(aggregated_db_index, wptr_tmp);
}
if (ring->use_doorbell) {
atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
ring->wptr);
WDOORBELL64(ring->doorbell_index, ring->wptr);
} else {
/* XXX check if swapping is necessary on BE */
if (ring->use_doorbell) {
atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
ring->wptr);
WDOORBELL64(ring->doorbell_index, ring->wptr);
} else {
BUG(); /* only DOORBELL method supported on gfx10 now */
}
BUG(); /* only DOORBELL method supported on gfx10 now */
}
}
@ -8584,10 +8497,6 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
(!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
}
if (ring->is_mes_queue)
/* inherit vmid from mqd */
control |= 0x400000;
amdgpu_ring_write(ring, header);
BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
amdgpu_ring_write(ring,
@ -8607,10 +8516,6 @@ static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
if (ring->is_mes_queue)
/* inherit vmid from mqd */
control |= 0x40000000;
/* Currently, there is a high possibility to get wave ID mismatch
* between ME and GDS, leading to a hw deadlock, because ME generates
* different wave IDs than the GDS expects. This situation happens
@ -8668,8 +8573,7 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
amdgpu_ring_write(ring, upper_32_bits(addr));
amdgpu_ring_write(ring, lower_32_bits(seq));
amdgpu_ring_write(ring, upper_32_bits(seq));
amdgpu_ring_write(ring, ring->is_mes_queue ?
(ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
amdgpu_ring_write(ring, 0);
}
static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
@ -8697,10 +8601,7 @@ static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
unsigned int vmid, uint64_t pd_addr)
{
if (ring->is_mes_queue)
gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
else
amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
/* compute doesn't have PFP */
if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
@ -8851,19 +8752,9 @@ static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
if (ring->is_mes_queue) {
offset = offsetof(struct amdgpu_mes_ctx_meta_data,
gfx[0].gfx_meta_data) +
offsetof(struct v10_gfx_meta_data, ce_payload);
ce_payload_gpu_addr =
amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
ce_payload_cpu_addr =
amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
} else {
offset = offsetof(struct v10_gfx_meta_data, ce_payload);
ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
}
offset = offsetof(struct v10_gfx_meta_data, ce_payload);
ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
@ -8889,28 +8780,13 @@ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
void *de_payload_cpu_addr;
int cnt;
if (ring->is_mes_queue) {
offset = offsetof(struct amdgpu_mes_ctx_meta_data,
gfx[0].gfx_meta_data) +
offsetof(struct v10_gfx_meta_data, de_payload);
de_payload_gpu_addr =
amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
de_payload_cpu_addr =
amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
offset = offsetof(struct v10_gfx_meta_data, de_payload);
de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
offset = offsetof(struct amdgpu_mes_ctx_meta_data,
gfx[0].gds_backup) +
offsetof(struct v10_gfx_meta_data, de_payload);
gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
} else {
offset = offsetof(struct v10_gfx_meta_data, de_payload);
de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
AMDGPU_CSA_SIZE - adev->gds.gds_size,
PAGE_SIZE);
}
gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
AMDGPU_CSA_SIZE - adev->gds.gds_size,
PAGE_SIZE);
de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
@ -9162,49 +9038,34 @@ static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
int i;
u8 me_id, pipe_id, queue_id;
struct amdgpu_ring *ring;
uint32_t mes_queue_id = entry->src_data[0];
DRM_DEBUG("IH: CP EOP\n");
if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
struct amdgpu_mes_queue *queue;
me_id = (entry->ring_id & 0x0c) >> 2;
pipe_id = (entry->ring_id & 0x03) >> 0;
queue_id = (entry->ring_id & 0x70) >> 4;
mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
spin_lock(&adev->mes.queue_id_lock);
queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
if (queue) {
DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
amdgpu_fence_process(queue->ring);
}
spin_unlock(&adev->mes.queue_id_lock);
} else {
me_id = (entry->ring_id & 0x0c) >> 2;
pipe_id = (entry->ring_id & 0x03) >> 0;
queue_id = (entry->ring_id & 0x70) >> 4;
switch (me_id) {
case 0:
if (pipe_id == 0)
amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
else
amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
break;
case 1:
case 2:
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
/* Per-queue interrupt is supported for MEC starting from VI.
* The interrupt can only be enabled/disabled per pipe instead
* of per queue.
*/
if ((ring->me == me_id) &&
(ring->pipe == pipe_id) &&
(ring->queue == queue_id))
amdgpu_fence_process(ring);
}
break;
switch (me_id) {
case 0:
if (pipe_id == 0)
amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
else
amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
break;
case 1:
case 2:
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
/* Per-queue interrupt is supported for MEC starting from VI.
* The interrupt can only be enabled/disabled per pipe instead
* of per queue.
*/
if ((ring->me == me_id) &&
(ring->pipe == pipe_id) &&
(ring->queue == queue_id))
amdgpu_fence_process(ring);
}
break;
}
return 0;

1189
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
View File

File diff suppressed because it is too large Load Diff

29
drivers/gpu/drm/amd/amdgpu/mes_v10_1.h
View File

@ -1,29 +0,0 @@
/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __MES_V10_1_H__
#define __MES_V10_1_H__
extern const struct amdgpu_ip_block_version mes_v10_1_ip_block;
#endif

1
drivers/gpu/drm/amd/amdgpu/nv.c
View File

@ -59,7 +59,6 @@
#include "vcn_v3_0.h"
#include "jpeg_v3_0.h"
#include "amdgpu_vkms.h"
#include "mes_v10_1.h"
#include "mxgpu_nv.h"
#include "smuio_v11_0.h"
#include "smuio_v11_0_6.h"

2
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
View File

@ -35,7 +35,7 @@
#include "cik_regs.h"
#include "kfd_kernel_queue.h"
#include "amdgpu_amdkfd.h"
#include "mes_api_def.h"
#include "mes_v11_api_def.h"
#include "kfd_debug.h"
/* Size of the per-pipe EOP queue */

570
drivers/gpu/drm/amd/include/mes_api_def.h
View File

@ -1,570 +0,0 @@
/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __MES_API_DEF_H__
#define __MES_API_DEF_H__
#pragma pack(push, 4)
#define MES_API_VERSION 1
/* Driver submits one API(cmd) as a single Frame and this command size is same
* for all API to ease the debugging and parsing of ring buffer.
*/
enum { API_FRAME_SIZE_IN_DWORDS = 64 };
/* To avoid command in scheduler context to be overwritten whenever multiple
* interrupts come in, this creates another queue.
*/
enum { API_NUMBER_OF_COMMAND_MAX = 32 };
enum MES_API_TYPE {
MES_API_TYPE_SCHEDULER = 1,
MES_API_TYPE_MAX
};
enum MES_SCH_API_OPCODE {
MES_SCH_API_SET_HW_RSRC = 0,
MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */
MES_SCH_API_ADD_QUEUE = 2,
MES_SCH_API_REMOVE_QUEUE = 3,
MES_SCH_API_PERFORM_YIELD = 4,
MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5,
MES_SCH_API_SUSPEND = 6,
MES_SCH_API_RESUME = 7,
MES_SCH_API_RESET = 8,
MES_SCH_API_SET_LOG_BUFFER = 9,
MES_SCH_API_CHANGE_GANG_PRORITY = 10,
MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
MES_SCH_API_PROGRAM_GDS = 12,
MES_SCH_API_SET_DEBUG_VMID = 13,
MES_SCH_API_MISC = 14,
MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15,
MES_SCH_API_AMD_LOG = 16,
MES_SCH_API_MAX = 0xFF
};
union MES_API_HEADER {
struct {
uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
uint32_t opcode : 8;
uint32_t dwsize : 8; /* including header */
uint32_t reserved : 12;
};
uint32_t u32All;
};
enum MES_AMD_PRIORITY_LEVEL {
AMD_PRIORITY_LEVEL_LOW = 0,
AMD_PRIORITY_LEVEL_NORMAL = 1,
AMD_PRIORITY_LEVEL_MEDIUM = 2,
AMD_PRIORITY_LEVEL_HIGH = 3,
AMD_PRIORITY_LEVEL_REALTIME = 4,
AMD_PRIORITY_NUM_LEVELS
};
enum MES_QUEUE_TYPE {
MES_QUEUE_TYPE_GFX,
MES_QUEUE_TYPE_COMPUTE,
MES_QUEUE_TYPE_SDMA,
MES_QUEUE_TYPE_MAX,
};
struct MES_API_STATUS {
uint64_t api_completion_fence_addr;
uint64_t api_completion_fence_value;
};
enum { MAX_COMPUTE_PIPES = 8 };
enum { MAX_GFX_PIPES = 2 };
enum { MAX_SDMA_PIPES = 2 };
enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
enum { MAX_GFX_HQD_PER_PIPE = 8 };
enum { MAX_SDMA_HQD_PER_PIPE = 10 };
enum { MAX_QUEUES_IN_A_GANG = 8 };
enum VM_HUB_TYPE {
VM_HUB_TYPE_GC = 0,
VM_HUB_TYPE_MM = 1,
VM_HUB_TYPE_MAX,
};
enum { VMID_INVALID = 0xffff };
enum { MAX_VMID_GCHUB = 16 };
enum { MAX_VMID_MMHUB = 16 };
enum MES_LOG_OPERATION {
MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
};
enum MES_LOG_CONTEXT_STATE {
MES_LOG_CONTEXT_STATE_IDLE = 0,
MES_LOG_CONTEXT_STATE_RUNNING = 1,
MES_LOG_CONTEXT_STATE_READY = 2,
MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
MES_LOG_CONTEXT_STATE_INVALID = 0xF,
};
struct MES_LOG_CONTEXT_STATE_CHANGE {
void *h_context;
enum MES_LOG_CONTEXT_STATE new_context_state;
};
struct MES_LOG_QUEUE_NEW_WORK {
uint64_t h_queue;
uint64_t reserved;
};
struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
uint64_t h_queue;
uint64_t h_sync_object;
};
struct MES_LOG_QUEUE_NO_MORE_WORK {
uint64_t h_queue;
uint64_t reserved;
};
struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
uint64_t h_queue;
uint64_t h_sync_object;
};
struct MES_LOG_ENTRY_HEADER {
uint32_t first_free_entry_index;
uint32_t wraparound_count;
uint64_t number_of_entries;
uint64_t reserved[2];
};
struct MES_LOG_ENTRY_DATA {
uint64_t gpu_time_stamp;
uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
uint32_t reserved_operation_type_bits;
union {
struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
uint64_t all[2];
};
};
struct MES_LOG_BUFFER {
struct MES_LOG_ENTRY_HEADER header;
struct MES_LOG_ENTRY_DATA entries[1];
};
enum MES_SWIP_TO_HWIP_DEF {
MES_MAX_HWIP_SEGMENT = 6,
};
union MESAPI_SET_HW_RESOURCES {
struct {
union MES_API_HEADER header;
uint32_t vmid_mask_mmhub;
uint32_t vmid_mask_gfxhub;
uint32_t gds_size;
uint32_t paging_vmid;
uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];
uint32_t gfx_hqd_mask[MAX_GFX_PIPES];
uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];
uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
uint64_t g_sch_ctx_gpu_mc_ptr;
uint64_t query_status_fence_gpu_mc_ptr;
uint32_t gc_base[MES_MAX_HWIP_SEGMENT];
uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];
uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];
struct MES_API_STATUS api_status;
union {
struct {
uint32_t disable_reset : 1;
uint32_t use_different_vmid_compute : 1;
uint32_t disable_mes_log : 1;
uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
uint32_t second_gfx_pipe_enabled : 1;
uint32_t enable_level_process_quantum_check : 1;
uint32_t apply_cwsr_program_all_vmid_sq_shader_tba_registers_wa : 1;
uint32_t enable_mqd_active_poll : 1;
uint32_t disable_timer_int : 1;
uint32_t reserved : 22;
};
uint32_t uint32_t_all;
};
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__ADD_QUEUE {
struct {
union MES_API_HEADER header;
uint32_t process_id;
uint64_t page_table_base_addr;
uint64_t process_va_start;
uint64_t process_va_end;
uint64_t process_quantum;
uint64_t process_context_addr;
uint64_t gang_quantum;
uint64_t gang_context_addr;
uint32_t inprocess_gang_priority;
enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
uint32_t doorbell_offset;
uint64_t mqd_addr;
uint64_t wptr_addr;
uint64_t h_context;
uint64_t h_queue;
enum MES_QUEUE_TYPE queue_type;
uint32_t gds_base;
uint32_t gds_size;
uint32_t gws_base;
uint32_t gws_size;
uint32_t oa_mask;
uint64_t trap_handler_addr;
uint32_t vm_context_cntl;
struct {
uint32_t paging : 1;
uint32_t debug_vmid : 4;
uint32_t program_gds : 1;
uint32_t is_gang_suspended : 1;
uint32_t is_tmz_queue : 1;
uint32_t map_kiq_utility_queue : 1;
uint32_t reserved : 23;
};
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__REMOVE_QUEUE {
struct {
union MES_API_HEADER header;
uint32_t doorbell_offset;
uint64_t gang_context_addr;
struct {
uint32_t unmap_legacy_gfx_queue : 1;
uint32_t unmap_kiq_utility_queue : 1;
uint32_t preempt_legacy_gfx_queue : 1;
uint32_t reserved : 29;
};
struct MES_API_STATUS api_status;
uint32_t pipe_id;
uint32_t queue_id;
uint64_t tf_addr;
uint32_t tf_data;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__SET_SCHEDULING_CONFIG {
struct {
union MES_API_HEADER header;
/* Grace period when preempting another priority band for this
* priority band. The value for idle priority band is ignored,
* as it never preempts other bands.
*/
uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
/* Default quantum for scheduling across processes within
* a priority band.
*/
uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
/* Default grace period for processes that preempt each other
* within a priority band.
*/
uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
/* For normal level this field specifies the target GPU
* percentage in situations when it's starved by the high level.
* Valid values are between 0 and 50, with the default being 10.
*/
uint32_t normal_yield_percent;
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__PERFORM_YIELD {
struct {
union MES_API_HEADER header;
uint32_t dummy;
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
struct {
union MES_API_HEADER header;
uint32_t inprocess_gang_priority;
enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
uint64_t gang_quantum;
uint64_t gang_context_addr;
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__SUSPEND {
struct {
union MES_API_HEADER header;
/* false - suspend all gangs; true - specific gang */
struct {
uint32_t suspend_all_gangs : 1;
uint32_t reserved : 31;
};
/* gang_context_addr is valid only if suspend_all = false */
uint64_t gang_context_addr;
uint64_t suspend_fence_addr;
uint32_t suspend_fence_value;
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__RESUME {
struct {
union MES_API_HEADER header;
/* false - resume all gangs; true - specified gang */
struct {
uint32_t resume_all_gangs : 1;
uint32_t reserved : 31;
};
/* valid only if resume_all_gangs = false */
uint64_t gang_context_addr;
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__RESET {
struct {
union MES_API_HEADER header;
struct {
/* Only reset the queue given by doorbell_offset (not entire gang) */
uint32_t reset_queue_only : 1;
/* Hang detection first then reset any queues that are hung */
uint32_t hang_detect_then_reset : 1;
/* Only do hang detection (no reset) */
uint32_t hang_detect_only : 1;
/* Rest HP and LP kernel queues not managed by MES */
uint32_t reset_legacy_gfx : 1;
uint32_t reserved : 28;
};
uint64_t gang_context_addr;
/* valid only if reset_queue_only = true */
uint32_t doorbell_offset;
/* valid only if hang_detect_then_reset = true */
uint64_t doorbell_offset_addr;
enum MES_QUEUE_TYPE queue_type;
/* valid only if reset_legacy_gfx = true */
uint32_t pipe_id_lp;
uint32_t queue_id_lp;
uint32_t vmid_id_lp;
uint64_t mqd_mc_addr_lp;
uint32_t doorbell_offset_lp;
uint64_t wptr_addr_lp;
uint32_t pipe_id_hp;
uint32_t queue_id_hp;
uint32_t vmid_id_hp;
uint64_t mqd_mc_addr_hp;
uint32_t doorbell_offset_hp;
uint64_t wptr_addr_hp;
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__SET_LOGGING_BUFFER {
struct {
union MES_API_HEADER header;
/* There are separate log buffers for each queue type */
enum MES_QUEUE_TYPE log_type;
/* Log buffer GPU Address */
uint64_t logging_buffer_addr;
/* number of entries in the log buffer */
uint32_t number_of_entries;
/* Entry index at which CPU interrupt needs to be signalled */
uint32_t interrupt_entry;
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__QUERY_MES_STATUS {
struct {
union MES_API_HEADER header;
bool mes_healthy; /* 0 - not healthy, 1 - healthy */
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__PROGRAM_GDS {
struct {
union MES_API_HEADER header;
uint64_t process_context_addr;
uint32_t gds_base;
uint32_t gds_size;
uint32_t gws_base;
uint32_t gws_size;
uint32_t oa_mask;
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__SET_DEBUG_VMID {
struct {
union MES_API_HEADER header;
struct MES_API_STATUS api_status;
union {
struct {
uint32_t use_gds : 1;
uint32_t reserved : 31;
} flags;
uint32_t u32All;
};
uint32_t reserved;
uint32_t debug_vmid;
uint64_t process_context_addr;
uint64_t page_table_base_addr;
uint64_t process_va_start;
uint64_t process_va_end;
uint32_t gds_base;
uint32_t gds_size;
uint32_t gws_base;
uint32_t gws_size;
uint32_t oa_mask;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
enum MESAPI_MISC_OPCODE {
MESAPI_MISC__MODIFY_REG,
MESAPI_MISC__INV_GART,
MESAPI_MISC__QUERY_STATUS,
MESAPI_MISC__MAX,
};
enum MODIFY_REG_SUBCODE {
MODIFY_REG__OVERWRITE,
MODIFY_REG__RMW_OR,
MODIFY_REG__RMW_AND,
MODIFY_REG__MAX,
};
enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
struct MODIFY_REG {
enum MODIFY_REG_SUBCODE subcode;
uint32_t reg_offset;
uint32_t reg_value;
};
struct INV_GART {
uint64_t inv_range_va_start;
uint64_t inv_range_size;
};
struct QUERY_STATUS {
uint32_t context_id;
};
union MESAPI__MISC {
struct {
union MES_API_HEADER header;
enum MESAPI_MISC_OPCODE opcode;
struct MES_API_STATUS api_status;
union {
struct MODIFY_REG modify_reg;
struct INV_GART inv_gart;
struct QUERY_STATUS query_status;
uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
};
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__UPDATE_ROOT_PAGE_TABLE {
struct {
union MES_API_HEADER header;
uint64_t page_table_base_addr;
uint64_t process_context_addr;
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI_AMD_LOG {
struct {
union MES_API_HEADER header;
uint64_t p_buffer_memory;
uint64_t p_buffer_size_used;
struct MES_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
#pragma pack(pop)
#endif