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drm/i915/display: Program TRANS_VTOTAL from mode vtotal

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There are monitors being sensitive to MSA and end up
blanking out when we override Vtotal, DP transcoder
uses TRANS_VTOTAL to derive MSA VTotal. Avoid overriding
crtc_vtotal to 1 on platform which supports VRR Timing
generator and always program VTOTAL from mode timing in
transcoder timing paths.

--v2:
- Remove write to crtc_state->hw.adjusted_mode.crtc_vtotal
during intel_vrr_get_config. (Ankit)
- Fix merge conflicts.

Bspec: 70001
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260617045850.862100-1-mitulkumar.ajitkumar.golani@intel.com
This commit is contained in:
Mitul Golani 2026-06-17 10:28:50 +05:30 committed by Suraj Kandpal
parent 94c0b93dc2
commit f26a8df8df
2 changed files with 0 additions and 27 deletions
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17
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -2737,15 +2737,6 @@ void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state,
HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
/*
* For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
* bits are not required. Since the support for these bits is going to
* be deprecated in upcoming platforms, avoid writing these bits for the
* platforms that do not use legacy Timing Generator.
*/
if (intel_vrr_always_use_vrr_tg(display))
crtc_vtotal = 1;
intel_de_write(display, TRANS_VTOTAL(display, transcoder), intel_de_write(display, TRANS_VTOTAL(display, transcoder),
VACTIVE(crtc_vdisplay - 1) | VACTIVE(crtc_vdisplay - 1) |
VTOTAL(crtc_vtotal - 1)); VTOTAL(crtc_vtotal - 1));
@ -2834,14 +2825,6 @@ void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state,
intel_de_write(display, TRANS_VSYNC(display, transcoder), intel_de_write(display, TRANS_VSYNC(display, transcoder),
VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
/*
* For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
* bits are not required. Since the support for these bits is going to
* be deprecated in upcoming platforms, avoid writing these bits for the
* platforms that do not use legacy Timing Generator.
*/
if (intel_vrr_always_use_vrr_tg(display))
crtc_vtotal = 1;
/* /*
* The double buffer latch point for TRANS_VTOTAL * The double buffer latch point for TRANS_VTOTAL

10
drivers/gpu/drm/i915/display/intel_vrr.c
View File

@ -1102,16 +1102,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display); crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);
} }
/*
* For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
* bits are not filled. Since for these platforms TRAN_VMIN is always
* filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for
* adjusted_mode.
*/
if (intel_vrr_always_use_vrr_tg(display))
crtc_state->hw.adjusted_mode.crtc_vtotal =
intel_vrr_vmin_vtotal(crtc_state);
if (HAS_AS_SDP(display)) { if (HAS_AS_SDP(display)) {
trans_vrr_vsync = trans_vrr_vsync =
intel_de_read(display, intel_de_read(display,