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drm/amdgpu: Save nps to eeprom
nps info saved together with bad page makes bad page parsing more efficient Signed-off-by: ganglxie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -852,6 +852,7 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
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{
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struct amdgpu_device *adev = to_amdgpu_device(control);
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int res, i;
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uint64_t nps = AMDGPU_NPS1_PARTITION_MODE;
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if (!__is_ras_eeprom_supported(adev))
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return 0;
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@ -865,9 +866,12 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
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return -EINVAL;
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}
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if (adev->gmc.gmc_funcs->query_mem_partition_mode)
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nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
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/* set the new channel index flag */
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for (i = 0; i < num; i++)
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record[i].retired_page |= UMC_CHANNEL_IDX_V2;
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record[i].retired_page |= (nps << UMC_NPS_SHIFT);
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mutex_lock(&control->ras_tbl_mutex);
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@ -881,7 +885,7 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
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/* clear channel index flag, the flag is only saved on eeprom */
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for (i = 0; i < num; i++)
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record[i].retired_page &= ~UMC_CHANNEL_IDX_V2;
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record[i].retired_page &= ~(nps << UMC_NPS_SHIFT);
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return res;
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}
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@ -71,6 +71,13 @@
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*/
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#define UMC_CHANNEL_IDX_V2 BIT_ULL(47)
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/*
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* save nps value to eeprom_table_record.retired_page[47:40],
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* the channel index flag above will be retired.
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*/
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#define UMC_NPS_SHIFT 40
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#define UMC_NPS_MASK 0xffULL
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typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst,
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uint32_t umc_inst, uint32_t ch_inst, void *data);
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