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clk: renesas: r8a08g046: Add support for PLL6

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Add support for the PLL6 clk by registering it with rzg2l-cpg driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260326110648.29389-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2026-03-26 11:06:37 +00:00 committed by Geert Uytterhoeven
parent 78db1faa6b
commit f232745679
1 changed files with 6 additions and 0 deletions
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6
drivers/clk/renesas/r9a08g046-cpg.c
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@ -29,6 +29,9 @@
#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
/* PLL 1/4/6/7 configuration registers macro. */
#define G3L_PLL1467_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12 | (setting))
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R9A08G046_USB_SCLK,
@ -45,6 +48,7 @@ enum clk_ids {
CLK_PLL2_DIV2,
CLK_PLL3,
CLK_PLL3_DIV2,
CLK_PLL6,
/* Module Clocks */
MOD_CLK_BASE,
@ -78,6 +82,8 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
/* Internal Core Clocks */
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
DEF_G3L_PLL(".pll6", CLK_PLL6, CLK_EXTAL, G3L_PLL1467_CONF(0x54, 0x58, 0),
500000000UL),
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),