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Merge branch 'octeontx2-pf-extend-link-modes-support'

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Hariprasad Kelam says:

====================
Octeontx2-pf: extend link modes support

This series of patches adds multi advertise mode support along with
other improvements in link mode management code flow.

Patch1: Currently all SGMII modes 10/100/1000baseT are mapped with
        single firmware mode. This patch updates these link modes
        with corresponding firmware modes.

Patch2: Due to limitation in current kernel <-> firmware communication,
        link modes are divided into multiple groups, and identified
        with their group index.

Patch3: Adds support for multi advertise mode.
====================

Link: https://patch.msgid.link/20250625092107.9746-1-hkelam@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2025-06-27 16:56:02 -07:00
commit f22e6fdf7b
6 changed files with 113 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
View File

@ -1182,17 +1182,25 @@ static int cgx_link_usertable_index_map(int speed)
static void set_mod_args(struct cgx_set_link_mode_args *args,
u32 speed, u8 duplex, u8 autoneg, u64 mode)
{
/* Fill default values incase of user did not pass
* valid parameters
int mode_baseidx;
u8 cgx_mode;
if (args->multimode) {
args->mode |= mode;
return;
}
/* Derive mode_base_idx and mode fields based
* on cgx_mode value
*/
if (args->duplex == DUPLEX_UNKNOWN)
args->duplex = duplex;
if (args->speed == SPEED_UNKNOWN)
args->speed = speed;
if (args->an == AUTONEG_UNKNOWN)
args->an = autoneg;
cgx_mode = find_first_bit((unsigned long *)&mode,
CGX_MODE_MAX);
args->mode = mode;
args->ports = 0;
mode_baseidx = cgx_mode - 41;
if (mode_baseidx > 0) {
args->mode_baseidx = 1;
args->mode = BIT_ULL(mode_baseidx);
}
}
static void otx2_map_ethtool_link_modes(u64 bitmask,
@ -1200,16 +1208,16 @@ static void otx2_map_ethtool_link_modes(u64 bitmask,
{
switch (bitmask) {
case ETHTOOL_LINK_MODE_10baseT_Half_BIT:
set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII));
set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT));
break;
case ETHTOOL_LINK_MODE_10baseT_Full_BIT:
set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII));
set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT));
break;
case ETHTOOL_LINK_MODE_100baseT_Half_BIT:
set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII));
set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT));
break;
case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII));
set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT));
break;
case ETHTOOL_LINK_MODE_1000baseT_Half_BIT:
set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII));
@ -1481,25 +1489,36 @@ int cgx_get_fwdata_base(u64 *base)
}
int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
struct cgx_lmac_fwdata_s *linkmodes,
int cgx_id, int lmac_id)
{
struct cgx *cgx = cgxd;
u64 req = 0, resp;
u8 bit;
if (!cgx)
return -ENODEV;
if (args.mode)
otx2_map_ethtool_link_modes(args.mode, &args);
if (!args.speed && args.duplex && !args.an)
return -EINVAL;
for_each_set_bit(bit, args.advertising,
__ETHTOOL_LINK_MODE_MASK_NBITS)
otx2_map_ethtool_link_modes(bit, &args);
if (args.multimode) {
if (linkmodes->advertised_link_modes_own != CGX_CMD_OWN_NS)
return -EBUSY;
linkmodes->advertised_link_modes = args.mode;
/* Update ownership */
linkmodes->advertised_link_modes_own = CGX_CMD_OWN_FIRMWARE;
args.mode = GENMASK_ULL(41, 0);
}
req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req);
req = FIELD_SET(CMDMODECHANGE_SPEED,
cgx_link_usertable_index_map(args.speed), req);
req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req);
req = FIELD_SET(CMDMODECHANGE_AN, args.an, req);
req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req);
req = FIELD_SET(CMDMODECHANGE_MODE_BASEIDX, args.mode_baseidx, req);
req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req);
return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);

1
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
View File

@ -171,6 +171,7 @@ int cgx_set_fec(u64 fec, int cgx_id, int lmac_id);
int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);
int cgx_get_phy_fec_stats(void *cgxd, int lmac_id);
int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
struct cgx_lmac_fwdata_s *linkmodes,
int cgx_id, int lmac_id);
u64 cgx_features_get(void *cgxd);
struct mac_ops *get_mac_ops(void *cgxd);

33
drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
View File

@ -95,7 +95,31 @@ enum CGX_MODE_ {
CGX_MODE_100G_C2M,
CGX_MODE_100G_CR4,
CGX_MODE_100G_KR4,
CGX_MODE_MAX /* = 29 */
CGX_MODE_LAUI_2_C2C_BIT,
CGX_MODE_LAUI_2_C2M_BIT,
CGX_MODE_50GBASE_CR2_C_BIT,
CGX_MODE_50GBASE_KR2_C_BIT, /* = 30 */
CGX_MODE_100GAUI_2_C2C_BIT,
CGX_MODE_100GAUI_2_C2M_BIT,
CGX_MODE_100GBASE_CR2_BIT,
CGX_MODE_100GBASE_KR2_BIT,
CGX_MODE_SFI_1G_BIT,
CGX_MODE_25GBASE_CR_C_BIT,
CGX_MODE_25GBASE_KR_C_BIT,
CGX_MODE_SGMII_10M_BIT,
CGX_MODE_SGMII_100M_BIT, /* = 39 */
CGX_MODE_2500_BASEX_BIT = 42, /* Mode group 1 */
CGX_MODE_5000_BASEX_BIT,
CGX_MODE_O_USGMII_BIT,
CGX_MODE_Q_USGMII_BIT,
CGX_MODE_2_5G_USXGMII_BIT,
CGX_MODE_5G_USXGMII_BIT,
CGX_MODE_10G_SXGMII_BIT,
CGX_MODE_10G_DXGMII_BIT,
CGX_MODE_10G_QXGMII_BIT,
CGX_MODE_TP_BIT,
CGX_MODE_FIBER_BIT,
CGX_MODE_MAX /* = 53 */
};
/* REQUEST ID types. Input to firmware */
enum cgx_cmd_id {
@ -258,7 +282,12 @@ struct cgx_lnk_sts {
#define CMDMODECHANGE_SPEED GENMASK_ULL(11, 8)
#define CMDMODECHANGE_DUPLEX GENMASK_ULL(12, 12)
#define CMDMODECHANGE_AN GENMASK_ULL(13, 13)
#define CMDMODECHANGE_PORT GENMASK_ULL(21, 14)
/* this field categorize the mode ID(FLAGS) range to accommodate
* more modes.
* To specify mode ID range of 0 - 41, this field will be 0.
* To specify mode ID range of 42 - 83, this field will be 1.
*/
#define CMDMODECHANGE_MODE_BASEIDX GENMASK_ULL(21, 20)
#define CMDMODECHANGE_FLAGS GENMASK_ULL(63, 22)
/* LINK_BRING_UP command timeout */

9
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
View File

@ -10,6 +10,7 @@
#include <linux/etherdevice.h>
#include <linux/sizes.h>
#include <linux/ethtool.h>
#include "rvu_struct.h"
#include "common.h"
@ -658,7 +659,8 @@ struct cgx_lmac_fwdata_s {
u64 supported_link_modes;
/* only applicable if AN is supported */
u64 advertised_fec;
u64 advertised_link_modes;
u64 advertised_link_modes_own:1; /* CGX_CMD_OWN */
u64 advertised_link_modes:63;
/* Only applicable if SFP/QSFP slot is present */
struct sfp_eeprom_s sfp_eeprom;
struct phy_s phy;
@ -675,12 +677,13 @@ struct cgx_set_link_mode_args {
u32 speed;
u8 duplex;
u8 an;
u8 ports;
u8 mode_baseidx;
u8 multimode;
u64 mode;
__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
};
struct cgx_set_link_mode_req {
#define AUTONEG_UNKNOWN 0xff
struct mbox_msghdr hdr;
struct cgx_set_link_mode_args args;
};

9
drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
View File

@ -1223,6 +1223,7 @@ int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu,
struct cgx_set_link_mode_rsp *rsp)
{
int pf = rvu_get_pf(rvu->pdev, req->hdr.pcifunc);
struct cgx_lmac_fwdata_s *linkmodes;
u8 cgx_idx, lmac;
void *cgxd;
@ -1231,7 +1232,13 @@ int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu,
rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
cgxd = rvu_cgx_pdata(cgx_idx, rvu);
rsp->status = cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac);
if (rvu->hw->lmac_per_cgx == CGX_LMACS_USX)
linkmodes = &rvu->fwdata->cgx_fw_data_usx[cgx_idx][lmac];
else
linkmodes = &rvu->fwdata->cgx_fw_data[cgx_idx][lmac];
rsp->status = cgx_set_link_mode(cgxd, req->args, linkmodes,
cgx_idx, lmac);
return 0;
}

62
drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c
View File

@ -15,6 +15,7 @@
#include "otx2_common.h"
#include "otx2_ptp.h"
#include <cgx_fw_if.h>
#define DRV_NAME "rvu-nicpf"
#define DRV_VF_NAME "rvu-nicvf"
@ -1126,17 +1127,9 @@ static void otx2_get_link_mode_info(u64 link_mode_bmap,
*link_ksettings)
{
__ETHTOOL_DECLARE_LINK_MODE_MASK(otx2_link_modes) = { 0, };
const int otx2_sgmii_features[6] = {
ETHTOOL_LINK_MODE_10baseT_Half_BIT,
ETHTOOL_LINK_MODE_10baseT_Full_BIT,
ETHTOOL_LINK_MODE_100baseT_Half_BIT,
ETHTOOL_LINK_MODE_100baseT_Full_BIT,
ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
};
/* CGX link modes to Ethtool link mode mapping */
const int cgx_link_mode[27] = {
0, /* SGMII Mode */
const int cgx_link_mode[CGX_MODE_MAX] = {
0, /* SGMII 1000baseT */
ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
@ -1166,14 +1159,19 @@ static void otx2_get_link_mode_info(u64 link_mode_bmap,
};
u8 bit;
for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, 27) {
/* SGMII mode is set */
if (bit == 0)
linkmode_set_bit_array(otx2_sgmii_features,
ARRAY_SIZE(otx2_sgmii_features),
otx2_link_modes);
else
for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, ARRAY_SIZE(cgx_link_mode)) {
if (bit == CGX_MODE_SGMII_10M_BIT) {
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, otx2_link_modes);
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, otx2_link_modes);
} else if (bit == CGX_MODE_SGMII_100M_BIT) {
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, otx2_link_modes);
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, otx2_link_modes);
} else if (bit == CGX_MODE_SGMII) {
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, otx2_link_modes);
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, otx2_link_modes);
} else {
linkmode_set_bit(cgx_link_mode[bit], otx2_link_modes);
}
}
if (req_mode == OTX2_MODE_ADVERTISED)
@ -1214,23 +1212,10 @@ static int otx2_get_link_ksettings(struct net_device *netdev,
return 0;
}
static void otx2_get_advertised_mode(const struct ethtool_link_ksettings *cmd,
u64 *mode)
{
u32 bit_pos;
/* Firmware does not support requesting multiple advertised modes
* return first set bit
*/
bit_pos = find_first_bit(cmd->link_modes.advertising,
__ETHTOOL_LINK_MODE_MASK_NBITS);
if (bit_pos != __ETHTOOL_LINK_MODE_MASK_NBITS)
*mode = bit_pos;
}
static int otx2_set_link_ksettings(struct net_device *netdev,
const struct ethtool_link_ksettings *cmd)
{
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
struct otx2_nic *pf = netdev_priv(netdev);
struct ethtool_link_ksettings cur_ks;
struct cgx_set_link_mode_req *req;
@ -1267,7 +1252,20 @@ static int otx2_set_link_ksettings(struct net_device *netdev,
*/
req->args.duplex = cmd->base.duplex ^ 0x1;
req->args.an = cmd->base.autoneg;
otx2_get_advertised_mode(cmd, &req->args.mode);
/* Mask unsupported modes and send message to AF */
linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mask);
linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mask);
linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mask);
linkmode_copy(req->args.advertising,
cmd->link_modes.advertising);
linkmode_andnot(req->args.advertising,
req->args.advertising, mask);
/* inform AF that we need parse this differently */
if (bitmap_weight(req->args.advertising,
__ETHTOOL_LINK_MODE_MASK_NBITS) >= 2)
req->args.multimode = true;
err = otx2_sync_mbox_msg(&pf->mbox);
end: