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drm/amd/display: Disable boot optimization for DCN401
[Why] DCN401 currently has an issue re-enabling when pipe splitting is enabled, while the root cause is being investigated we can make sure everything is being reset as a workaround, by disabling boot optimization. [How] - use enable_accelerated_mode instead of init_pipes to fully reset asic Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -304,7 +304,14 @@ void dcn401_init_hw(struct dc *dc)
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* everything down.
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*/
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if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
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hws->funcs.init_pipes(dc, dc->current_state);
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/* Disable boot optimizations means power down everything including PHY, DIG,
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* and OTG (i.e. the boot is not optimized because we do a full power down).
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*/
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if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)
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dc->hwss.enable_accelerated_mode(dc, dc->current_state);
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else
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hws->funcs.init_pipes(dc, dc->current_state);
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if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
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dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
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!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
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@ -733,6 +733,7 @@ static const struct dc_debug_options debug_defaults_drv = {
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.force_cositing = CHROMA_COSITING_TOPLEFT + 1,
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.disable_idle_power_optimizations = true,
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.edp_oled_no_backlight_enable = true,
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.disable_boot_optimizations = true,
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};
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static struct dce_aux *dcn401_aux_engine_create(
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