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drm/amd/display: Fix dig register undefined

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[Why]
Some of the stream encoder registers have register offset address 0. It
is causing no display in some scenarios due to DIG_FE was not setup
correctly and was not enabled.

[How]
Fix stream encoder register define list.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Duncan Ma 2023-08-01 17:59:05 -04:00 committed by Alex Deucher
parent 1101185bc5
commit f1eb045639
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
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@ -308,7 +308,7 @@ static const struct dcn31_apg_mask apg_mask = {
};
#define stream_enc_regs_init(id)\
SE_DCN32_REG_LIST_RI(id)
SE_DCN35_REG_LIST_RI(id)
static struct dcn10_stream_enc_registers stream_enc_regs[5];