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dt-bindings: display: Document the Xylon LogiCVC display controller
The Xylon LogiCVC is a display controller implemented as programmable logic in Xilinx FPGAs. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210914200539.732093-2-paul.kocialkowski@bootlin.com
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Paul Kocialkowski
Rob Herring
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 Bootlin
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Xylon LogiCVC display controller
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maintainers:
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- Paul Kocialkowski <paul.kocialkowski@bootlin.com>
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description: |
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The Xylon LogiCVC is a display controller that supports multiple layers.
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It is usually implemented as programmable logic and was optimized for use
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with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
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Because the controller is intended for use in a FPGA, most of the
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configuration of the controller takes place at logic configuration bitstream
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synthesis time. As a result, many of the device-tree bindings are meant to
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reflect the synthesis configuration and must not be configured differently.
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Matching synthesis parameters are provided when applicable.
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Layers are declared in the "layers" sub-node and have dedicated configuration.
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In version 3 of the controller, each layer has fixed memory offset and address
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starting from the video memory base address for its framebuffer. In version 4,
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framebuffers are configured with a direct memory address instead.
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properties:
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compatible:
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enum:
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- xylon,logicvc-3.02.a-display
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- xylon,logicvc-4.01.a-display
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 4
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clock-names:
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minItems: 1
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items:
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# vclk is required and must be provided as first item.
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- const: vclk
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# Other clocks are optional and can be provided in any order.
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- enum:
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- vclk2
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- lvdsclk
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- lvdsclkn
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- enum:
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- vclk2
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- lvdsclk
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- lvdsclkn
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- enum:
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- vclk2
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- lvdsclk
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- lvdsclkn
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interrupts:
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maxItems: 1
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memory-region:
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maxItems: 1
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xylon,display-interface:
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enum:
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# Parallel RGB interface (C_DISPLAY_INTERFACE == 0)
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- parallel-rgb
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# ITU-T BR656 interface (C_DISPLAY_INTERFACE == 1)
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- bt656
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# 4-bit LVDS interface (C_DISPLAY_INTERFACE == 2)
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- lvds-4bits
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# 3-bit LVDS interface (C_DISPLAY_INTERFACE == 4)
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- lvds-3bits
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# DVI interface (C_DISPLAY_INTERFACE == 5)
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- dvi
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description: Display output interface (C_DISPLAY_INTERFACE).
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xylon,display-colorspace:
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enum:
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# RGB colorspace (C_DISPLAY_COLOR_SPACE == 0)
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- rgb
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# YUV 4:2:2 colorspace (C_DISPLAY_COLOR_SPACE == 1)
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- yuv422
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# YUV 4:4:4 colorspace (C_DISPLAY_COLOR_SPACE == 2)
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- yuv444
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description: Display output colorspace (C_DISPLAY_COLOR_SPACE).
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xylon,display-depth:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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description: Display output depth (C_PIXEL_DATA_WIDTH).
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xylon,row-stride:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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description: Fixed number of pixels in a framebuffer row (C_ROW_STRIDE).
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xylon,dithering:
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$ref: "/schemas/types.yaml#/definitions/flag"
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description: Dithering module is enabled (C_XCOLOR)
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xylon,background-layer:
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$ref: "/schemas/types.yaml#/definitions/flag"
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description: |
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The last layer is used to display a black background (C_USE_BACKGROUND).
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The layer must still be registered.
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xylon,layers-configurable:
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$ref: "/schemas/types.yaml#/definitions/flag"
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description: |
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Configuration of layers' size, position and offset is enabled
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(C_USE_SIZE_POSITION).
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layers:
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type: object
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^layer@[0-9]+$":
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type: object
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properties:
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reg:
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maxItems: 1
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xylon,layer-depth:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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description: Layer depth (C_LAYER_X_DATA_WIDTH).
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xylon,layer-colorspace:
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enum:
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# RGB colorspace (C_LAYER_X_TYPE == 0)
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- rgb
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# YUV packed colorspace (C_LAYER_X_TYPE == 0)
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- yuv
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description: Layer colorspace (C_LAYER_X_TYPE).
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xylon,layer-alpha-mode:
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enum:
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# Alpha is configured layer-wide (C_LAYER_X_ALPHA_MODE == 0)
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- layer
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# Alpha is configured per-pixel (C_LAYER_X_ALPHA_MODE == 1)
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- pixel
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description: Alpha mode for the layer (C_LAYER_X_ALPHA_MODE).
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xylon,layer-base-offset:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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description: |
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Offset in number of lines (C_LAYER_X_OFFSET) starting from the
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video RAM base (C_VMEM_BASEADDR), only for version 3.
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xylon,layer-buffer-offset:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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description: |
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Offset in number of lines (C_BUFFER_*_OFFSET) starting from the
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layer base offset for the second buffer used in double-buffering.
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xylon,layer-primary:
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$ref: "/schemas/types.yaml#/definitions/flag"
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description: |
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Layer should be registered as a primary plane (exactly one is
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required).
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additionalProperties: false
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required:
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- reg
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- xylon,layer-depth
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- xylon,layer-colorspace
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- xylon,layer-alpha-mode
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required:
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- "#address-cells"
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- "#size-cells"
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- layer@0
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additionalProperties: false
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description: |
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The description of the display controller layers, containing layer
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sub-nodes that each describe a registered layer.
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port:
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$ref: /schemas/graph.yaml#/properties/port
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description: |
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Video output port, typically connected to a panel or bridge.
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additionalProperties: false
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- xylon,display-interface
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- xylon,display-colorspace
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- xylon,display-depth
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- xylon,row-stride
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- layers
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- port
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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logicvc: logicvc@43c00000 {
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compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd";
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reg = <0x43c00000 0x6000>;
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#address-cells = <1>;
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#size-cells = <1>;
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logicvc_display: display@0 {
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compatible = "xylon,logicvc-3.02.a-display";
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reg = <0x0 0x6000>;
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memory-region = <&logicvc_cma>;
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clocks = <&logicvc_vclk 0>, <&logicvc_lvdsclk 0>;
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clock-names = "vclk", "lvdsclk";
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interrupt-parent = <&intc>;
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interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
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xylon,display-interface = "lvds-4bits";
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xylon,display-colorspace = "rgb";
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xylon,display-depth = <16>;
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xylon,row-stride = <1024>;
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xylon,layers-configurable;
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layers {
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#address-cells = <1>;
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#size-cells = <0>;
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layer@0 {
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reg = <0>;
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xylon,layer-depth = <16>;
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xylon,layer-colorspace = "rgb";
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xylon,layer-alpha-mode = "layer";
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xylon,layer-base-offset = <0>;
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xylon,layer-buffer-offset = <480>;
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xylon,layer-primary;
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};
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layer@1 {
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reg = <1>;
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xylon,layer-depth = <16>;
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xylon,layer-colorspace = "rgb";
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xylon,layer-alpha-mode = "layer";
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xylon,layer-base-offset = <2400>;
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xylon,layer-buffer-offset = <480>;
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};
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layer@2 {
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reg = <2>;
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xylon,layer-depth = <16>;
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xylon,layer-colorspace = "rgb";
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xylon,layer-alpha-mode = "layer";
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xylon,layer-base-offset = <960>;
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xylon,layer-buffer-offset = <480>;
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};
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layer@3 {
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reg = <3>;
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xylon,layer-depth = <16>;
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xylon,layer-colorspace = "rgb";
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xylon,layer-alpha-mode = "layer";
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xylon,layer-base-offset = <480>;
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xylon,layer-buffer-offset = <480>;
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};
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layer@4 {
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reg = <4>;
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xylon,layer-depth = <16>;
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xylon,layer-colorspace = "rgb";
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xylon,layer-alpha-mode = "layer";
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xylon,layer-base-offset = <8192>;
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xylon,layer-buffer-offset = <480>;
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};
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};
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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logicvc_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&panel_input>;
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};
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};
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};
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};
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