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mvebu fixes for 6.17 (part 1)

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Fix SATA ports on various boards: Macchiatobin, CN913x-solidrun.
 Fix audio on Armada 370 DB and OpenRD.
 Disable eMMC high-speed modes on the CN9132 CEX-7 module.
 Disable runtime reconfiguration for PCIe lanes on the CN9132 CEX-7 module.
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Merge tag 'mvebu-fixes-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes

mvebu fixes for 6.17 (part 1)

Fix SATA ports on various boards: Macchiatobin, CN913x-solidrun.
Fix audio on Armada 370 DB and OpenRD.
Disable eMMC high-speed modes on the CN9132 CEX-7 module.
Disable runtime reconfiguration for PCIe lanes on the CN9132 CEX-7 module.

* tag 'mvebu-fixes-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
  arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports
  arm64: dts: marvell: cn9132-clearfog: disable eMMC high-speed modes
  arm64: dts: marvell: cn913x-solidrun: fix sata ports status
  ARM: dts: kirkwood: Fix sound DAI cells for OpenRD clients
  ARM64: dts: mcbin: fix SATA ports on Macchiatobin
  ARM: dts: armada-370-db: Fix stereo audio input routing on Armada 370

Link: https://lore.kernel.org/r/87ikhnn1pl.fsf@BLaptop.bootlin.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-09-12 17:55:31 +02:00
commit f1a43af7a9
7 changed files with 36 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/marvell/armada-370-db.dts
View File

@ -119,7 +119,7 @@ sound {
"Out Jack", "HPL",
"Out Jack", "HPR",
"AIN1L", "In Jack",
"AIN1L", "In Jack";
"AIN1R", "In Jack";
status = "okay";
simple-audio-card,dai-link@0 {

2
arch/arm/boot/dts/marvell/kirkwood-openrd-client.dts
View File

@ -38,7 +38,7 @@ sound {
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&audio0 0>;
sound-dai = <&audio0>;
};
simple-audio-card,codec {

2
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
View File

@ -345,11 +345,13 @@ &cp1_sata0 {
/* CPS Lane 1 - U32 */
sata-port@0 {
phys = <&cp1_comphy1 0>;
status = "okay";
};
/* CPS Lane 3 - U31 */
sata-port@1 {
phys = <&cp1_comphy3 1>;
status = "okay";
};
};

7
arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
View File

@ -152,11 +152,12 @@ expander0_pins: cp0-expander0-pins {
/* SRDS #0 - SATA on M.2 connector */
&cp0_sata0 {
phys = <&cp0_comphy0 1>;
status = "okay";
/* only port 1 is available */
/delete-node/ sata-port@0;
sata-port@1 {
phys = <&cp0_comphy0 1>;
status = "okay";
};
};
/* microSD */

6
arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
View File

@ -563,11 +563,13 @@ &cp1_rtc {
/* SRDS #1 - SATA on M.2 (J44) */
&cp1_sata0 {
phys = <&cp1_comphy1 0>;
status = "okay";
/* only port 0 is available */
/delete-node/ sata-port@1;
sata-port@0 {
phys = <&cp1_comphy1 0>;
status = "okay";
};
};
&cp1_syscon0 {

22
arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
View File

@ -413,7 +413,13 @@ fixed-link {
/* SRDS #0,#1,#2,#3 - PCIe */
&cp0_pcie0 {
num-lanes = <4>;
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
/*
* The mvebu-comphy driver does not currently know how to pass correct
* lane-count to ATF while configuring the serdes lanes.
* Rely on bootloader configuration only.
*
* phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
*/
status = "okay";
};
@ -475,7 +481,13 @@ &cp1_eth0 {
/* SRDS #0,#1 - PCIe */
&cp1_pcie0 {
num-lanes = <2>;
phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
/*
* The mvebu-comphy driver does not currently know how to pass correct
* lane-count to ATF while configuring the serdes lanes.
* Rely on bootloader configuration only.
*
* phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
*/
status = "okay";
};
@ -512,10 +524,9 @@ &cp1_sata0 {
status = "okay";
/* only port 1 is available */
/delete-node/ sata-port@0;
sata-port@1 {
phys = <&cp1_comphy3 1>;
status = "okay";
};
};
@ -631,9 +642,8 @@ &cp2_sata0 {
status = "okay";
/* only port 1 is available */
/delete-node/ sata-port@0;
sata-port@1 {
status = "okay";
phys = <&cp2_comphy3 1>;
};
};

8
arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi
View File

@ -137,6 +137,14 @@ &ap_sdhci0 {
pinctrl-0 = <&ap_mmc0_pins>;
pinctrl-names = "default";
vqmmc-supply = <&v_1_8>;
/*
* Not stable in HS modes - phy needs "more calibration", so disable
* UHS (by preventing voltage switch), SDR104, SDR50 and DDR50 modes.
*/
no-1-8-v;
no-sd;
no-sdio;
non-removable;
status = "okay";
};