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iommu/riscv: Advertise Svpbmt support to generic page table

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The RISC-V IOMMU can optionally support Svpbmt page-based memory types
in its page table format. When present,the generic page table code can
use this capability to encode memory attributes (e.g. MMIO vs normal
memory) in PTEs.

Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
Fangyu Yu 2026-04-17 22:07:45 +08:00 committed by Joerg Roedel
parent 5d6919055d
commit f196a86687
2 changed files with 6 additions and 0 deletions
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2
drivers/iommu/riscv/iommu.c
View File

@ -1268,6 +1268,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev)
cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) |
BIT(PT_FEAT_FLUSH_RANGE) |
BIT(PT_FEAT_RISCV_SVNAPOT_64K);
if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT)
cfg.common.features |= BIT(PT_FEAT_RISCV_SVPBMT);
domain->riscvpt.iommu.nid = dev_to_node(iommu->dev);
domain->domain.ops = &riscv_iommu_paging_domain_ops;

4
include/linux/generic_pt/common.h
View File

@ -188,6 +188,10 @@ enum {
* Support the 64k contiguous page size following the Svnapot extension.
*/
PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START,
/*
* Support Svpbmt extension: encode page-based memory type (PBMT) in PTEs.
*/
PT_FEAT_RISCV_SVPBMT,
};