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media: qcom: camss: Add CSID 340 support
Add support for CSID found in QCM2290, it's a simplified gen-2 version. - There is no Test Pattern Generator (moved outside CSID) - There is no subsampling (moved to CAMIF module) Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Loic Poulain
Mauro Carvalho Chehab
parent
acf8d08469
commit
f0fc808a46
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@ -6,6 +6,7 @@ qcom-camss-objs += \
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camss-csid.o \
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camss-csid-4-1.o \
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camss-csid-4-7.o \
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camss-csid-340.o \
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camss-csid-680.o \
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camss-csid-gen2.o \
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camss-csid-780.o \
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189
drivers/media/platform/qcom/camss/camss-csid-340.c
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189
drivers/media/platform/qcom/camss/camss-csid-340.c
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@ -0,0 +1,189 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module 340
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*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include "camss.h"
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#include "camss-csid.h"
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#include "camss-csid-gen2.h"
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#define CSID_RST_STROBES (0x010)
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#define CSID_RST_SW_REGS BIT(0)
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#define CSID_RST_IRQ BIT(1)
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#define CSID_RST_IFE_CLK BIT(2)
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#define CSID_RST_PHY_CLK BIT(3)
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#define CSID_RST_CSID_CLK BIT(4)
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#define CSID_IRQ_STATUS (0x070)
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#define CSID_IRQ_MASK (0x074)
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#define CSID_IRQ_MASK_RST_DONE BIT(0)
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#define CSID_IRQ_CLEAR (0x078)
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#define CSID_IRQ_CMD (0x080)
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#define CSID_IRQ_CMD_CLEAR BIT(0)
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#define CSID_CSI2_RX_CFG0 (0x100)
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#define CSI2_RX_CFG0_NUM_ACTIVE_LANES_MASK GENMASK(1, 0)
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#define CSI2_RX_CFG0_DLX_INPUT_SEL_MASK GENMASK(17, 4)
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#define CSI2_RX_CFG0_PHY_NUM_SEL_MASK GENMASK(21, 20)
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#define CSI2_RX_CFG0_PHY_NUM_SEL_BASE_IDX 1
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#define CSI2_RX_CFG0_PHY_TYPE_SEL BIT(24)
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#define CSID_CSI2_RX_CFG1 (0x104)
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#define CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN BIT(0)
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#define CSI2_RX_CFG1_MISR_EN BIT(6)
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#define CSI2_RX_CFG1_CGC_MODE BIT(7)
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#define CSID_RDI_CFG0(rdi) (0x300 + 0x100 * (rdi))
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#define CSID_RDI_CFG0_BYTE_CNTR_EN BIT(0)
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#define CSID_RDI_CFG0_TIMESTAMP_EN BIT(1)
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#define CSID_RDI_CFG0_DECODE_FORMAT_MASK GENMASK(15, 12)
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#define CSID_RDI_CFG0_DECODE_FORMAT_NOP CSID_RDI_CFG0_DECODE_FORMAT_MASK
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#define CSID_RDI_CFG0_DT_MASK GENMASK(21, 16)
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#define CSID_RDI_CFG0_VC_MASK GENMASK(23, 22)
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#define CSID_RDI_CFG0_DTID_MASK GENMASK(28, 27)
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#define CSID_RDI_CFG0_ENABLE BIT(31)
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#define CSID_RDI_CTRL(rdi) (0x308 + 0x100 * (rdi))
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#define CSID_RDI_CTRL_HALT_AT_FRAME_BOUNDARY 0
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#define CSID_RDI_CTRL_RESUME_AT_FRAME_BOUNDARY 1
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static void __csid_configure_rx(struct csid_device *csid,
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struct csid_phy_config *phy, int vc)
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{
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u32 val;
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val = FIELD_PREP(CSI2_RX_CFG0_NUM_ACTIVE_LANES_MASK, phy->lane_cnt - 1);
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val |= FIELD_PREP(CSI2_RX_CFG0_DLX_INPUT_SEL_MASK, phy->lane_assign);
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val |= FIELD_PREP(CSI2_RX_CFG0_PHY_NUM_SEL_MASK,
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phy->csiphy_id + CSI2_RX_CFG0_PHY_NUM_SEL_BASE_IDX);
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writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
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val = CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;
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writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
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}
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static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
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{
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writel_relaxed(!!enable, csid->base + CSID_RDI_CTRL(rdi));
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}
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static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
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{
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struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
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const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
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csid->res->formats->nformats,
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input_format->code);
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u8 lane_cnt = csid->phy.lane_cnt;
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u8 dt_id;
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u32 val;
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if (!lane_cnt)
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lane_cnt = 4;
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/*
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* DT_ID is a two bit bitfield that is concatenated with
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* the four least significant bits of the five bit VC
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* bitfield to generate an internal CID value.
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*
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* CSID_RDI_CFG0(vc)
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* DT_ID : 28:27
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* VC : 26:22
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* DT : 21:16
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*
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* CID : VC 3:0 << 2 | DT_ID 1:0
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*/
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dt_id = vc & 0x03;
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val = CSID_RDI_CFG0_DECODE_FORMAT_NOP; /* only for RDI path */
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val |= FIELD_PREP(CSID_RDI_CFG0_DT_MASK, format->data_type);
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val |= FIELD_PREP(CSID_RDI_CFG0_VC_MASK, vc);
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val |= FIELD_PREP(CSID_RDI_CFG0_DTID_MASK, dt_id);
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if (enable)
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val |= CSID_RDI_CFG0_ENABLE;
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dev_dbg(csid->camss->dev, "CSID%u: Stream %s (dt:0x%x vc=%u)\n",
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csid->id, enable ? "enable" : "disable", format->data_type, vc);
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writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
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}
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static void csid_configure_stream(struct csid_device *csid, u8 enable)
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{
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int i;
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for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) {
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if (csid->phy.en_vc & BIT(i)) {
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__csid_configure_rdi_stream(csid, enable, i);
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__csid_configure_rx(csid, &csid->phy, i);
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__csid_ctrl_rdi(csid, enable, i);
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}
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}
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}
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static int csid_reset(struct csid_device *csid)
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{
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unsigned long time;
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writel_relaxed(CSID_IRQ_MASK_RST_DONE, csid->base + CSID_IRQ_MASK);
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writel_relaxed(CSID_IRQ_MASK_RST_DONE, csid->base + CSID_IRQ_CLEAR);
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writel_relaxed(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
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reinit_completion(&csid->reset_complete);
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/* Reset with registers preserved */
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writel(CSID_RST_IRQ | CSID_RST_IFE_CLK | CSID_RST_PHY_CLK | CSID_RST_CSID_CLK,
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csid->base + CSID_RST_STROBES);
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time = wait_for_completion_timeout(&csid->reset_complete,
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msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
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if (!time) {
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dev_err(csid->camss->dev, "CSID%u: reset timeout\n", csid->id);
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return -EIO;
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}
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dev_dbg(csid->camss->dev, "CSID%u: reset done\n", csid->id);
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return 0;
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}
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static irqreturn_t csid_isr(int irq, void *dev)
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{
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struct csid_device *csid = dev;
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u32 val;
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val = readl_relaxed(csid->base + CSID_IRQ_STATUS);
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writel_relaxed(val, csid->base + CSID_IRQ_CLEAR);
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writel_relaxed(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
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if (val & CSID_IRQ_MASK_RST_DONE)
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complete(&csid->reset_complete);
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else
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dev_warn_ratelimited(csid->camss->dev, "Spurious CSID interrupt\n");
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return IRQ_HANDLED;
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}
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static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
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{
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return -EOPNOTSUPP; /* Not part of CSID */
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}
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static void csid_subdev_init(struct csid_device *csid) {}
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const struct csid_hw_ops csid_ops_340 = {
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.configure_testgen_pattern = csid_configure_testgen_pattern,
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.configure_stream = csid_configure_stream,
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.hw_version = csid_hw_version,
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.isr = csid_isr,
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.reset = csid_reset,
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.src_pad_code = csid_src_pad_code,
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.subdev_init = csid_subdev_init,
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};
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@ -213,6 +213,7 @@ extern const struct csid_formats csid_formats_gen2;
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extern const struct csid_hw_ops csid_ops_4_1;
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extern const struct csid_hw_ops csid_ops_4_7;
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extern const struct csid_hw_ops csid_ops_340;
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extern const struct csid_hw_ops csid_ops_680;
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extern const struct csid_hw_ops csid_ops_gen2;
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extern const struct csid_hw_ops csid_ops_780;
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