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drm/i915/irq: emphasize display_irqs_enabled is only about VLV/CHV

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Use display_irqs_enabled only on VLV/CHV where it's relevant. Rename to
vlv_display_irqs_enabled, to emphasize it's really only about VLV/CHV.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f60104ea59687cb8c65b18b4f9ddd832a643407d.1732102179.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2024-11-20 13:30:33 +02:00
parent 1fbad9acb1
commit f0fa762400
3 changed files with 21 additions and 20 deletions
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9
drivers/gpu/drm/i915/display/intel_display_core.h
View File

@ -453,7 +453,14 @@ struct intel_display {
} ips;
struct {
bool display_irqs_enabled;
/*
* Most platforms treat the display irq block as an always-on
* power domain. vlv/chv can disable it at runtime and need
* special care to avoid writing any of the display block
* registers outside of the power domain. We defer setting up
* the display irqs in this case to the runtime pm.
*/
bool vlv_display_irqs_enabled;
/* For i915gm/i945gm vblank irq workaround */
u8 vblank_enabled;

26
drivers/gpu/drm/i915/display/intel_display_irq.c
View File

@ -434,7 +434,8 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
spin_lock(&dev_priv->irq_lock);
if (!dev_priv->display.irq.display_irqs_enabled) {
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
!dev_priv->display.irq.vlv_display_irqs_enabled) {
spin_unlock(&dev_priv->irq_lock);
return;
}
@ -1501,7 +1502,7 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv)
void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
if (dev_priv->display.irq.display_irqs_enabled)
if (dev_priv->display.irq.vlv_display_irqs_enabled)
_vlv_display_irq_reset(dev_priv);
}
@ -1524,7 +1525,7 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
u32 enable_mask;
enum pipe pipe;
if (!dev_priv->display.irq.display_irqs_enabled)
if (!dev_priv->display.irq.vlv_display_irqs_enabled)
return;
pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
@ -1699,10 +1700,10 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->irq_lock);
if (dev_priv->display.irq.display_irqs_enabled)
if (dev_priv->display.irq.vlv_display_irqs_enabled)
return;
dev_priv->display.irq.display_irqs_enabled = true;
dev_priv->display.irq.vlv_display_irqs_enabled = true;
if (intel_irqs_enabled(dev_priv)) {
_vlv_display_irq_reset(dev_priv);
@ -1714,10 +1715,10 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->irq_lock);
if (!dev_priv->display.irq.display_irqs_enabled)
if (!dev_priv->display.irq.vlv_display_irqs_enabled)
return;
dev_priv->display.irq.display_irqs_enabled = false;
dev_priv->display.irq.vlv_display_irqs_enabled = false;
if (intel_irqs_enabled(dev_priv))
_vlv_display_irq_reset(dev_priv);
@ -1913,17 +1914,6 @@ void intel_display_irq_init(struct drm_i915_private *i915)
{
i915->drm.vblank_disable_immediate = true;
/*
* Most platforms treat the display irq block as an always-on power
* domain. vlv/chv can disable it at runtime and need special care to
* avoid writing any of the display block registers outside of the power
* domain. We defer setting up the display irqs in this case to the
* runtime pm.
*/
i915->display.irq.display_irqs_enabled = true;
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
i915->display.irq.display_irqs_enabled = false;
intel_hotplug_irq_init(i915);
INIT_WORK(&i915->display.irq.vblank_dc_work,

6
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
View File

@ -1457,7 +1457,11 @@ void intel_hpd_enable_detection(struct intel_encoder *encoder)
void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
if (i915->display.irq.display_irqs_enabled && i915->display.funcs.hotplug)
if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) &&
!i915->display.irq.vlv_display_irqs_enabled)
return;
if (i915->display.funcs.hotplug)
i915->display.funcs.hotplug->hpd_irq_setup(i915);
}