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media: rzg2l-cru: Manually track active slot number

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The CRU cycles over the hardware slots where the destination address for
the next frame has to be programmed.

The RZ/G2L version of the IP has a register that tells which is the
last used slot by the hardware but, unfortunately, such register is not
available on RZ/G3E and RZ/V2H(P).

The driver currently compares the value of the AMnMADRSL/H register
which report "the memory address which the current video data was
written to" and compares it with the address programmed in the slots.

This heuristic requires a bit of book keeping and proper locking. As the
driver handles the FrameEnd interrupt, it's way easier to keep track
of the slot that has been used by ourselves with a driver variable.

Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com>
Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Jacopo Mondi 2026-02-11 09:55:00 +01:00 committed by Hans Verkuil
parent ffd977914e
commit f067b1c9c2
2 changed files with 7 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h
View File

@ -119,9 +119,10 @@ struct rzg2l_cru_info {
* @mdev_lock: protects the count, notifier and csi members
* @pad: media pad for the video device entity
*
* @hw_lock: protects the slot counter, hardware programming of
* slot addresses and the @buf_addr[] list
* @hw_lock: protects the @active_slot counter, hardware programming
* of slot addresses and the @buf_addr[] list
* @buf_addr: Memory addresses where current video data is written
* @active_slot: The slot in use
*
* @lock: protects @queue
* @queue: vb2 buffers queue
@ -162,6 +163,7 @@ struct rzg2l_cru_dev {
spinlock_t hw_lock;
dma_addr_t buf_addr[RZG2L_CRU_HW_BUFFER_DEFAULT];
unsigned int active_slot;
struct mutex lock;
struct vb2_queue queue;

31
drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c
View File

@ -634,31 +634,6 @@ irqreturn_t rzg2l_cru_irq(int irq, void *data)
return IRQ_RETVAL(handled);
}
static int rzg3e_cru_get_current_slot(struct rzg2l_cru_dev *cru)
{
u64 amnmadrs;
int slot;
/*
* When AMnMADRSL is read, AMnMADRSH of the higher-order
* address also latches the address.
*
* AMnMADRSH must be read after AMnMADRSL has been read.
*/
amnmadrs = rzg2l_cru_read(cru, AMnMADRSL);
amnmadrs |= (u64)rzg2l_cru_read(cru, AMnMADRSH) << 32;
/* Ensure amnmadrs is within this buffer range */
for (slot = 0; slot < cru->num_buf; slot++) {
if (amnmadrs >= cru->buf_addr[slot] &&
amnmadrs < cru->buf_addr[slot] + cru->format.sizeimage)
return slot;
}
dev_err(cru->dev, "Invalid MB address 0x%llx (out of range)\n", amnmadrs);
return -EINVAL;
}
irqreturn_t rzg3e_cru_irq(int irq, void *data)
{
struct rzg2l_cru_dev *cru = data;
@ -690,9 +665,8 @@ irqreturn_t rzg3e_cru_irq(int irq, void *data)
return IRQ_HANDLED;
}
slot = rzg3e_cru_get_current_slot(cru);
if (slot < 0)
return IRQ_HANDLED;
slot = cru->active_slot;
cru->active_slot = (cru->active_slot + 1) % cru->num_buf;
dev_dbg(cru->dev, "Current written slot: %d\n", slot);
cru->buf_addr[slot] = 0;
@ -769,6 +743,7 @@ static int rzg2l_cru_start_streaming_vq(struct vb2_queue *vq, unsigned int count
goto assert_presetn;
}
cru->active_slot = 0;
cru->sequence = 0;
ret = rzg2l_cru_set_stream(cru, 1);