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arm64: dts: lg: Add missing PL011 "uartclk"

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The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
LG131x SoCs are missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Link: https://lore.kernel.org/r/20250609-dt-lg-fixes-v1-2-e210e797c2d7@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Rob Herring (Arm) 2025-06-09 16:54:57 -05:00 committed by Arnd Bergmann
parent caec315724
commit f060fee24a
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1 changed files with 6 additions and 6 deletions
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12
arch/arm64/boot/dts/lg/lg131x.dtsi
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@ -128,24 +128,24 @@ uart0: serial@fe000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfe000000 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
clocks = <&clk_bus>, <&clk_bus>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart1: serial@fe100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfe100000 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
clocks = <&clk_bus>, <&clk_bus>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: serial@fe200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfe200000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
clocks = <&clk_bus>, <&clk_bus>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
spi0: spi@fe800000 {