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drm/amd/display: Update test link rate DPCD bit field to match spec
[Why] An SCR was made to the DP2.0 spec that updated the bit field definition for UHBR13.5 in the test link rate DPCD register. [How] Add new translation to match the SCR update. Keep old translation for backwards compatibility. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -142,7 +142,8 @@ enum dp_test_link_rate {
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DP_TEST_LINK_RATE_HBR3 = 0x1E,
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DP_TEST_LINK_RATE_UHBR10 = 0x01,
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DP_TEST_LINK_RATE_UHBR20 = 0x02,
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DP_TEST_LINK_RATE_UHBR13_5 = 0x03,
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DP_TEST_LINK_RATE_UHBR13_5_LEGACY = 0x03, /* For backward compatibility*/
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DP_TEST_LINK_RATE_UHBR13_5 = 0x04,
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};
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struct dc_link_settings {
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@ -53,6 +53,7 @@ static enum dc_link_rate get_link_rate_from_test_link_rate(uint8_t test_rate)
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return LINK_RATE_UHBR10;
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case DP_TEST_LINK_RATE_UHBR20:
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return LINK_RATE_UHBR20;
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case DP_TEST_LINK_RATE_UHBR13_5_LEGACY:
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case DP_TEST_LINK_RATE_UHBR13_5:
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return LINK_RATE_UHBR13_5;
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default:
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@ -119,6 +120,11 @@ static void dp_test_send_link_training(struct dc_link *link)
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1);
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link_settings.link_rate = get_link_rate_from_test_link_rate(test_rate);
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if (link_settings.link_rate == LINK_RATE_UNKNOWN) {
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DC_LOG_ERROR("%s: Invalid test link rate.", __func__);
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ASSERT(0);
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}
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/* Set preferred link settings */
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link->verified_link_cap.lane_count = link_settings.lane_count;
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link->verified_link_cap.link_rate = link_settings.link_rate;
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@ -457,7 +463,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
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controller_color_space = pipe_ctx->stream_res.test_pattern_params.color_space;
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if (controller_color_space == CONTROLLER_DP_COLOR_SPACE_UDEFINED) {
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DC_LOG_WARNING("%s: Color space must be defined for test pattern", __func__);
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DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
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ASSERT(0);
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}
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