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arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
Add initial devicetree support for Samsung smdk board using Exynos8855 SoC. This SoC has Octa-core CPU with tri cluster architecture, a custom GPU and a NPU supporting up to 14.7 TOPS apart from other supporting peripheral and IPs. Commercially this SoC is also known as Exynos1580 [1] [1] https://semiconductor.samsung.com/processor/mobile-processor/exynos-1580/ Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://semiconductor.samsung.com/processor/mobile-processor/exynos-1580/ Link: https://patch.msgid.link/20260627171228.2687857-6-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Alim Akhtar
Krzysztof Kozlowski
parent
4b4a2ce19a
commit
f03058d376
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@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
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exynos7870-on7xelte.dtb \
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exynos7885-jackpotlte.dtb \
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exynos850-e850-96.dtb \
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exynos8855-smdk.dtb \
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exynos8895-dreamlte.dtb \
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exynos9810-starlte.dtb \
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exynos990-c1s.dtb \
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574
arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
Normal file
574
arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
Normal file
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@ -0,0 +1,574 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung's S5E8855 SoC pin-mux and pin-config device tree source
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*
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* Copyright (c) 2023 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung's S5E8855 SoC pin-mux and pin-config options are listed as device
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* tree nodes are listed in this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "exynos-pinctrl.h"
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&pinctrl_alive {
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gpa0: gpa0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpa1: gpa1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpq0: gpq0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpq1: gpq1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpc0: gpc0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc1: gpc1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc2: gpc2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc3: gpc3-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc4: gpc4-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc5: gpc5-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc6: gpc6-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc7: gpc7-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc8: gpc8-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc9: gpc9-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc10: gpc10-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc11: gpc11-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc12: gpc12-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc13: gpc13-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpc14: gpc14-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpj0: gpj0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpj1: gpj1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpj2: gpj2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&pinctrl_cmgp {
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gpm0: gpm0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm1: gpm1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm2: gpm2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm3: gpm3-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm4: gpm4-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm5: gpm5-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm6: gpm6-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm7: gpm7-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm8: gpm8-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm9: gpm9-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm10: gpm10-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm11: gpm11-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm12: gpm12-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm13: gpm13-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm14: gpm14-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm15: gpm15-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm16: gpm16-gpio-bank {
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||||
gpio-controller;
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||||
#gpio-cells = <2>;
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||||
|
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interrupt-controller;
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#interrupt-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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||||
};
|
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gpm17: gpm17-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
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|
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interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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};
|
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gpm18: gpm18-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
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|
||||
gpm19: gpm19-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
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interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
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|
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gpm20: gpm20-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm21: gpm21-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_hsi_ufs {
|
||||
gpf3: gpf3-gpio-bank{
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
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&pinctrl_peric {
|
||||
gpp0: gpp0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpp1: gpp1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpp2: gpp2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg0: gpg0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg1: gpg1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb0: gpb0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb1: gpb1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_pericmmc {
|
||||
gpf2: gpf2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_usi {
|
||||
gpp3: gpp3-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpp4: gpp4-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg2: gpg2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg3: gpg3-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
31
arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
Normal file
31
arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Samsung Exynos8855 SMDK board device tree source
|
||||
*
|
||||
* Copyright (C) 2023 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Device tree source file for Samsung SMDK board which is based on
|
||||
* Exynos8855 SoC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "exynos8855.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Samsung Exynos8855 SMDK board";
|
||||
compatible = "samsung,exynos8855-smdk","samsung,exynos8855";
|
||||
|
||||
chosen {
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x80000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&oscclk {
|
||||
clock-frequency = <76800000>;
|
||||
};
|
||||
204
arch/arm64/boot/dts/exynos/exynos8855.dtsi
Normal file
204
arch/arm64/boot/dts/exynos/exynos8855.dtsi
Normal file
|
|
@ -0,0 +1,204 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Samsung Exynos8855 SoC device tree source
|
||||
*
|
||||
* Copyright (C) 2023 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Samsung Exynos8855 SoC device nodes are listed in this file.
|
||||
* Exynos8855 based board files can include this file and provide
|
||||
* values for board specific bindings.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "samsung,exynos8855";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
pinctrl0 = &pinctrl_alive;
|
||||
pinctrl1 = &pinctrl_cmgp;
|
||||
pinctrl2 = &pinctrl_hsi_ufs;
|
||||
pinctrl3 = &pinctrl_peric;
|
||||
pinctrl4 = &pinctrl_pericmmc;
|
||||
pinctrl5 = &pinctrl_usi;
|
||||
};
|
||||
|
||||
oscclk: clock-oscclk {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "oscclk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster2 {
|
||||
core0 {
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a520";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a520";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a520";
|
||||
reg = <0x200>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a520";
|
||||
reg = <0x300>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a720";
|
||||
reg = <0x400>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a720";
|
||||
reg = <0x500>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a720";
|
||||
reg = <0x600>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a720";
|
||||
reg = <0x700>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x0 0x20000000>;
|
||||
|
||||
gic: interrupt-controller@10200000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x10200000 0x10000>,
|
||||
<0x10240000 0x140000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_alive: pinctrl@11850000 {
|
||||
compatible = "samsung,exynos8855-pinctrl";
|
||||
reg = <0x11850000 0x1000>;
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos8855-wakeup-eint",
|
||||
"samsung,exynos7-wakeup-eint";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_cmgp: pinctrl@12030000 {
|
||||
compatible = "samsung,exynos8855-pinctrl";
|
||||
reg = <0x12030000 0x1000>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_usi: pinctrl@15030000 {
|
||||
compatible = "samsung,exynos8855-pinctrl";
|
||||
reg = <0x15030000 0x1000>;
|
||||
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_peric: pinctrl@15440000 {
|
||||
compatible = "samsung,exynos8855-pinctrl";
|
||||
reg = <0x15440000 0x1000>;
|
||||
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_pericmmc: pinctrl@154f0000 {
|
||||
compatible = "samsung,exynos8855-pinctrl";
|
||||
reg = <0x154f0000 0x1000>;
|
||||
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_hsi_ufs: pinctrl@17040000 {
|
||||
compatible = "samsung,exynos8855-pinctrl";
|
||||
reg = <0x17040000 0x1000>;
|
||||
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
/* Hypervisor Virtual Timer interrupt is not wired to GIC */
|
||||
interrupts =
|
||||
<GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "exynos8855-pinctrl.dtsi"
|
||||
Loading…
Reference in New Issue
Block a user