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HID: intel-thc-hid: intel-thc: Add THC SPI config interfaces
Add SPI bus related APIs to configure SPI operation parameters, such as port type, bus frequency, bus IO mode, read/write OPcode, and slave register addresses. Co-developed-by: Even Xu <even.xu@intel.com> Signed-off-by: Even Xu <even.xu@intel.com> Signed-off-by: Xinpeng Sun <xinpeng.sun@intel.com> Tested-by: Rui Zhang <rui1.zhang@intel.com> Tested-by: Mark Pearson <mpearson-lenovo@squebb.ca> Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Mark Pearson <mpearson-lenovo@squebb.ca> Tested-by: Aaron Ma <aaron.ma@canonical.com> Signed-off-by: Jiri Kosina <jkosina@suse.com>
This commit is contained in:
Xinpeng Sun
Jiri Kosina
parent
4e682ea6d6
commit
f02bcabad0
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@ -1061,6 +1061,235 @@ int thc_interrupt_handler(struct thc_device *dev)
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}
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EXPORT_SYMBOL_NS_GPL(thc_interrupt_handler, "INTEL_THC");
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/**
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* thc_port_select - Set THC port type
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*
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* @dev: The pointer of THC private device context
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* @port_type: THC port type to use for current device
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*
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* Return: 0 on success, other error codes on failed.
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*/
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int thc_port_select(struct thc_device *dev, enum thc_port_type port_type)
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{
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u32 ctrl, mask;
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if (port_type == THC_PORT_TYPE_SPI) {
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dev_dbg(dev->dev, "Set THC port type to SPI\n");
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dev->port_type = THC_PORT_TYPE_SPI;
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/* Enable delay of CS assertion and set to default value */
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ctrl = THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_EN |
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FIELD_PREP(THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_VAL,
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THC_CSA_CK_DELAY_VAL_DEFAULT);
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mask = THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_EN |
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THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_VAL;
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regmap_write_bits(dev->thc_regmap, THC_M_PRT_SPI_DUTYC_CFG_OFFSET,
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mask, ctrl);
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} else if (port_type == THC_PORT_TYPE_I2C) {
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dev_dbg(dev->dev, "Set THC port type to I2C\n");
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dev->port_type = THC_PORT_TYPE_I2C;
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/* Set THC transition arbitration policy to frame boundary for I2C */
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ctrl = FIELD_PREP(THC_M_PRT_CONTROL_THC_ARB_POLICY,
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THC_ARB_POLICY_FRAME_BOUNDARY);
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mask = THC_M_PRT_CONTROL_THC_ARB_POLICY;
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regmap_write_bits(dev->thc_regmap, THC_M_PRT_CONTROL_OFFSET, mask, ctrl);
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} else {
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dev_err(dev->dev, "unsupported THC port type: %d\n", port_type);
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return -EINVAL;
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}
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ctrl = FIELD_PREP(THC_M_PRT_CONTROL_PORT_TYPE, port_type);
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mask = THC_M_PRT_CONTROL_PORT_TYPE;
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regmap_write_bits(dev->thc_regmap, THC_M_PRT_CONTROL_OFFSET, mask, ctrl);
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(thc_port_select, "INTEL_THC");
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#define THC_SPI_FREQUENCY_7M 7812500
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#define THC_SPI_FREQUENCY_15M 15625000
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#define THC_SPI_FREQUENCY_17M 17857100
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#define THC_SPI_FREQUENCY_20M 20833000
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#define THC_SPI_FREQUENCY_25M 25000000
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#define THC_SPI_FREQUENCY_31M 31250000
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#define THC_SPI_FREQUENCY_41M 41666700
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#define THC_SPI_LOW_FREQUENCY THC_SPI_FREQUENCY_17M
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static u8 thc_get_spi_freq_div_val(struct thc_device *dev, u32 spi_freq_val)
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{
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int frequency[] = {
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THC_SPI_FREQUENCY_7M,
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THC_SPI_FREQUENCY_15M,
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THC_SPI_FREQUENCY_17M,
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THC_SPI_FREQUENCY_20M,
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THC_SPI_FREQUENCY_25M,
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THC_SPI_FREQUENCY_31M,
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THC_SPI_FREQUENCY_41M,
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};
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u8 frequency_div[] = {
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THC_SPI_FRQ_DIV_2,
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THC_SPI_FRQ_DIV_1,
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THC_SPI_FRQ_DIV_7,
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THC_SPI_FRQ_DIV_6,
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THC_SPI_FRQ_DIV_5,
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THC_SPI_FRQ_DIV_4,
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THC_SPI_FRQ_DIV_3,
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};
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int size = ARRAY_SIZE(frequency);
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u32 closest_freq;
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u8 freq_div;
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int i;
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for (i = size - 1; i >= 0; i--)
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if ((int)spi_freq_val - frequency[i] >= 0)
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break;
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if (i < 0) {
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dev_err_once(dev->dev, "Not supported SPI frequency %d\n", spi_freq_val);
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return THC_SPI_FRQ_RESERVED;
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}
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closest_freq = frequency[i];
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freq_div = frequency_div[i];
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dev_dbg(dev->dev,
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"Setting SPI frequency: spi_freq_val = %u, Closest freq = %u\n",
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spi_freq_val, closest_freq);
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return freq_div;
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}
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/**
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* thc_spi_read_config - Configure SPI bus read attributes
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*
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* @dev: The pointer of THC private device context
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* @spi_freq_val: SPI read frequecy value
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* @io_mode: SPI read IO mode
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* @opcode: Read opcode
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* @spi_rd_mps: SPI read max packet size
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*
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* Return: 0 on success, other error codes on failed.
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*/
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int thc_spi_read_config(struct thc_device *dev, u32 spi_freq_val,
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u32 io_mode, u32 opcode, u32 spi_rd_mps)
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{
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bool is_low_freq = false;
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u32 cfg, mask;
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u8 freq_div;
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freq_div = thc_get_spi_freq_div_val(dev, spi_freq_val);
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if (freq_div == THC_SPI_FRQ_RESERVED)
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return -EINVAL;
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if (spi_freq_val < THC_SPI_LOW_FREQUENCY)
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is_low_freq = true;
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cfg = FIELD_PREP(THC_M_PRT_SPI_CFG_SPI_TCRF, freq_div) |
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FIELD_PREP(THC_M_PRT_SPI_CFG_SPI_TRMODE, io_mode) |
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(is_low_freq ? THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN : 0) |
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FIELD_PREP(THC_M_PRT_SPI_CFG_SPI_RD_MPS, spi_rd_mps);
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mask = THC_M_PRT_SPI_CFG_SPI_TCRF |
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THC_M_PRT_SPI_CFG_SPI_TRMODE |
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THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN |
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THC_M_PRT_SPI_CFG_SPI_RD_MPS;
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regmap_write_bits(dev->thc_regmap,
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THC_M_PRT_SPI_CFG_OFFSET, mask, cfg);
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if (io_mode == THC_QUAD_IO)
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opcode = FIELD_PREP(THC_M_PRT_SPI_ICRRD_OPCODE_SPI_QIO, opcode);
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else if (io_mode == THC_DUAL_IO)
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opcode = FIELD_PREP(THC_M_PRT_SPI_ICRRD_OPCODE_SPI_DIO, opcode);
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else
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opcode = FIELD_PREP(THC_M_PRT_SPI_ICRRD_OPCODE_SPI_SIO, opcode);
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regmap_write(dev->thc_regmap, THC_M_PRT_SPI_ICRRD_OPCODE_OFFSET, opcode);
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regmap_write(dev->thc_regmap, THC_M_PRT_SPI_DMARD_OPCODE_OFFSET, opcode);
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(thc_spi_read_config, "INTEL_THC");
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/**
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* thc_spi_write_config - Configure SPI bus write attributes
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*
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* @dev: The pointer of THC private device context
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* @spi_freq_val: SPI write frequecy value
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* @io_mode: SPI write IO mode
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* @opcode: Write opcode
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* @spi_wr_mps: SPI write max packet size
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* @perf_limit: Performance limitation in unit of 10us
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*
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* Return: 0 on success, other error codes on failed.
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*/
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int thc_spi_write_config(struct thc_device *dev, u32 spi_freq_val,
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u32 io_mode, u32 opcode, u32 spi_wr_mps,
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u32 perf_limit)
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{
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bool is_low_freq = false;
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u32 cfg, mask;
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u8 freq_div;
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freq_div = thc_get_spi_freq_div_val(dev, spi_freq_val);
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if (freq_div == THC_SPI_FRQ_RESERVED)
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return -EINVAL;
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if (spi_freq_val < THC_SPI_LOW_FREQUENCY)
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is_low_freq = true;
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cfg = FIELD_PREP(THC_M_PRT_SPI_CFG_SPI_TCWF, freq_div) |
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FIELD_PREP(THC_M_PRT_SPI_CFG_SPI_TWMODE, io_mode) |
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(is_low_freq ? THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN : 0) |
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FIELD_PREP(THC_M_PRT_SPI_CFG_SPI_WR_MPS, spi_wr_mps);
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mask = THC_M_PRT_SPI_CFG_SPI_TCWF |
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THC_M_PRT_SPI_CFG_SPI_TWMODE |
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THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN |
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THC_M_PRT_SPI_CFG_SPI_WR_MPS;
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regmap_write_bits(dev->thc_regmap,
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THC_M_PRT_SPI_CFG_OFFSET, mask, cfg);
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if (io_mode == THC_QUAD_IO)
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opcode = FIELD_PREP(THC_M_PRT_SPI_ICRRD_OPCODE_SPI_QIO, opcode);
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else if (io_mode == THC_DUAL_IO)
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opcode = FIELD_PREP(THC_M_PRT_SPI_ICRRD_OPCODE_SPI_DIO, opcode);
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else
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opcode = FIELD_PREP(THC_M_PRT_SPI_ICRRD_OPCODE_SPI_SIO, opcode);
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regmap_write(dev->thc_regmap, THC_M_PRT_SPI_WR_OPCODE_OFFSET, opcode);
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dev->perf_limit = perf_limit;
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(thc_spi_write_config, "INTEL_THC");
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/**
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* thc_spi_input_output_address_config - Configure SPI input and output addresses
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*
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* @dev: the pointer of THC private device context
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* @input_hdr_addr: input report header address
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* @input_bdy_addr: input report body address
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* @output_addr: output report address
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*/
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void thc_spi_input_output_address_config(struct thc_device *dev, u32 input_hdr_addr,
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u32 input_bdy_addr, u32 output_addr)
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{
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regmap_write(dev->thc_regmap,
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THC_M_PRT_DEV_INT_CAUSE_ADDR_OFFSET, input_hdr_addr);
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regmap_write(dev->thc_regmap,
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THC_M_PRT_RD_BULK_ADDR_1_OFFSET, input_bdy_addr);
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regmap_write(dev->thc_regmap,
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THC_M_PRT_RD_BULK_ADDR_2_OFFSET, input_bdy_addr);
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regmap_write(dev->thc_regmap,
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THC_M_PRT_WR_BULK_ADDR_OFFSET, output_addr);
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}
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EXPORT_SYMBOL_NS_GPL(thc_spi_input_output_address_config, "INTEL_THC");
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MODULE_AUTHOR("Xinpeng Sun <xinpeng.sun@intel.com>");
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MODULE_AUTHOR("Even Xu <even.xu@intel.com>");
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@ -98,5 +98,12 @@ void thc_change_ltr_mode(struct thc_device *dev, u32 ltr_mode);
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void thc_ltr_unconfig(struct thc_device *dev);
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u32 thc_int_cause_read(struct thc_device *dev);
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int thc_interrupt_handler(struct thc_device *dev);
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int thc_port_select(struct thc_device *dev, enum thc_port_type port_type);
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int thc_spi_read_config(struct thc_device *dev, u32 spi_freq_val,
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u32 io_mode, u32 opcode, u32 spi_rd_mps);
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int thc_spi_write_config(struct thc_device *dev, u32 spi_freq_val,
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u32 io_mode, u32 opcode, u32 spi_wr_mps, u32 perf_limit);
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void thc_spi_input_output_address_config(struct thc_device *dev, u32 input_hdr_addr,
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u32 input_bdy_addr, u32 output_addr);
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#endif /* _INTEL_THC_DEV_H_ */
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@ -636,6 +636,20 @@
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#define THC_M_PRT_SW_DMA_PRD_TABLE_LEN_THC_M_PRT_SW_DMA_PRD_TABLE_LEN GENMASK(23, 0)
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#define THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_VAL GENMASK(3, 0)
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#define THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_EN BIT(25)
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/* CS Assertion delay default value */
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#define THC_CSA_CK_DELAY_VAL_DEFAULT 4
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/* ARB policy definition */
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/* Arbiter switches on packet boundary */
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#define THC_ARB_POLICY_PACKET_BOUNDARY 0
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/* Arbiter switches on Micro Frame boundary */
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#define THC_ARB_POLICY_UFRAME_BOUNDARY 1
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/* Arbiter switches on Frame boundary */
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#define THC_ARB_POLICY_FRAME_BOUNDARY 2
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#define THC_REGMAP_POLLING_INTERVAL_US 10 /* 10us */
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#define THC_PIO_DONE_TIMEOUT_US USEC_PER_SEC /* 1s */
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@ -697,4 +711,42 @@ enum thc_pio_opcode {
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THC_PIO_OP_I2C_TIC_WRITE_AND_READ = 0x1C,
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};
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/**
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* THC SPI IO mode
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* @THC_SINGLE_IO: single IO mode, 1(opcode) - 1(address) - 1(data)
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* @THC_DUAL_IO: dual IO mode, 1(opcode) - 2(address) - 2(data)
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* @THC_QUAD_IO: quad IO mode, 1(opcode) - 4(address) - 4(data)
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* @THC_QUAD_PARALLEL_IO: parallel quad IO mode, 4(opcode) - 4(address) - 4(data)
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*/
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enum thc_spi_iomode {
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THC_SINGLE_IO = 0,
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THC_DUAL_IO = 1,
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THC_QUAD_IO = 2,
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THC_QUAD_PARALLEL_IO = 3,
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};
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/**
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* THC SPI frequency divider
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*
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* This DIV final value is determined by THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN bit.
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* If THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN isn't be set, THC takes the DIV value directly;
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* If THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN is set, THC takes the DIV value multiply by 8.
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*
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* For example, if THC input clock is 125MHz:
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* When THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN isn't set, THC_SPI_FRQ_DIV_3 means DIV is 3,
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* THC final clock is 125 / 3 = 41.667MHz;
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* When THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN is set, THC_SPI_FRQ_DIV_3 means DIV is 3 * 8,
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* THC final clock is 125 / (3 * 8) = 5.208MHz;
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*/
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enum thc_spi_frq_div {
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THC_SPI_FRQ_RESERVED = 0,
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THC_SPI_FRQ_DIV_1 = 1,
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THC_SPI_FRQ_DIV_2 = 2,
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THC_SPI_FRQ_DIV_3 = 3,
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THC_SPI_FRQ_DIV_4 = 4,
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THC_SPI_FRQ_DIV_5 = 5,
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THC_SPI_FRQ_DIV_6 = 6,
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THC_SPI_FRQ_DIV_7 = 7,
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};
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#endif /* _INTEL_THC_HW_H_ */
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