From 74178bb23c6bdca547c8c6bad89f3338f1af89be Mon Sep 17 00:00:00 2001 From: Jun Guo Date: Fri, 19 Sep 2025 09:31:18 +0800 Subject: [PATCH 1/5] arm64: dts: cix: add DT nodes for SPI Add the device tree node for the spi controller of the CIX SKY1 SoC. Signed-off-by: Jun Guo Link: https://lore.kernel.org/r/20250919013118.853078-1-jun.guo@cixtech.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 2fb2c99c0796..ea324336bf34 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -264,6 +264,26 @@ i2c7: i2c@4080000 { status = "disabled"; }; + spi0: spi@4090000 { + compatible = "cdns,spi-r1p6"; + reg = <0x0 0x04090000 0x0 0x10000>; + clocks = <&scmi_clk CLK_TREE_FCH_SPI0_APB>, + <&scmi_clk CLK_TREE_FCH_SPI0_APB>; + clock-names = "ref_clk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + spi1: spi@40a0000 { + compatible = "cdns,spi-r1p6"; + reg = <0x0 0x040a0000 0x0 0x10000>; + clocks = <&scmi_clk CLK_TREE_FCH_SPI1_APB>, + <&scmi_clk CLK_TREE_FCH_SPI1_APB>; + clock-names = "ref_clk", "pclk"; + interrupts = ; + status = "disabled"; + }; + uart0: serial@40b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x040b0000 0x0 0x1000>; From 1f0de24c547d19adbdba338072fe19a01e87b9b1 Mon Sep 17 00:00:00 2001 From: Gary Yang Date: Tue, 21 Oct 2025 15:04:10 +0800 Subject: [PATCH 2/5] arm64: dts: cix: Add pinctrl nodes for sky1 Add the pin-controller nodes for Sky1 platform. Signed-off-by: Gary Yang Link: https://lore.kernel.org/r/20251021070410.3585997-4-gary.yang@cixtech.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 32 ++ arch/arm64/boot/dts/cix/sky1-pinfunc.h | 401 ++++++++++++++++++++++ arch/arm64/boot/dts/cix/sky1.dtsi | 10 + 3 files changed, 443 insertions(+) create mode 100644 arch/arm64/boot/dts/cix/sky1-pinfunc.h diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts index d74964d53c3b..cdaca197edda 100644 --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -7,6 +7,8 @@ /dts-v1/; #include "sky1.dtsi" +#include "sky1-pinfunc.h" + / { model = "Radxa Orion O6"; compatible = "radxa,orion-o6", "cix,sky1"; @@ -34,6 +36,36 @@ linux,cma { }; +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hog-cfg { + pins { + pinmux = , + , + , + ; + bias-pull-down; + drive-strength = <8>; + }; + }; +}; + +&iomuxc_s5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_s5>; + + pinctrl_hog_s5: hog-s5-cfg { + pins { + pinmux = ; + bias-pull-up; + drive-strength = <8>; + + }; + }; +}; + &uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/cix/sky1-pinfunc.h b/arch/arm64/boot/dts/cix/sky1-pinfunc.h new file mode 100644 index 000000000000..ebe9f6fef403 --- /dev/null +++ b/arch/arm64/boot/dts/cix/sky1-pinfunc.h @@ -0,0 +1,401 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2024-2025 Cix Technology Group Co., Ltd. + */ + +#ifndef __CIX_SKY1_H +#define __CIX_SKY1_H + +/* s5 pads */ +#define CIX_PAD_GPIO001_FUNC_GPIO001 (0 << 8 | 0x0) +#define CIX_PAD_GPIO002_FUNC_GPIO002 (1 << 8 | 0x0) +#define CIX_PAD_GPIO003_FUNC_GPIO003 (2 << 8 | 0x0) +#define CIX_PAD_GPIO004_FUNC_GPIO004 (3 << 8 | 0x0) +#define CIX_PAD_GPIO005_FUNC_GPIO005 (4 << 8 | 0x0) +#define CIX_PAD_GPIO006_FUNC_GPIO006 (5 << 8 | 0x0) +#define CIX_PAD_GPIO007_FUNC_GPIO007 (6 << 8 | 0x0) +#define CIX_PAD_GPIO008_FUNC_GPIO008 (7 << 8 | 0x0) +#define CIX_PAD_GPIO009_FUNC_GPIO009 (8 << 8 | 0x0) +#define CIX_PAD_GPIO010_FUNC_GPIO010 (9 << 8 | 0x0) +#define CIX_PAD_GPIO011_FUNC_GPIO011 (10 << 8 | 0x0) +#define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0) +#define CIX_PAD_GPIO013_FUNC_GPIO013 (12 << 8 | 0x0) +#define CIX_PAD_GPIO014_FUNC_GPIO014 (13 << 8 | 0x0) +#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I2C0_SCL (28 << 8 | 0x0) +#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I3C0_SCL (28 << 8 | 0x1) +#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I2C0_SDA (29 << 8 | 0x0) +#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I3C0_SDA (29 << 8 | 0x1) +#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I2C1_SCL (30 << 8 | 0x0) +#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I3C1_SCL (30 << 8 | 0x1) +#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_SPI_CS0 (30 << 8 | 0x2) +#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I2C1_SDA (31 << 8 | 0x0) +#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I3C1_SDA (31 << 8 | 0x1) +#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_SPI_CS1 (31 << 8 | 0x2) +#define CIX_PAD_SFI_GPIO0_FUNC_GPIO015 (32 << 8 | 0x0) +#define CIX_PAD_SFI_GPIO0_FUNC_SFI_SPI_SCK (32 << 8 | 0x1) +#define CIX_PAD_SFI_GPIO0_FUNC_SFI_GPIO0 (32 << 8 | 0x2) +#define CIX_PAD_SFI_GPIO1_FUNC_GPIO016 (33 << 8 | 0x0) +#define CIX_PAD_SFI_GPIO1_FUNC_SFI_SPI_MOSI (33 << 8 | 0x1) +#define CIX_PAD_SFI_GPIO1_FUNC_SFI_GPIO1 (33 << 8 | 0x2) +#define CIX_PAD_SFI_GPIO2_FUNC_GPIO017 (34 << 8 | 0x0) +#define CIX_PAD_SFI_GPIO2_FUNC_SFI_SPI_MISO (34 << 8 | 0x1) +#define CIX_PAD_SFI_GPIO2_FUNC_SFI_GPIO2 (34 << 8 | 0x2) +#define CIX_PAD_GPIO018_FUNC_SFI_GPIO3 (35 << 8 | 0x0) +#define CIX_PAD_GPIO018_FUNC_GPIO018 (35 << 8 | 0x1) +#define CIX_PAD_GPIO019_FUNC_SFI_GPIO4 (36 << 8 | 0x0) +#define CIX_PAD_GPIO019_FUNC_GPIO019 (36 << 8 | 0x1) +#define CIX_PAD_GPIO020_FUNC_SFI_GPIO5 (37 << 8 | 0x0) +#define CIX_PAD_GPIO020_FUNC_GPIO020 (37 << 8 | 0x1) +#define CIX_PAD_GPIO021_FUNC_SFI_GPIO6 (38 << 8 | 0x0) +#define CIX_PAD_GPIO021_FUNC_GPIO021 (38 << 8 | 0x1) +#define CIX_PAD_GPIO022_FUNC_SFI_GPIO7 (39 << 8 | 0x0) +#define CIX_PAD_GPIO022_FUNC_GPIO022 (39 << 8 | 0x1) +#define CIX_PAD_GPIO023_FUNC_SFI_GPIO8 (40 << 8 | 0x0) +#define CIX_PAD_GPIO023_FUNC_GPIO023 (40 << 8 | 0x1) +#define CIX_PAD_GPIO023_FUNC_SFI_I3C0_PUR_EN_L (40 << 8 | 0x2) +#define CIX_PAD_GPIO024_FUNC_SFI_GPIO9 (41 << 8 | 0x0) +#define CIX_PAD_GPIO024_FUNC_GPIO024 (41 << 8 | 0x1) +#define CIX_PAD_GPIO024_FUNC_SFI_I3C1_PUR_EN_L (41 << 8 | 0x2) +#define CIX_PAD_SPI1_MISO_FUNC_SPI1_MISO (42 << 8 | 0x0) +#define CIX_PAD_SPI1_MISO_FUNC_GPIO025 (42 << 8 | 0x1) +#define CIX_PAD_SPI1_CS0_FUNC_SPI1_CS0 (43 << 8 | 0x0) +#define CIX_PAD_SPI1_CS0_FUNC_GPIO026 (43 << 8 | 0x1) +#define CIX_PAD_SPI1_CS1_FUNC_SPI1_CS1 (44 << 8 | 0x0) +#define CIX_PAD_SPI1_CS1_FUNC_GPIO027 (44 << 8 | 0x1) +#define CIX_PAD_SPI1_MOSI_FUNC_SPI1_MOSI (45 << 8 | 0x0) +#define CIX_PAD_SPI1_MOSI_FUNC_GPIO028 (45 << 8 | 0x1) +#define CIX_PAD_SPI1_CLK_FUNC_SPI1_CLK (46 << 8 | 0x0) +#define CIX_PAD_SPI1_CLK_FUNC_GPIO029 (46 << 8 | 0x1) +#define CIX_PAD_GPIO030_FUNC_GPIO030 (47 << 8 | 0x0) +#define CIX_PAD_GPIO030_FUNC_USB_OC0_L (47 << 8 | 0x1) +#define CIX_PAD_GPIO031_FUNC_GPIO031 (48 << 8 | 0x0) +#define CIX_PAD_GPIO031_FUNC_USB_OC1_L (48 << 8 | 0x1) +#define CIX_PAD_GPIO032_FUNC_GPIO032 (49 << 8 | 0x0) +#define CIX_PAD_GPIO032_FUNC_USB_OC2_L (49 << 8 | 0x1) +#define CIX_PAD_GPIO033_FUNC_GPIO033 (50 << 8 | 0x0) +#define CIX_PAD_GPIO033_FUNC_USB_OC3_L (50 << 8 | 0x1) +#define CIX_PAD_GPIO034_FUNC_GPIO034 (51 << 8 | 0x0) +#define CIX_PAD_GPIO034_FUNC_USB_OC4_L (51 << 8 | 0x1) +#define CIX_PAD_GPIO035_FUNC_GPIO035 (52 << 8 | 0x0) +#define CIX_PAD_GPIO035_FUNC_USB_OC5_L (52 << 8 | 0x1) +#define CIX_PAD_GPIO036_FUNC_GPIO036 (53 << 8 | 0x0) +#define CIX_PAD_GPIO036_FUNC_USB_OC6_L (53 << 8 | 0x1) +#define CIX_PAD_GPIO037_FUNC_GPIO037 (54 << 8 | 0x0) +#define CIX_PAD_GPIO037_FUNC_USB_OC7_L (54 << 8 | 0x1) +#define CIX_PAD_GPIO038_FUNC_GPIO038 (55 << 8 | 0x0) +#define CIX_PAD_GPIO038_FUNC_USB_OC8_L (55 << 8 | 0x1) +#define CIX_PAD_GPIO039_FUNC_GPIO039 (56 << 8 | 0x0) +#define CIX_PAD_GPIO039_FUNC_USB_OC9_L (56 << 8 | 0x1) +#define CIX_PAD_GPIO040_FUNC_GPIO040 (57 << 8 | 0x0) +#define CIX_PAD_GPIO040_FUNC_USB_DRIVE_VBUS0 (57 << 8 | 0x1) +#define CIX_PAD_GPIO041_FUNC_GPIO041 (58 << 8 | 0x0) +#define CIX_PAD_GPIO041_FUNC_USB_DRIVE_VBUS4 (58 << 8 | 0x1) +#define CIX_PAD_GPIO042_FUNC_GPIO042 (59 << 8 | 0x0) +#define CIX_PAD_GPIO042_FUNC_USB_DRIVE_VBUS5 (59 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_CLK_FUNC_SE_QSPI_CLK (60 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_CLK_FUNC_QSPI_CLK (60 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_CS_L_FUNC_SE_QSPI_CS_L (61 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_CS_L_FUNC_QSPI_CS_L (61 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_DATA0_FUNC_SE_QSPI_DATA0 (62 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_DATA0_FUNC_QSPI_DATA0 (62 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_DATA1_FUNC_SE_QSPI_DATA1 (63 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_DATA1_FUNC_QSPI_DATA1 (63 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_DATA2_FUNC_SE_QSPI_DATA2 (64 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_DATA2_FUNC_QSPI_DATA2 (64 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_DATA3_FUNC_SE_QSPI_DATA3 (65 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_DATA3_FUNC_QSPI_DATA3 (65 << 8 | 0x1) +/* s0 pads */ +#define CIX_PAD_GPIO043_FUNC_GPIO043 (0 << 8 | 0x0) +#define CIX_PAD_GPIO044_FUNC_GPIO044 (1 << 8 | 0x0) +#define CIX_PAD_GPIO045_FUNC_GPIO045 (2 << 8 | 0x0) +#define CIX_PAD_GPIO046_FUNC_GPIO046 (3 << 8 | 0x0) +#define CIX_PAD_DP2_DIGON_FUNC_DP2_DIGON (18 << 8 | 0x0) +#define CIX_PAD_DP2_BLON_FUNC_DP2_BLON (19 << 8 | 0x0) +#define CIX_PAD_DP2_VARY_BL_FUNC_DP2_VARY_BL (20 << 8 | 0x0) +#define CIX_PAD_I2C7_SCL_FUNC_I2C7_SCL (21 << 8 | 0x0) +#define CIX_PAD_I2C7_SDA_FUNC_I2C7_SDA (22 << 8 | 0x0) +#define CIX_PAD_I2C5_SCL_FUNC_I2C5_SCL (26 << 8 | 0x0) +#define CIX_PAD_I2C5_SCL_FUNC_GPIO047 (26 << 8 | 0x1) +#define CIX_PAD_I2C5_SDA_FUNC_I2C5_SDA (27 << 8 | 0x0) +#define CIX_PAD_I2C5_SDA_FUNC_GPIO048 (27 << 8 | 0x1) +#define CIX_PAD_I2C6_SCL_FUNC_I2C6_SCL (28 << 8 | 0x0) +#define CIX_PAD_I2C6_SCL_FUNC_GPIO049 (28 << 8 | 0x1) +#define CIX_PAD_I2C6_SDA_FUNC_I2C6_SDA (29 << 8 | 0x0) +#define CIX_PAD_I2C6_SDA_FUNC_GPIO050 (29 << 8 | 0x1) +#define CIX_PAD_I2C0_CLK_FUNC_I2C0_CLK (30 << 8 | 0x0) +#define CIX_PAD_I2C0_CLK_FUNC_GPIO051 (30 << 8 | 0x1) +#define CIX_PAD_I2C0_SDA_FUNC_I2C0_SDA (31 << 8 | 0x0) +#define CIX_PAD_I2C0_SDA_FUNC_GPIO052 (31 << 8 | 0x1) +#define CIX_PAD_I2C1_CLK_FUNC_I2C1_CLK (32 << 8 | 0x0) +#define CIX_PAD_I2C1_CLK_FUNC_GPIO053 (32 << 8 | 0x1) +#define CIX_PAD_I2C1_SDA_FUNC_I2C1_SDA (33 << 8 | 0x0) +#define CIX_PAD_I2C1_SDA_FUNC_GPIO054 (33 << 8 | 0x1) +#define CIX_PAD_I2C2_SCL_FUNC_I2C2_SCL (34 << 8 | 0x0) +#define CIX_PAD_I2C2_SCL_FUNC_I3C0_SCL (34 << 8 | 0x1) +#define CIX_PAD_I2C2_SCL_FUNC_GPIO055 (34 << 8 | 0x2) +#define CIX_PAD_I2C2_SDA_FUNC_I2C2_SDA (35 << 8 | 0x0) +#define CIX_PAD_I2C2_SDA_FUNC_I3C0_SDA (35 << 8 | 0x1) +#define CIX_PAD_I2C2_SDA_FUNC_GPIO056 (35 << 8 | 0x2) +#define CIX_PAD_GPIO057_FUNC_GPIO057 (36 << 8 | 0x0) +#define CIX_PAD_GPIO057_FUNC_I3C0_PUR_EN_L (36 << 8 | 0x1) +#define CIX_PAD_I2C3_CLK_FUNC_I2C3_CLK (37 << 8 | 0x0) +#define CIX_PAD_I2C3_CLK_FUNC_I3C1_CLK (37 << 8 | 0x1) +#define CIX_PAD_I2C3_CLK_FUNC_GPIO058 (37 << 8 | 0x2) +#define CIX_PAD_I2C3_SDA_FUNC_I2C3_SDA (38 << 8 | 0x0) +#define CIX_PAD_I2C3_SDA_FUNC_I3C1_SDA (38 << 8 | 0x1) +#define CIX_PAD_I2C3_SDA_FUNC_GPIO059 (38 << 8 | 0x2) +#define CIX_PAD_GPIO060_FUNC_GPIO060 (39 << 8 | 0x0) +#define CIX_PAD_GPIO060_FUNC_I3C1_PUR_EN_L (39 << 8 | 0x1) +#define CIX_PAD_I2C4_CLK_FUNC_I2C4_CLK (40 << 8 | 0x0) +#define CIX_PAD_I2C4_CLK_FUNC_GPIO061 (40 << 8 | 0x1) +#define CIX_PAD_I2C4_SDA_FUNC_I2C4_SDA (41 << 8 | 0x0) +#define CIX_PAD_I2C4_SDA_FUNC_GPIO062 (41 << 8 | 0x1) +#define CIX_PAD_HDA_BITCLK_FUNC_HDA_BITCLK (42 << 8 | 0x0) +#define CIX_PAD_HDA_BITCLK_FUNC_I2S0_SCK (42 << 8 | 0x1) +#define CIX_PAD_HDA_BITCLK_FUNC_I2S9_RSCK_DBG (42 << 8 | 0x2) +#define CIX_PAD_HDA_RST_L_FUNC_HDA_RST_L (43 << 8 | 0x0) +#define CIX_PAD_HDA_RST_L_FUNC_I2S0_DATA_IN (43 << 8 | 0x1) +#define CIX_PAD_HDA_RST_L_FUNC_I2S9_DATA_IN0_DBG (43 << 8 | 0x2) +#define CIX_PAD_HDA_SDIN0_FUNC_HDA_SDIN0 (44 << 8 | 0x0) +#define CIX_PAD_HDA_SDIN0_FUNC_I2S0_MCLK (44 << 8 | 0x1) +#define CIX_PAD_HDA_SDIN0_FUNC_I2S9_TSCK_DBG (44 << 8 | 0x2) +#define CIX_PAD_HDA_SDOUT0_FUNC_HDA_SDOUT0 (45 << 8 | 0x0) +#define CIX_PAD_HDA_SDOUT0_FUNC_I2S0_DATA_OUT (45 << 8 | 0x1) +#define CIX_PAD_HDA_SDOUT0_FUNC_I2S9_TWS_DBG (45 << 8 | 0x2) +#define CIX_PAD_HDA_SYNC_FUNC_HDA_SYNC (46 << 8 | 0x0) +#define CIX_PAD_HDA_SYNC_FUNC_I2S0_WS (46 << 8 | 0x1) +#define CIX_PAD_HDA_SYNC_FUNC_I2S9_RWS_DBG (46 << 8 | 0x2) +#define CIX_PAD_HDA_SDIN1_FUNC_HDA_SDIN1 (47 << 8 | 0x0) +#define CIX_PAD_HDA_SDIN1_FUNC_GPIO063 (47 << 8 | 0x1) +#define CIX_PAD_HDA_SDIN1_FUNC_I2S9_DATA_IN1_DBG (47 << 8 | 0x2) +#define CIX_PAD_HDA_SDOUT1_FUNC_HDA_SDOUT1 (48 << 8 | 0x0) +#define CIX_PAD_HDA_SDOUT1_FUNC_GPIO064 (48 << 8 | 0x1) +#define CIX_PAD_HDA_SDOUT1_FUNC_I2S9_DATA_OUT0_DBG (48 << 8 | 0x2) +#define CIX_PAD_I2S1_MCLK_FUNC_I2S1_MCLK (49 << 8 | 0x0) +#define CIX_PAD_I2S1_MCLK_FUNC_GPIO065 (49 << 8 | 0x1) +#define CIX_PAD_I2S1_SCK_FUNC_I2S1_SCK (50 << 8 | 0x0) +#define CIX_PAD_I2S1_SCK_FUNC_GPIO066 (50 << 8 | 0x1) +#define CIX_PAD_I2S1_WS_FUNC_I2S1_WS (51 << 8 | 0x0) +#define CIX_PAD_I2S1_WS_FUNC_GPIO067 (51 << 8 | 0x1) +#define CIX_PAD_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (52 << 8 | 0x0) +#define CIX_PAD_I2S1_DATA_IN_FUNC_GPIO068 (52 << 8 | 0x1) +#define CIX_PAD_I2S1_DATA_OUT_FUNC_I2S1_DATA_OUT (53 << 8 | 0x0) +#define CIX_PAD_I2S1_DATA_OUT_FUNC_GPIO069 (53 << 8 | 0x1) +#define CIX_PAD_I2S2_MCLK_FUNC_I2S2_MCLK (54 << 8 | 0x0) +#define CIX_PAD_I2S2_MCLK_FUNC_GPIO070 (54 << 8 | 0x1) +#define CIX_PAD_I2S2_RSCK_FUNC_I2S2_RSCK (55 << 8 | 0x0) +#define CIX_PAD_I2S2_RSCK_FUNC_GPIO071 (55 << 8 | 0x1) +#define CIX_PAD_I2S2_RSCK_FUNC_I2S5_RSCK_DBG (55 << 8 | 0x2) +#define CIX_PAD_I2S2_RSCK_FUNC_I2S6_RSCK_DBG (55 << 8 | 0x3) +#define CIX_PAD_I2S2_RWS_FUNC_I2S2_RWS (56 << 8 | 0x0) +#define CIX_PAD_I2S2_RWS_FUNC_GPIO072 (56 << 8 | 0x1) +#define CIX_PAD_I2S2_RWS_FUNC_I2S5_RWS_DBG (56 << 8 | 0x2) +#define CIX_PAD_I2S2_RWS_FUNC_I2S6_RWS_DBG (56 << 8 | 0x3) +#define CIX_PAD_I2S2_TSCK_FUNC_I2S2_TSCK (57 << 8 | 0x0) +#define CIX_PAD_I2S2_TSCK_FUNC_GPIO073 (57 << 8 | 0x1) +#define CIX_PAD_I2S2_TSCK_FUNC_I2S5_TSCK_DBG (57 << 8 | 0x2) +#define CIX_PAD_I2S2_TSCK_FUNC_I2S6_TSCK_DBG (57 << 8 | 0x3) +#define CIX_PAD_I2S2_TWS_FUNC_I2S2_TWS (58 << 8 | 0x0) +#define CIX_PAD_I2S2_TWS_FUNC_GPIO074 (58 << 8 | 0x1) +#define CIX_PAD_I2S2_TWS_FUNC_I2S5_TWS_DBG (58 << 8 | 0x2) +#define CIX_PAD_I2S2_TWS_FUNC_I2S6_TWS_DBG (58 << 8 | 0x3) +#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S2_DATA_IN0 (59 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_IN0_FUNC_GPIO075 (59 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S5_DATA_IN0_DBG (59 << 8 | 0x2) +#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S6_DATA_IN0_DBG (59 << 8 | 0x3) +#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S2_DATA_IN1 (60 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_IN1_FUNC_GPIO076 (60 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S5_DATA_IN1_DBG (60 << 8 | 0x2) +#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S6_DATA_IN1_DBG (60 << 8 | 0x3) +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S2_DATA_OUT0 (61 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_GPIO077 (61 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S5_DATA_OUT0_DBG (61 << 8 | 0x2) +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S6_DATA_OUT0_DBG (61 << 8 | 0x3) +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S2_DATA_OUT1 (62 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_GPIO078 (62 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S5_DATA_OUT1_DBG (62 << 8 | 0x2) +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S6_DATA_OUT1_DBG (62 << 8 | 0x3) +#define CIX_PAD_I2S2_DATA_OUT2_FUNC_I2S2_DATA_OUT2 (63 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_OUT2_FUNC_GPIO079 (63 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_OUT3_FUNC_I2S2_DATA_OUT3 (64 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_OUT3_FUNC_GPIO080 (64 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_OUT3_FUNC_I2S9_DATA_OUT1_DBG (64 << 8 | 0x2) +#define CIX_PAD_I2S3_MCLK_FUNC_I2S3_MCLK (65 << 8 | 0x0) +#define CIX_PAD_I2S3_MCLK_FUNC_GPIO081 (65 << 8 | 0x1) +#define CIX_PAD_I2S3_RSCK_FUNC_I2S3_RSCK (66 << 8 | 0x0) +#define CIX_PAD_I2S3_RSCK_FUNC_GPIO082 (66 << 8 | 0x1) +#define CIX_PAD_I2S3_RSCK_FUNC_I2S7_RSCK_DBG (66 << 8 | 0x2) +#define CIX_PAD_I2S3_RSCK_FUNC_I2S8_RSCK_DBG (66 << 8 | 0x3) +#define CIX_PAD_I2S3_RWS_FUNC_I2S3_RWS (67 << 8 | 0x0) +#define CIX_PAD_I2S3_RWS_FUNC_GPIO083 (67 << 8 | 0x1) +#define CIX_PAD_I2S3_RWS_FUNC_I2S7_RWS_DBG (67 << 8 | 0x2) +#define CIX_PAD_I2S3_RWS_FUNC_I2S8_RWS_DBG (67 << 8 | 0x3) +#define CIX_PAD_I2S3_TSCK_FUNC_I2S3_TSCK (68 << 8 | 0x0) +#define CIX_PAD_I2S3_TSCK_FUNC_GPIO084 (68 << 8 | 0x1) +#define CIX_PAD_I2S3_TSCK_FUNC_I2S7_TSCK_DBG (68 << 8 | 0x2) +#define CIX_PAD_I2S3_TSCK_FUNC_I2S8_TSCK_DBG (68 << 8 | 0x3) +#define CIX_PAD_I2S3_TWS_FUNC_I2S3_TWS (69 << 8 | 0x0) +#define CIX_PAD_I2S3_TWS_FUNC_GPIO085 (69 << 8 | 0x1) +#define CIX_PAD_I2S3_TWS_FUNC_I2S7_TWS_DBG (69 << 8 | 0x2) +#define CIX_PAD_I2S3_TWS_FUNC_I2S8_TWS_DBG (69 << 8 | 0x3) +#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S3_DATA_IN0 (70 << 8 | 0x0) +#define CIX_PAD_I2S3_DATA_IN0_FUNC_GPIO086 (70 << 8 | 0x1) +#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S7_DATA_IN0_DBG (70 << 8 | 0x2) +#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S8_DATA_IN0_DBG (70 << 8 | 0x3) +#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S3_DATA_IN1 (71 << 8 | 0x0) +#define CIX_PAD_I2S3_DATA_IN1_FUNC_GPIO087 (71 << 8 | 0x1) +#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S7_DATA_IN1_DBG (71 << 8 | 0x2) +#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S8_DATA_IN1_DBG (71 << 8 | 0x3) +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S3_DATA_OUT0 (72 << 8 | 0x0) +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_GPIO088 (72 << 8 | 0x1) +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S7_DATA_OUT0_DBG (72 << 8 | 0x2) +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S8_DATA_OUT0_DBG (72 << 8 | 0x3) +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S3_DATA_OUT1 (73 << 8 | 0x0) +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_GPIO089 (73 << 8 | 0x1) +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S7_DATA_OUT1_DBG (73 << 8 | 0x2) +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S8_DATA_OUT1_DBG (73 << 8 | 0x3) +#define CIX_PAD_GPIO090_FUNC_GPIO090 (74 << 8 | 0x0) +#define CIX_PAD_GPIO090_FUNC_I2S4_MCLK_LB (74 << 8 | 0x1) +#define CIX_PAD_GPIO091_FUNC_GPIO091 (75 << 8 | 0x0) +#define CIX_PAD_GPIO091_FUNC_I2S4_SCK_LB (75 << 8 | 0x1) +#define CIX_PAD_GPIO092_FUNC_GPIO092 (76 << 8 | 0x0) +#define CIX_PAD_GPIO092_FUNC_I2S4_WS_LB (76 << 8 | 0x1) +#define CIX_PAD_GPIO093_FUNC_GPIO093 (77 << 8 | 0x0) +#define CIX_PAD_GPIO093_FUNC_I2S4_DATA_IN_LB (77 << 8 | 0x1) +#define CIX_PAD_GPIO094_FUNC_GPIO094 (78 << 8 | 0x0) +#define CIX_PAD_GPIO094_FUNC_I2S4_DATA_OUT_LB (78 << 8 | 0x1) +#define CIX_PAD_UART0_TXD_FUNC_UART0_TXD (79 << 8 | 0x0) +#define CIX_PAD_UART0_TXD_FUNC_PWM0 (79 << 8 | 0x1) +#define CIX_PAD_UART0_TXD_FUNC_GPIO095 (79 << 8 | 0x2) +#define CIX_PAD_UART0_RXD_FUNC_UART0_RXD (80 << 8 | 0x0) +#define CIX_PAD_UART0_RXD_FUNC_PWM1 (80 << 8 | 0x1) +#define CIX_PAD_UART0_RXD_FUNC_GPIO096 (80 << 8 | 0x2) +#define CIX_PAD_UART0_CTS_FUNC_UART0_CTS (81 << 8 | 0x0) +#define CIX_PAD_UART0_CTS_FUNC_FAN_OUT2 (81 << 8 | 0x1) +#define CIX_PAD_UART0_CTS_FUNC_GPIO097 (81 << 8 | 0x2) +#define CIX_PAD_UART0_RTS_FUNC_UART0_RTS (82 << 8 | 0x0) +#define CIX_PAD_UART0_RTS_FUNC_FAN_TACH2 (82 << 8 | 0x1) +#define CIX_PAD_UART0_RTS_FUNC_GPIO098 (82 << 8 | 0x2) +#define CIX_PAD_UART1_TXD_FUNC_UART1_TXD (83 << 8 | 0x0) +#define CIX_PAD_UART1_TXD_FUNC_FAN_OUT0 (83 << 8 | 0x1) +#define CIX_PAD_UART1_TXD_FUNC_GPIO099 (83 << 8 | 0x2) +#define CIX_PAD_UART1_RXD_FUNC_UART1_RXD (84 << 8 | 0x0) +#define CIX_PAD_UART1_RXD_FUNC_FAN_TACH0 (84 << 8 | 0x1) +#define CIX_PAD_UART1_RXD_FUNC_GPIO100 (84 << 8 | 0x2) +#define CIX_PAD_UART1_CTS_FUNC_UART1_CTS (85 << 8 | 0x0) +#define CIX_PAD_UART1_CTS_FUNC_FAN_OUT1 (85 << 8 | 0x1) +#define CIX_PAD_UART1_CTS_FUNC_GPIO101 (85 << 8 | 0x2) +#define CIX_PAD_UART1_RTS_FUNC_UART1_RTS (86 << 8 | 0x0) +#define CIX_PAD_UART1_RTS_FUNC_FAN_TACH1 (86 << 8 | 0x1) +#define CIX_PAD_UART1_RTS_FUNC_GPIO102 (86 << 8 | 0x2) +#define CIX_PAD_UART2_TXD_FUNC_UART2_TXD (87 << 8 | 0x0) +#define CIX_PAD_UART2_TXD_FUNC_GPIO103 (87 << 8 | 0x1) +#define CIX_PAD_UART2_RXD_FUNC_UART2_RXD (88 << 8 | 0x0) +#define CIX_PAD_UART2_RXD_FUNC_GPIO104 (88 << 8 | 0x1) +#define CIX_PAD_UART3_TXD_FUNC_UART3_TXD (89 << 8 | 0x0) +#define CIX_PAD_UART3_TXD_FUNC_GPIO105 (89 << 8 | 0x1) +#define CIX_PAD_UART3_RXD_FUNC_UART3_RXD (90 << 8 | 0x0) +#define CIX_PAD_UART3_RXD_FUNC_GPIO106 (90 << 8 | 0x1) +#define CIX_PAD_UART3_CTS_FUNC_UART3_CTS (91 << 8 | 0x0) +#define CIX_PAD_UART3_CTS_FUNC_GPIO107 (91 << 8 | 0x1) +#define CIX_PAD_UART3_CTS_FUNC_TRIGIN0 (91 << 8 | 0x2) +#define CIX_PAD_UART3_RTS_FUNC_UART3_RTS (92 << 8 | 0x0) +#define CIX_PAD_UART3_RTS_FUNC_GPIO108 (92 << 8 | 0x1) +#define CIX_PAD_UART3_RTS_FUNC_TRIGIN1 (92 << 8 | 0x2) +#define CIX_PAD_UART4_CSU_PM_TXD_FUNC_UART4_CSU_PM_TXD (93 << 8 | 0x0) +#define CIX_PAD_UART4_CSU_PM_TXD_FUNC_GPIO109 (93 << 8 | 0x1) +#define CIX_PAD_UART4_CSU_PM_RXD_FUNC_UART4_CSU_PM_RXD (94 << 8 | 0x0) +#define CIX_PAD_UART4_CSU_PM_RXD_FUNC_GPIO110 (94 << 8 | 0x1) +#define CIX_PAD_UART5_CSU_SE_TXD_FUNC_UART5_CSU_SE_TXD (95 << 8 | 0x0) +#define CIX_PAD_UART5_CSU_SE_TXD_FUNC_GPIO111 (95 << 8 | 0x1) +#define CIX_PAD_UART5_CSU_SE_RXD_FUNC_UART5_CSU_SE_RXD (96 << 8 | 0x0) +#define CIX_PAD_UART5_CSU_SE_RXD_FUNC_GPIO112 (96 << 8 | 0x1) +#define CIX_PAD_UART6_CSU_SE_RXD_FUNC_UART6_CSU_SE_RXD (97 << 8 | 0x0) +#define CIX_PAD_UART6_CSU_SE_RXD_FUNC_GPIO113 (97 << 8 | 0x1) +#define CIX_PAD_CLK_REQ0_L_FUNC_CLK_REQ0_L (98 << 8 | 0x0) +#define CIX_PAD_CLK_REQ0_L_FUNC_GPIO114 (98 << 8 | 0x1) +#define CIX_PAD_CLK_REQ2_L_FUNC_CLK_REQ2_L (99 << 8 | 0x0) +#define CIX_PAD_CLK_REQ2_L_FUNC_GPIO115 (99 << 8 | 0x1) +#define CIX_PAD_CLK_REQ4_L_FUNC_CLK_REQ4_L (100 << 8 | 0x0) +#define CIX_PAD_CLK_REQ4_L_FUNC_GPIO116 (100 << 8 | 0x1) +#define CIX_PAD_CSI0_MCLK0_FUNC_CSI0_MCLK0 (101 << 8 | 0x0) +#define CIX_PAD_CSI0_MCLK0_FUNC_GPIO117 (101 << 8 | 0x1) +#define CIX_PAD_CSI0_MCLK1_FUNC_CSI0_MCLK1 (102 << 8 | 0x0) +#define CIX_PAD_CSI0_MCLK1_FUNC_GPIO118 (102 << 8 | 0x1) +#define CIX_PAD_CSI1_MCLK0_FUNC_CSI1_MCLK0 (103 << 8 | 0x0) +#define CIX_PAD_CSI1_MCLK0_FUNC_GPIO119 (103 << 8 | 0x1) +#define CIX_PAD_CSI1_MCLK1_FUNC_CSI1_MCLK1 (104 << 8 | 0x0) +#define CIX_PAD_CSI1_MCLK1_FUNC_GPIO120 (104 << 8 | 0x1) +#define CIX_PAD_GPIO121_FUNC_GPIO121 (105 << 8 | 0x0) +#define CIX_PAD_GPIO121_FUNC_GMAC0_REFCLK_25M (105 << 8 | 0x1) +#define CIX_PAD_GPIO122_FUNC_GPIO122 (106 << 8 | 0x0) +#define CIX_PAD_GPIO122_FUNC_GMAC0_TX_CTL (106 << 8 | 0x1) +#define CIX_PAD_GPIO123_FUNC_GPIO123 (107 << 8 | 0x0) +#define CIX_PAD_GPIO123_FUNC_GMAC0_TXD0 (107 << 8 | 0x1) +#define CIX_PAD_GPIO124_FUNC_GPIO124 (108 << 8 | 0x0) +#define CIX_PAD_GPIO124_FUNC_GMAC0_TXD1 (108 << 8 | 0x1) +#define CIX_PAD_GPIO125_FUNC_GPIO125 (109 << 8 | 0x0) +#define CIX_PAD_GPIO125_FUNC_GMAC0_TXD2 (109 << 8 | 0x1) +#define CIX_PAD_GPIO126_FUNC_GPIO126 (110 << 8 | 0x0) +#define CIX_PAD_GPIO126_FUNC_GMAC0_TXD3 (110 << 8 | 0x1) +#define CIX_PAD_GPIO127_FUNC_GPIO127 (111 << 8 | 0x0) +#define CIX_PAD_GPIO127_FUNC_GMAC0_TX_CLK (111 << 8 | 0x1) +#define CIX_PAD_GPIO128_FUNC_GPIO128 (112 << 8 | 0x0) +#define CIX_PAD_GPIO128_FUNC_GMAC0_RX_CTL (112 << 8 | 0x1) +#define CIX_PAD_GPIO129_FUNC_GPIO129 (113 << 8 | 0x0) +#define CIX_PAD_GPIO129_FUNC_GMAC0_RXD0 (113 << 8 | 0x1) +#define CIX_PAD_GPIO130_FUNC_GPIO130 (114 << 8 | 0x0) +#define CIX_PAD_GPIO130_FUNC_GMAC0_RXD1 (114 << 8 | 0x1) +#define CIX_PAD_GPIO131_FUNC_GPIO131 (115 << 8 | 0x0) +#define CIX_PAD_GPIO131_FUNC_GMAC0_RXD2 (115 << 8 | 0x1) +#define CIX_PAD_GPIO132_FUNC_GPIO132 (116 << 8 | 0x0) +#define CIX_PAD_GPIO132_FUNC_GMAC0_RXD3 (116 << 8 | 0x1) +#define CIX_PAD_GPIO133_FUNC_GPIO133 (117 << 8 | 0x0) +#define CIX_PAD_GPIO133_FUNC_GMAC0_RX_CLK (117 << 8 | 0x1) +#define CIX_PAD_GPIO134_FUNC_GPIO134 (118 << 8 | 0x0) +#define CIX_PAD_GPIO134_FUNC_GMAC0_MDC (118 << 8 | 0x1) +#define CIX_PAD_GPIO135_FUNC_GPIO135 (119 << 8 | 0x0) +#define CIX_PAD_GPIO135_FUNC_GMAC0_MDIO (119 << 8 | 0x1) +#define CIX_PAD_GPIO136_FUNC_GPIO136 (120 << 8 | 0x0) +#define CIX_PAD_GPIO136_FUNC_GMAC1_REFCLK_25M (120 << 8 | 0x1) +#define CIX_PAD_GPIO137_FUNC_GPIO137 (121 << 8 | 0x0) +#define CIX_PAD_GPIO137_FUNC_GMAC1_TX_CTL (121 << 8 | 0x1) +#define CIX_PAD_GPIO138_FUNC_GPIO138 (122 << 8 | 0x0) +#define CIX_PAD_GPIO138_FUNC_GMAC1_TXD0 (122 << 8 | 0x1) +#define CIX_PAD_GPIO138_FUNC_SPI2_MISO (122 << 8 | 0x2) +#define CIX_PAD_GPIO139_FUNC_GPIO139 (123 << 8 | 0x0) +#define CIX_PAD_GPIO139_FUNC_GMAC1_TXD1 (123 << 8 | 0x1) +#define CIX_PAD_GPIO139_FUNC_SPI2_CS0 (123 << 8 | 0x2) +#define CIX_PAD_GPIO140_FUNC_GPIO140 (124 << 8 | 0x0) +#define CIX_PAD_GPIO140_FUNC_GMAC1_TXD2 (124 << 8 | 0x1) +#define CIX_PAD_GPIO140_FUNC_SPI2_CS1 (124 << 8 | 0x2) +#define CIX_PAD_GPIO141_FUNC_GPIO141 (125 << 8 | 0x0) +#define CIX_PAD_GPIO141_FUNC_GMAC1_TXD3 (125 << 8 | 0x1) +#define CIX_PAD_GPIO141_FUNC_SPI2_MOSI (125 << 8 | 0x2) +#define CIX_PAD_GPIO142_FUNC_GPIO142 (126 << 8 | 0x0) +#define CIX_PAD_GPIO142_FUNC_GMAC1_TX_CLK (126 << 8 | 0x1) +#define CIX_PAD_GPIO142_FUNC_SPI2_CLK (126 << 8 | 0x2) +#define CIX_PAD_GPIO143_FUNC_GPIO143 (127 << 8 | 0x0) +#define CIX_PAD_GPIO143_FUNC_GMAC1_RX_CTL (127 << 8 | 0x1) +#define CIX_PAD_GPIO144_FUNC_GPIO144 (128 << 8 | 0x0) +#define CIX_PAD_GPIO144_FUNC_GMAC1_RXD0 (128 << 8 | 0x1) +#define CIX_PAD_GPIO145_FUNC_GPIO145 (129 << 8 | 0x0) +#define CIX_PAD_GPIO145_FUNC_GMAC1_RXD1 (129 << 8 | 0x1) +#define CIX_PAD_GPIO146_FUNC_GPIO146 (130 << 8 | 0x0) +#define CIX_PAD_GPIO146_FUNC_GMAC1_RXD2 (130 << 8 | 0x1) +#define CIX_PAD_GPIO147_FUNC_GPIO147 (131 << 8 | 0x0) +#define CIX_PAD_GPIO147_FUNC_GMAC1_RXD3 (131 << 8 | 0x1) +#define CIX_PAD_GPIO148_FUNC_GPIO148 (132 << 8 | 0x0) +#define CIX_PAD_GPIO148_FUNC_GMAC1_RX_CLK (132 << 8 | 0x1) +#define CIX_PAD_GPIO149_FUNC_GPIO149 (133 << 8 | 0x0) +#define CIX_PAD_GPIO149_FUNC_GMAC1_MDC (133 << 8 | 0x1) +#define CIX_PAD_GPIO150_FUNC_GPIO150 (134 << 8 | 0x0) +#define CIX_PAD_GPIO150_FUNC_GMAC1_MDIO (134 << 8 | 0x1) +#define CIX_PAD_GPIO151_FUNC_GPIO151 (135 << 8 | 0x0) +#define CIX_PAD_GPIO151_FUNC_PM_GPIO0 (135 << 8 | 0x1) +#define CIX_PAD_GPIO152_FUNC_GPIO152 (136 << 8 | 0x0) +#define CIX_PAD_GPIO152_FUNC_PM_GPIO1 (136 << 8 | 0x1) +#define CIX_PAD_GPIO153_FUNC_GPIO153 (137 << 8 | 0x0) +#define CIX_PAD_GPIO153_FUNC_PM_GPIO2 (137 << 8 | 0x1) + +#endif diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index ea324336bf34..3bc4c4f09ec2 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -348,6 +348,11 @@ i3c1: i3c@4100000 { status = "disabled"; }; + iomuxc: pinctrl@4170000 { + compatible = "cix,sky1-pinctrl"; + reg = <0x0 0x04170000 0x0 0x1000>; + }; + mbox_ap2se: mailbox@5060000 { compatible = "cix,sky1-mbox"; reg = <0x0 0x05060000 0x0 0x10000>; @@ -436,6 +441,11 @@ ppi_partition1: interrupt-partition-1 { }; }; }; + + iomuxc_s5: pinctrl@16007000 { + compatible = "cix,sky1-pinctrl-s5"; + reg = <0x0 0x16007000 0x0 0x1000>; + }; }; timer { From 0b014cd8f15e3b8607fa1e9e25e5566c9eac75f2 Mon Sep 17 00:00:00 2001 From: Hans Zhang Date: Sat, 8 Nov 2025 22:03:04 +0800 Subject: [PATCH 3/5] arm64: dts: cix: Add PCIe Root Complex on sky1 Add pcie_x*_rc node to support Sky1 PCIe driver based on the Cadence PCIe core. Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts using the ARM GICv3. Acked-by: Manivannan Sadhasivam Signed-off-by: Hans Zhang Link: https://lore.kernel.org/r/20251108140305.1120117-10-hans.zhang@cixtech.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1.dtsi | 126 ++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 3bc4c4f09ec2..f4be70a6278b 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -413,6 +413,132 @@ mbox_ap2sfh: mailbox@80a0000 { cix,mbox-dir = "tx"; }; + pcie_x8_rc: pcie@a010000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x0a000300 0x00 0x100>, + <0x00 0x0a000400 0x00 0x100>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, + <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0xc0 0xff>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0xc000 &gic_its 0xc000 0x4000>; + status = "disabled"; + }; + + pcie_x4_rc: pcie@a070000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a070000 0x00 0x10000>, + <0x00 0x29000000 0x00 0x3000000>, + <0x00 0x0a060300 0x00 0x40>, + <0x00 0x0a060400 0x00 0x40>, + <0x00 0x50000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, + <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, + <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x90 0xbf>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0x9000 &gic_its 0x9000 0x3000>; + status = "disabled"; + }; + + pcie_x2_rc: pcie@a0c0000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a0c0000 0x00 0x10000>, + <0x00 0x26000000 0x00 0x3000000>, + <0x00 0x0a0600340 0x00 0x20>, + <0x00 0x0a0600440 0x00 0x20>, + <0x00 0x40000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, + <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x60 0x8f>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0x6000 &gic_its 0x6000 0x3000>; + status = "disabled"; + }; + + pcie_x1_0_rc: pcie@a0d0000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a0d0000 0x00 0x10000>, + <0x00 0x20000000 0x00 0x3000000>, + <0x00 0x0a060360 0x00 0x20>, + <0x00 0x0a060460 0x00 0x20>, + <0x00 0x30000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, + <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, + <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x2f>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0x0000 &gic_its 0x0000 0x3000>; + status = "disabled"; + }; + + pcie_x1_1_rc: pcie@a0e0000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a0e0000 0x00 0x10000>, + <0x00 0x23000000 0x00 0x3000000>, + <0x00 0x0a060380 0x00 0x20>, + <0x00 0x0a060480 0x00 0x20>, + <0x00 0x38000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, + <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, + <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x30 0x5f>; + device_type = "pci"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0x3000 &gic_its 0x3000 0x3000>; + status = "disabled"; + }; + gic: interrupt-controller@e010000 { compatible = "arm,gic-v3"; reg = <0x0 0x0e010000 0 0x10000>, /* GICD */ From b2bc5a821b941b15ed46df39b7c21c48510bea47 Mon Sep 17 00:00:00 2001 From: Hans Zhang Date: Sat, 8 Nov 2025 22:03:05 +0800 Subject: [PATCH 4/5] arm64: dts: cix: Enable PCIe on the Orion O6 board Add PCIe RC support on Orion O6 board. The Orion O6 board includes multiple PCIe root complexes. The current device tree configuration enables detection and basic operation of PCIe endpoints on this platform. GPIO and pinctrl subsystems for this platform are not yet ready for upstream inclusion. Consequently, attributes such as reset-gpios and pinctrl configurations are temporarily omitted from the PCIe node definitions. Endpoint detection and functionality are confirmed to be operational with this basic configuration. The missing GPIO and pinctrl support will be added incrementally in future patches as the dependent subsystems become available upstream. Acked-by: Manivannan Sadhasivam Signed-off-by: Hans Zhang Link: https://lore.kernel.org/r/20251108140305.1120117-11-hans.zhang@cixtech.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts index cdaca197edda..4dee8cd0b86d 100644 --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -66,6 +66,26 @@ pins { }; }; +&pcie_x8_rc { + status = "okay"; +}; + +&pcie_x4_rc { + status = "okay"; +}; + +&pcie_x2_rc { + status = "okay"; +}; + +&pcie_x1_0_rc { + status = "okay"; +}; + +&pcie_x1_1_rc { + status = "okay"; +}; + &uart2 { status = "okay"; }; From 7dfe67ab5a830083d28a072d262c5f6d3df6b39f Mon Sep 17 00:00:00 2001 From: Jun Guo Date: Fri, 31 Oct 2025 15:30:03 +0800 Subject: [PATCH 5/5] arm64: dts: cix: add a compatible string for the cix sky1 SoC The SPI IP design for the cix sky1 SoC uses a FIFO with a data width of 32 bits, instead of the default 8 bits. Therefore, a compatible string is added to specify the FIFO data width configuration for the cix sky1 SoC. Signed-off-by: Jun Guo Link: https://lore.kernel.org/r/20251031073003.3289573-4-jun.guo@cixtech.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index f4be70a6278b..64b76905cbff 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -265,7 +265,7 @@ i2c7: i2c@4080000 { }; spi0: spi@4090000 { - compatible = "cdns,spi-r1p6"; + compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; reg = <0x0 0x04090000 0x0 0x10000>; clocks = <&scmi_clk CLK_TREE_FCH_SPI0_APB>, <&scmi_clk CLK_TREE_FCH_SPI0_APB>; @@ -275,7 +275,7 @@ spi0: spi@4090000 { }; spi1: spi@40a0000 { - compatible = "cdns,spi-r1p6"; + compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; reg = <0x0 0x040a0000 0x0 0x10000>; clocks = <&scmi_clk CLK_TREE_FCH_SPI1_APB>, <&scmi_clk CLK_TREE_FCH_SPI1_APB>;