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arm64: dts: hi3798cv200: add GICH, GICV register space and irq

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This is needed by KVM to make use of VGIC code. Just like regular
GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been
verified.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Link: https://lore.kernel.org/r/20240219-cache-v3-2-a33c57534ae9@outlook.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Yang Xiwen 2024-02-19 23:05:27 +08:00 committed by Krzysztof Kozlowski
parent 428a575dc9
commit f00a6b9644
1 changed files with 5 additions and 1 deletions
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6
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
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@ -58,7 +58,11 @@ cpu@3 {
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
<0x0 0xf1002000 0x0 0x2000>; /* GICC */
<0x0 0xf1002000 0x0 0x2000>, /* GICC */
<0x0 0xf1004000 0x0 0x2000>, /* GICH */
<0x0 0xf1006000 0x0 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;