drm/amd/pm/si: Fix updating clock limits on AC/DC

Assume that the AC limits are the maximum of all power states,
and the DC limits are the maximum of battery power states.
This shouldn't make any difference in practice, but is
cleaner and more robust against bogus information in the VBIOS.

Fixes: e6c5d36756 ("drm/amd/pm/si: Fix updating clock limits from power states")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://patch.msgid.link/20260923120354.1027996-2-timur.kristof@gmail.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Timur Kristóf 2026-09-23 14:03:54 +02:00 committed by Alex Deucher
parent a113d4d659
commit ef8cb9dcc7

View File

@ -7238,6 +7238,19 @@ static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
adev->pm.dpm.uvd_ps = rps;
}
static void si_update_limits(struct amdgpu_clock_and_voltage_limits *limits,
struct rv7xx_pl *pl)
{
if (pl->sclk > limits->sclk)
limits->sclk = pl->sclk;
if (pl->mclk > limits->mclk)
limits->mclk = pl->mclk;
if (pl->vddc > limits->vddc)
limits->vddc = pl->vddc;
if (pl->vddci > limits->vddci)
limits->vddci = pl->vddci;
}
static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
struct amdgpu_ps *rps, int index,
union pplib_clock_info *clock_info)
@ -7246,7 +7259,6 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
struct si_power_info *si_pi = si_get_pi(adev);
struct si_ps *ps = si_get_ps(rps);
struct amdgpu_clock_and_voltage_limits *limits;
u16 leakage_voltage;
struct rv7xx_pl *pl = &ps->performance_levels[index];
int ret;
@ -7311,26 +7323,14 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
* VBIOS can contain conflicting values between:
* - the maximum allowed clocks and voltages on AC or DC
* - the clocks and voltages in power states on AC or DC
*
* Assume that the AC limits are the maximum of all power states,
* and the DC limits are the maximum of battery power states.
*/
si_update_limits(&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac, pl);
if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
else if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
else
limits = NULL;
if (limits) {
if (pl->sclk > limits->sclk)
limits->sclk = pl->sclk;
if (pl->mclk > limits->mclk)
limits->mclk = pl->mclk;
if (pl->vddc > limits->vddc)
limits->vddc = pl->vddc;
if (pl->vddci > limits->vddci)
limits->vddci = pl->vddci;
}
si_update_limits(&adev->pm.dpm.dyn_state.max_clock_voltage_on_dc, pl);
}
union pplib_power_state {