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watchdog: rzv2h: Add support for configurable count clock source

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Add support for selecting the count clock source used by the watchdog
timer. The RZ/V2H(P) SoC uses the LOCO as the count source, whereas on
RZ/T2H and RZ/N2H SoCs, the count source is the peripheral clock (PCLKL).

Introduce a `count_source` field in the SoC-specific data structure and
refactor the clock rate selection logic accordingly. This prepares the
driver for supporting the RZ/T2H and RZ/N2H SoCs, which differ in their
watchdog clocking architecture from RZ/V2H(P).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
Lad Prabhakar 2025-08-20 21:23:20 +01:00 committed by Wim Van Sebroeck
parent 6229b35298
commit ef6080fec6
1 changed files with 20 additions and 1 deletions
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21
drivers/watchdog/rzv2h_wdt.c
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@ -42,12 +42,18 @@ module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
enum rzv2h_wdt_count_source {
COUNT_SOURCE_LOCO,
COUNT_SOURCE_PCLK,
};
struct rzv2h_of_data {
u8 cks_min;
u8 cks_max;
u16 cks_div;
u8 tops;
u16 timeout_cycles;
enum rzv2h_wdt_count_source count_source;
};
struct rzv2h_wdt_priv {
@ -214,6 +220,7 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct rzv2h_wdt_priv *priv;
struct clk *count_clk;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@ -239,8 +246,19 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(priv->rstc),
"failed to get cpg reset");
switch (priv->of_data->count_source) {
case COUNT_SOURCE_LOCO:
count_clk = priv->oscclk;
break;
case COUNT_SOURCE_PCLK:
count_clk = priv->pclk;
break;
default:
return dev_err_probe(dev, -EINVAL, "Invalid count source\n");
}
priv->wdev.max_hw_heartbeat_ms = (MILLI * priv->of_data->timeout_cycles *
priv->of_data->cks_div) / clk_get_rate(priv->oscclk);
priv->of_data->cks_div) / clk_get_rate(count_clk);
dev_dbg(dev, "max hw timeout of %dms\n", priv->wdev.max_hw_heartbeat_ms);
ret = devm_pm_runtime_enable(dev);
@ -269,6 +287,7 @@ static const struct rzv2h_of_data rzv2h_wdt_of_data = {
.cks_div = 256,
.tops = WDTCR_TOPS_16384,
.timeout_cycles = 16384,
.count_source = COUNT_SOURCE_LOCO,
};
static const struct of_device_id rzv2h_wdt_ids[] = {