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ASoC: SOF: Intel: Add HDA controller for Intel DSP
Support HDA controller operations for DSP and provide space for future DSP HDA FW integration. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
This commit is contained in:
Liam Girdwood
Pierre-Louis Bossart
parent
9d53e0f780
commit
ef57a22979
169
sound/soc/sof/intel/hda-ctrl.c
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169
sound/soc/sof/intel/hda-ctrl.c
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Jeeja KP <jeeja.kp@intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for generic Intel audio DSP HDA IP
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*/
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#include <linux/delay.h>
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#include <linux/fs.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/firmware.h>
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#include <linux/pci.h>
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#include <sound/hdaudio_ext.h>
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#include <sound/sof.h>
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#include <sound/pcm_params.h>
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#include <linux/pm_runtime.h>
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#include "../sof-priv.h"
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#include "../ops.h"
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#include "hda.h"
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/*
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* HDA Operations.
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*/
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int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev)
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{
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unsigned long timeout;
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u32 gctl = 0;
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/* reset the HDA controller */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,
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SOF_HDA_GCTL_RESET, 0);
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/* wait for reset */
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timeout = jiffies + msecs_to_jiffies(HDA_DSP_CTRL_RESET_TIMEOUT);
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while (time_before(jiffies, timeout)) {
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usleep_range(500, 1000);
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gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
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if ((gctl & SOF_HDA_GCTL_RESET) == 0)
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goto clear;
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}
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/* reset failed */
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dev_err(sdev->dev, "error: failed to reset HDA controller gctl 0x%x\n",
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gctl);
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return -EIO;
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clear:
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/* wait for codec */
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usleep_range(500, 1000);
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/* now take controller out of reset */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,
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SOF_HDA_GCTL_RESET, SOF_HDA_GCTL_RESET);
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/* wait for controller to be ready */
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timeout = jiffies + msecs_to_jiffies(HDA_DSP_CTRL_RESET_TIMEOUT);
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while (time_before(jiffies, timeout)) {
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gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
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if ((gctl & SOF_HDA_GCTL_RESET) == 1)
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return 0;
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usleep_range(500, 1000);
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}
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/* reset failed */
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dev_err(sdev->dev, "error: failed to ready HDA controller gctl 0x%x\n",
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gctl);
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return -EIO;
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}
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int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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u32 cap, offset, feature;
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int count = 0;
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offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);
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do {
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cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);
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dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",
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offset & SOF_HDA_CAP_NEXT_MASK);
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feature = (cap & SOF_HDA_CAP_ID_MASK) >> SOF_HDA_CAP_ID_OFF;
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switch (feature) {
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case SOF_HDA_PP_CAP_ID:
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dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",
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offset);
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bus->ppcap = bus->remap_addr + offset;
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sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;
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break;
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case SOF_HDA_SPIB_CAP_ID:
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dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",
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offset);
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bus->spbcap = bus->remap_addr + offset;
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sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;
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break;
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case SOF_HDA_DRSM_CAP_ID:
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dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",
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offset);
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bus->drsmcap = bus->remap_addr + offset;
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sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;
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break;
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case SOF_HDA_GTS_CAP_ID:
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dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",
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offset);
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bus->gtscap = bus->remap_addr + offset;
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break;
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case SOF_HDA_ML_CAP_ID:
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dev_dbg(sdev->dev, "found ML capability at 0x%x\n",
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offset);
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bus->mlcap = bus->remap_addr + offset;
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break;
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default:
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dev_vdbg(sdev->dev, "found capability %d at 0x%x\n",
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feature, offset);
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break;
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}
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offset = cap & SOF_HDA_CAP_NEXT_MASK;
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} while (count++ <= SOF_HDA_MAX_CAPS && offset);
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return 0;
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}
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void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
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{
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u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0;
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snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);
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}
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/*
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* While performing reset, controller may not come back properly and causing
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* issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
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* (init chip) and then again set CGCTL.MISCBDCGE to 1
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*/
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int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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int ret;
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hda_dsp_ctrl_misc_clock_gating(sdev, false);
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ret = snd_hdac_bus_init_chip(bus, full_reset);
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hda_dsp_ctrl_misc_clock_gating(sdev, true);
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return ret;
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}
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#endif
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