mirror of
https://github.com/torvalds/linux.git
synced 2026-05-24 15:12:13 +02:00
Qualcomm clock updates for v6.11
This adds clock controllers for SM7150 camera, display and video, QCM2290 GPU, QCS8386/QCS8084 NSS, SM8650 camera and video. qcom_cc_really_probe() is transitioned to take a struct device, to allow reuse in non-platform-drivers. Prepare-only branch clock ops are introduced to support clocks on buses that takes locks. The parent/child relationship for SC7280 camera GDSCs are added. Support for the Huayra 2290 alpha PLL is added. The highest SDCC clock frequency on IPQ6018 is adjusted to match the HS200 support. For IPQ9574 missing PCIe PIPE clocks are added. Various configuration and properties of the SA8775P, X1E80100 and SM7280 clocks and GDSCs are corrected. SM8350 GPU RCGs are made to park on XO while disabled. Unused CONFIG_QCOM_RPMCC Kconfig symbol is removed, and missing MODULE_DESCRIPTIONs are added in a few drivers. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmaJglgVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FpRAQAItnvABmeAHsiHzGLBhhu8Th6VnM A7K6RnauGbwq935hhwrffLKT4/j+0rAJkkRP0AwgdsKVyi+rxcnGABkQMpjYpDwu i4PbYnhyxqn47JEkOyHkeUWKawEfzTVghtsez5+3KUyPVYU/K7UwbVqrvX/1j+Tj 23a+D0cDgNQ0BkXxkm5+SPRIYEZBihqfZx6rgbxF23YR8jAGvi/I0pVsP0RuErQ0 pGuUKFgRtJQ4NbOih4X+43STLqmDu7gAm/opJZxEHfewh+np9X37QmMTsgbSHnfv Kldyx+iqxB/klr7Za8vkrjsBhGyftfbOAQ/xtxZFoiIOH7ohLJpbeSsguTpOO8Cb rdkdn09pjl/EPv7QjKiOpgCTrM5PuBjT6tfr4clBQkryPkQyyl89lP3A4d2k17Np wYae2P9X9JRC45L550h400R/pX6nKUQexgiiwlZkYFjB20oGTbgZ2Kj7B3rF6es2 y+veNfPoa3QMweEbW9MtKzMpIyW+kbtpGTkAlzbljbDAR0wbuom8h02LbXqWz6Bo yPWn3zXtpYfNyEfxbYHFc4I3YejZBkq/y5fh0Uka7YemvGyWazvY8/UC3BVYajSP SdpOx/T81S0u03yV8V4F/kEBB+5vT2DvseV39G8sM+1Ysj5sQldlN0Pk0gwE2f3U RSaEoUK1C2gP8xvo =jddZ -----END PGP SIGNATURE----- Merge tag 'qcom-clk-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: - Add clk drivers for Qualcomm SM7150 camera, display and video - Add Qualcomm QCM2290 GPU clk driver - Add Qualcomm QCS8386/QCS8084 NSS clk driver - Add Qualcomm SM8650 camera and video drivers - Make qcom_cc_really_probe() take a struct device to allow reuse in non-platform-drivers - Introduce prepare-only branch clock ops in the qcom clk driver to support clocks on buses that take locks - Describe parent/child relationship for Qualcomm SC7280 camera GDSCs - Support Qualcomm Huayra 2290 alpha PLL - Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to match HS200 support - Add missing PCIe PIPE clocks on Qualcomm IPQ9574 - Fix various configurations and properties in the Qualcomm SA8775P, X1E80100 and SM7280 drivers - Park Qualcomm SM8350 GPU RCGs on XO while disabled - Remove unused CONFIG_QCOM_RPMCC Kconfig symbol - Add missing MODULE_DESCRIPTIONs to some qcom clk drivers * tag 'qcom-clk-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (61 commits) clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks clk: qcom: gcc-ipq6018: update sdcc max clock frequency clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver dt-bindings: clock: qcom: Add SM8650 camera clock controller dt-bindings: clock: qcom: Update the order of SC8280XP camcc header clk: qcom: videocc-sm8550: Add SM8650 video clock controller clk: qcom: videocc-sm8550: Add support for videocc XO clk ares dt-bindings: clock: qcom: Add SM8650 video clock controller dt-bindings: clock: qcom: Update SM8450 videocc header file name clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON flags clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for gcc_ufs_phy_ice_core_clk clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks clk: qcom: gpucc-sm8350: Park RCG's clk source at XO during disable clk: qcom: nsscc-qca8k: Fix the MDIO functions undefined issue clk: qcom: select right config in CLK_QCM2290_GPUCC definition clk: qcom: Remove QCOM_RPMCC symbol clk: qcom: Add QCM2290 GPU clock controller driver ...
This commit is contained in:
Stephen Boyd
commit
ef0ae098a1
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@ -40,31 +40,19 @@ properties:
|
|||
- description: DSI 1 PLL byte clock
|
||||
- description: DSI 1 PLL DSI clock
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||||
|
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'#clock-cells':
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const: 1
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||||
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'#reset-cells':
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const: 1
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||||
|
||||
'#power-domain-cells':
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||||
const: 1
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||||
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||||
reg:
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maxItems: 1
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||||
|
||||
power-domains:
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||||
items:
|
||||
- description: MMCX power domain
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required:
|
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- compatible
|
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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@ -37,28 +37,16 @@ properties:
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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@ -27,6 +27,7 @@ properties:
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- qcom,sm8350-dispcc
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clocks:
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minItems: 7
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items:
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- description: Board XO source
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- description: Byte clock from DSI PHY0
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@ -35,8 +36,15 @@ properties:
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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- description: Link clock from eDP PHY
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- description: VCO DIV clock from eDP PHY
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- description: Link clock from DP1 PHY
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- description: VCO DIV clock from DP1 PHY
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- description: Link clock from DP2 PHY
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- description: VCO DIV clock from DP2 PHY
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clock-names:
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minItems: 7
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items:
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- const: bi_tcxo
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- const: dsi0_phy_pll_out_byteclk
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@ -45,18 +53,12 @@ properties:
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- const: dsi1_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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- const: edp_phy_pll_link_clk
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- const: edp_phy_pll_vco_div_clk
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- const: dptx1_phy_pll_link_clk
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- const: dptx1_phy_pll_vco_div_clk
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- const: dptx2_phy_pll_link_clk
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- const: dptx2_phy_pll_vco_div_clk
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power-domains:
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description:
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@ -70,14 +72,26 @@ properties:
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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allOf:
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- $ref: qcom,gcc.yaml#
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- if:
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not:
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properties:
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compatible:
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contains:
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const: qcom,sc8180x-dispcc
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then:
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properties:
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clocks:
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maxItems: 7
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clock-names:
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maxItems: 7
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unevaluatedProperties: false
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examples:
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- |
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|
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@ -69,6 +69,8 @@ properties:
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const: 1
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deprecated: true
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'#power-domain-cells': false
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required:
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- compatible
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@ -81,7 +83,6 @@ examples:
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reg = <0x00900000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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thermal-sensor {
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compatible = "qcom,msm8960-tsens";
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|
|
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|||
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@ -51,6 +51,7 @@ properties:
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|||
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required:
|
||||
- compatible
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- '#power-domain-cells'
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||||
|
||||
unevaluatedProperties: false
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||||
|
||||
|
|
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|||
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@ -34,6 +34,8 @@ properties:
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- const: xo
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- const: sleep_clk
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'#power-domain-cells': false
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required:
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- compatible
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@ -45,7 +47,6 @@ examples:
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compatible = "qcom,gcc-ipq4019";
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reg = <0x1800000 0x60000>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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clocks = <&xo>, <&sleep_clk>;
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clock-names = "xo", "sleep_clk";
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|
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@ -36,6 +36,8 @@ properties:
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- const: xo
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- const: sleep_clk
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'#power-domain-cells': false
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|
||||
required:
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- compatible
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- clocks
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@ -51,7 +53,6 @@ examples:
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clocks = <&xo>, <&sleep_clk>;
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clock-names = "xo", "sleep_clk";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
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...
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@ -46,6 +46,8 @@ properties:
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allOf:
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- $ref: /schemas/thermal/qcom-tsens.yaml#
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'#power-domain-cells': false
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required:
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- compatible
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- clocks
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@ -65,7 +67,6 @@ examples:
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clock-names = "pxo", "cxo", "pll4";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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||||
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tsens: thermal-sensor {
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compatible = "qcom,ipq8064-tsens";
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||||
|
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|||
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@ -39,6 +39,7 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
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||||
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unevaluatedProperties: false
|
||||
|
||||
|
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|||
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@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
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title: Qualcomm Global Clock & Reset Controller
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@ -15,7 +15,6 @@ description: |
|
|||
domains.
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See also::
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include/dt-bindings/clock/qcom,gcc-msm8953.h
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include/dt-bindings/clock/qcom,gcc-mdm9607.h
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allOf:
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||||
|
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@ -28,6 +27,7 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
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||||
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unevaluatedProperties: false
|
||||
|
||||
|
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@ -0,0 +1,50 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
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title: Qualcomm Global Clock & Reset Controller
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
|
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains.
|
||||
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||||
See also::
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include/dt-bindings/clock/qcom,gcc-mdm9615.h
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||||
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allOf:
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||||
- $ref: qcom,gcc.yaml#
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||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-mdm9615
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|
||||
clocks:
|
||||
items:
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||||
- description: CXO clock
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||||
- description: PLL4 from LLC
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||||
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'#power-domain-cells': false
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||||
|
||||
required:
|
||||
- compatible
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||||
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unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
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||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-mdm9615";
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reg = <0x900000 0x4000>;
|
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#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&cxo_board>,
|
||||
<&lcc_pll4>;
|
||||
};
|
||||
...
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@ -34,6 +34,8 @@ properties:
|
|||
- const: pxo
|
||||
- const: cxo
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||||
|
||||
'#power-domain-cells': false
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||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
|
@ -47,7 +49,6 @@ examples:
|
|||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clocks = <&pxo_board>, <&cxo_board>;
|
||||
clock-names = "pxo", "cxo";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@ required:
|
|||
- clocks
|
||||
- clock-names
|
||||
- vdd_gfx-supply
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ required:
|
|||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -65,6 +65,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -35,7 +35,6 @@ required:
|
|||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
|
|
|
|||
|
|
@ -33,28 +33,16 @@ properties:
|
|||
- const: gcc_gpu_gpll0_clk
|
||||
- const: gcc_gpu_gpll0_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -56,25 +56,10 @@ properties:
|
|||
vdd-gfx-supply:
|
||||
description: Regulator supply for the VDD_GFX pads
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
# Require that power-domains and vdd-gfx-supply are not both present
|
||||
|
|
@ -83,7 +68,10 @@ not:
|
|||
- power-domains
|
||||
- vdd-gfx-supply
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -33,6 +33,8 @@ properties:
|
|||
- description: UNIPHY RX clock source
|
||||
- description: UNIPHY TX clk source
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
|
@ -58,6 +60,5 @@ examples:
|
|||
<&uniphy_tx_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ properties:
|
|||
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
|
||||
- description: USB PCIE wrapper pipe clock source
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
|
@ -47,7 +49,6 @@ examples:
|
|||
<&pcie_2lane_phy_pipe_clk_x1>,
|
||||
<&usb_pcie_wrapper_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -33,6 +33,8 @@ properties:
|
|||
- description: PCIE30 PHY3 pipe clock source
|
||||
- description: USB3 PHY pipe clock source
|
||||
|
||||
'#power-domain-cells': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
|
@ -57,6 +59,5 @@ examples:
|
|||
<&usb3phy_0_cc_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -29,28 +29,16 @@ properties:
|
|||
- const: xo
|
||||
- const: gpll0
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -0,0 +1,86 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Luo Jie <quic_luoj@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm NSS clock control module provides the clocks and resets
|
||||
on QCA8386(switch mode)/QCA8084(PHY mode)
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,qca8k-nsscc.h
|
||||
include/dt-bindings/reset/qcom,qca8k-nsscc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,qca8084-nsscc
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qca8082-nsscc
|
||||
- qcom,qca8085-nsscc
|
||||
- qcom,qca8384-nsscc
|
||||
- qcom,qca8385-nsscc
|
||||
- qcom,qca8386-nsscc
|
||||
- const: qcom,qca8084-nsscc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Chip reference clock source
|
||||
- description: UNIPHY0 RX 312P5M/125M clock source
|
||||
- description: UNIPHY0 TX 312P5M/125M clock source
|
||||
- description: UNIPHY1 RX 312P5M/125M clock source
|
||||
- description: UNIPHY1 TX 312P5M/125M clock source
|
||||
- description: UNIPHY1 RX 312P5M clock source
|
||||
- description: UNIPHY1 TX 312P5M clock source
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: MDIO bus address for Clock & Reset Controller register
|
||||
|
||||
reset-gpios:
|
||||
description: GPIO connected to the chip
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- reg
|
||||
- reset-gpios
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@18 {
|
||||
compatible = "qcom,qca8084-nsscc";
|
||||
reg = <0x18>;
|
||||
reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&pcs0_pll>,
|
||||
<&qca8k_uniphy0_rx>,
|
||||
<&qca8k_uniphy0_tx>,
|
||||
<&qca8k_uniphy1_rx>,
|
||||
<&qca8k_uniphy1_tx>,
|
||||
<&qca8k_uniphy1_rx312p5m>,
|
||||
<&qca8k_uniphy1_tx312p5m>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -37,28 +37,16 @@ properties:
|
|||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -0,0 +1,77 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller on QCM2290
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module provides the clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,qcm2290-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qcm2290-gpucc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AHB interface clock,
|
||||
- description: SoC CXO clock
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the CX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required CX performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@5990000 {
|
||||
compatible = "qcom,qcm2290-gpucc";
|
||||
reg = <0x0 0x05990000 0x0 0x9000>;
|
||||
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
|
||||
<&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
power-domains = <&rpmpd QCM2290_VDDCX>;
|
||||
required-opps = <&rpmpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -31,6 +31,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -37,28 +37,16 @@ properties:
|
|||
- const: dp_phy_pll_link_clk
|
||||
- const: dp_phy_pll_vco_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -41,28 +41,16 @@ properties:
|
|||
- const: edp_phy_pll_link_clk
|
||||
- const: edp_phy_pll_vco_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -46,28 +46,16 @@ properties:
|
|||
- const: dp_link_clk_divsel_ten
|
||||
- const: dp_vco_divided_clk_src_mux
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -28,27 +28,15 @@ properties:
|
|||
- description: Pixel clock from DSI PHY0
|
||||
- description: GPLL0 DISP DIV clock from GCC
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm7150-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on SM7150
|
||||
|
||||
maintainers:
|
||||
- Danila Tikhonov <danila@jiaxyga.com>
|
||||
- David Wronek <david@mainlining.org>
|
||||
- Jens Reidel <adrian@travitia.xyz>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SM7150.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm7150-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm7150-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board XO Active-Only source
|
||||
- description: Sleep clock source
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
CX power domain.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
clock-controller@ad00000 {
|
||||
compatible = "qcom,sm7150-camcc";
|
||||
reg = <0xad00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller for SM7150
|
||||
|
||||
maintainers:
|
||||
- Danila Tikhonov <danila@jiaxyga.com>
|
||||
- David Wronek <david@mainlining.org>
|
||||
- Jens Reidel <adrian@travitia.xyz>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM7150.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm7150-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board Always On XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: Sleep clock source
|
||||
- description: Byte clock from MDSS DSI PHY0
|
||||
- description: Pixel clock from MDSS DSI PHY0
|
||||
- description: Byte clock from MDSS DSI PHY1
|
||||
- description: Pixel clock from MDSS DSI PHY1
|
||||
- description: Link clock from DP PHY
|
||||
- description: VCO DIV clock from DP PHY
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
CX power domain.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm7150-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sm7150-dispcc";
|
||||
reg = <0x0af00000 0x200000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&sleep_clk>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi1_phy 0>,
|
||||
<&mdss_dsi1_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>;
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -30,6 +30,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -0,0 +1,58 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm7150-videocc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Video Clock & Reset Controller on SM7150
|
||||
|
||||
maintainers:
|
||||
- Danila Tikhonov <danila@jiaxyga.com>
|
||||
- David Wronek <david@mainlining.org>
|
||||
- Jens Reidel <adrian@travitia.xyz>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module provides the clocks, resets and power
|
||||
domains on SM7150.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,videocc-sm7150.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm7150-videocc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board Always On XO source
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
CX power domain.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
videocc: clock-controller@ab00000 {
|
||||
compatible = "qcom,sm7150-videocc";
|
||||
reg = <0x0ab00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>;
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -8,15 +8,17 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450
|
|||
|
||||
maintainers:
|
||||
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
|
||||
- Jagadeesh Kona <quic_jkona@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SM8450.
|
||||
|
||||
See also::
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8450-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-camcc.h
|
||||
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8650-camcc.h
|
||||
include/dt-bindings/clock/qcom,x1e80100-camcc.h
|
||||
|
||||
allOf:
|
||||
|
|
@ -28,6 +30,7 @@ properties:
|
|||
- qcom,sc8280xp-camcc
|
||||
- qcom,sm8450-camcc
|
||||
- qcom,sm8550-camcc
|
||||
- qcom,sm8650-camcc
|
||||
- qcom,x1e80100-camcc
|
||||
|
||||
clocks:
|
||||
|
|
|
|||
|
|
@ -40,18 +40,6 @@ properties:
|
|||
- description: Link clock from DP PHY3
|
||||
- description: VCO DIV clock from DP PHY3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
|
|
@ -64,13 +52,13 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -34,27 +34,15 @@ properties:
|
|||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -8,21 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450
|
|||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
- Jagadeesh Kona <quic_jkona@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module provides the clocks, resets and power
|
||||
domains on SM8450.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,sm8450-videocc.h
|
||||
include/dt-bindings/clock/qcom,sm8650-videocc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8450-videocc
|
||||
- qcom,sm8550-videocc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
- qcom,sm8650-videocc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
@ -39,26 +40,17 @@ properties:
|
|||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -45,18 +45,6 @@ properties:
|
|||
- description: Link clock from DP PHY3
|
||||
- description: VCO DIV clock from DP PHY3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
|
|
@ -69,13 +57,13 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -37,18 +37,6 @@ properties:
|
|||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
|
|
@ -61,14 +49,13 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -119,7 +106,7 @@ allOf:
|
|||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -7,9 +7,6 @@ config QCOM_GDSC
|
|||
bool
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
|
||||
config QCOM_RPMCC
|
||||
bool
|
||||
|
||||
menuconfig COMMON_CLK_QCOM
|
||||
tristate "Support for Qualcomm's clock controllers"
|
||||
depends on OF
|
||||
|
|
@ -65,6 +62,15 @@ config CLK_X1E80100_TCSRCC
|
|||
Support for the TCSR clock controller on X1E80100 devices.
|
||||
Say Y if you want to use peripheral devices such as SD/UFS.
|
||||
|
||||
config CLK_QCM2290_GPUCC
|
||||
tristate "QCM2290 Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCM_GCC_2290
|
||||
help
|
||||
Support for the graphics clock controller on QCM2290 devices.
|
||||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config QCOM_A53PLL
|
||||
tristate "MSM8916 A53 PLL"
|
||||
help
|
||||
|
|
@ -113,7 +119,6 @@ config QCOM_CLK_APCS_SDX55
|
|||
config QCOM_CLK_RPM
|
||||
tristate "RPM based Clock Controller"
|
||||
depends on MFD_QCOM_RPM
|
||||
select QCOM_RPMCC
|
||||
help
|
||||
The RPM (Resource Power Manager) is a dedicated hardware engine for
|
||||
managing the shared SoC resources in order to keep the lowest power
|
||||
|
|
@ -126,7 +131,6 @@ config QCOM_CLK_RPM
|
|||
config QCOM_CLK_SMD_RPM
|
||||
tristate "RPM over SMD based Clock Controller"
|
||||
depends on QCOM_SMD_RPM
|
||||
select QCOM_RPMCC
|
||||
help
|
||||
The RPM (Resource Power Manager) is a dedicated hardware engine for
|
||||
managing the shared SoC resources in order to keep the lowest power
|
||||
|
|
@ -249,6 +253,15 @@ config IPQ_GCC_9574
|
|||
i2c, USB, SD/eMMC, etc. Select this for the root clock
|
||||
of ipq9574.
|
||||
|
||||
config IPQ_NSSCC_QCA8K
|
||||
tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller"
|
||||
depends on MDIO_BUS
|
||||
help
|
||||
Support for NSS(Network SubSystem) clock controller on
|
||||
qca8386/qca8084 chip.
|
||||
Say Y or M if you want to use network features of switch or
|
||||
PHY device. Select this for the root clock of qca8k.
|
||||
|
||||
config MSM_GCC_8660
|
||||
tristate "MSM8660 Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
|
|
@ -803,6 +816,14 @@ config SM_CAMCC_6350
|
|||
Support for the camera clock controller on SM6350 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SM_CAMCC_7150
|
||||
tristate "SM7150 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_7150
|
||||
help
|
||||
Support for the camera clock controller on SM7150 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SM_CAMCC_8250
|
||||
tristate "SM8250 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
|
@ -827,6 +848,14 @@ config SM_CAMCC_8550
|
|||
Support for the camera clock controller on SM8550 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SM_CAMCC_8650
|
||||
tristate "SM8650 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8650
|
||||
help
|
||||
Support for the camera clock controller on SM8650 devices.
|
||||
Say Y if you want to support camera devices and camera functionality.
|
||||
|
||||
config SM_DISPCC_6115
|
||||
tristate "SM6115 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
|
@ -847,6 +876,16 @@ config SM_DISPCC_6125
|
|||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen
|
||||
|
||||
config SM_DISPCC_7150
|
||||
tristate "SM7150 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on SM_GCC_7150
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
SM7150 devices.
|
||||
Say Y if you want to support display devices and functionality such as
|
||||
splash screen.
|
||||
|
||||
config SM_DISPCC_8250
|
||||
tristate "SM8150/SM8250/SM8350 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
|
@ -953,6 +992,7 @@ config SM_GCC_6375
|
|||
|
||||
config SM_GCC_7150
|
||||
tristate "SM7150 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SM7150 devices.
|
||||
|
|
@ -1118,6 +1158,16 @@ config SM_TCSRCC_8650
|
|||
Support for the TCSR clock controller on SM8650 devices.
|
||||
Say Y if you want to use peripheral devices such as SD/UFS.
|
||||
|
||||
config SM_VIDEOCC_7150
|
||||
tristate "SM7150 Video Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_7150
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the video clock controller on SM7150 devices.
|
||||
Say Y if you want to support video devices and functionality such as
|
||||
video encode and decode.
|
||||
|
||||
config SM_VIDEOCC_8150
|
||||
tristate "SM8150 Video Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
|
|||
obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
|
||||
obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o
|
||||
obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o
|
||||
obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o
|
||||
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
|
||||
obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
|
||||
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
|
||||
|
|
@ -36,6 +37,7 @@ obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
|
|||
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
|
||||
obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
|
||||
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
|
||||
obj-$(CONFIG_IPQ_NSSCC_QCA8K) += nsscc-qca8k.o
|
||||
obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
|
||||
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
|
||||
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
|
||||
|
|
@ -106,13 +108,16 @@ obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
|
|||
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
|
||||
obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
|
||||
obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
|
||||
obj-$(CONFIG_SM_CAMCC_7150) += camcc-sm7150.o
|
||||
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
|
||||
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
|
||||
obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
|
||||
obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o
|
||||
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
|
||||
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
|
||||
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
|
||||
obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o
|
||||
obj-$(CONFIG_SM_DISPCC_7150) += dispcc-sm7150.o
|
||||
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
|
||||
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
|
||||
obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o
|
||||
|
|
@ -141,6 +146,7 @@ obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
|
|||
obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
|
||||
obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
|
||||
obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_7150) += videocc-sm7150.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o
|
||||
|
|
|
|||
|
|
@ -123,7 +123,7 @@ static int apss_ipq6018_probe(struct platform_device *pdev)
|
|||
if (!regmap)
|
||||
return -ENODEV;
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
|
||||
ret = qcom_cc_really_probe(&pdev->dev, &apss_ipq6018_desc, regmap);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -1680,7 +1680,7 @@ static int cam_cc_sc7180_probe(struct platform_device *pdev)
|
|||
clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
|
||||
clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &cam_cc_sc7180_desc, regmap);
|
||||
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7180_desc, regmap);
|
||||
pm_runtime_put(&pdev->dev);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to register CAM CC clocks\n");
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
|
|
@ -2247,6 +2248,9 @@ static struct clk_branch cam_cc_sleep_clk = {
|
|||
|
||||
static struct gdsc cam_cc_titan_top_gdsc = {
|
||||
.gdscr = 0xc194,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0xf,
|
||||
.pd = {
|
||||
.name = "cam_cc_titan_top_gdsc",
|
||||
},
|
||||
|
|
@ -2256,46 +2260,66 @@ static struct gdsc cam_cc_titan_top_gdsc = {
|
|||
|
||||
static struct gdsc cam_cc_bps_gdsc = {
|
||||
.gdscr = 0x7004,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0xf,
|
||||
.pd = {
|
||||
.name = "cam_cc_bps_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &cam_cc_titan_top_gdsc.pd,
|
||||
.flags = HW_CTRL | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc cam_cc_ife_0_gdsc = {
|
||||
.gdscr = 0xa004,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0xf,
|
||||
.pd = {
|
||||
.name = "cam_cc_ife_0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &cam_cc_titan_top_gdsc.pd,
|
||||
.flags = RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc cam_cc_ife_1_gdsc = {
|
||||
.gdscr = 0xb004,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0xf,
|
||||
.pd = {
|
||||
.name = "cam_cc_ife_1_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &cam_cc_titan_top_gdsc.pd,
|
||||
.flags = RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc cam_cc_ife_2_gdsc = {
|
||||
.gdscr = 0xb070,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0xf,
|
||||
.pd = {
|
||||
.name = "cam_cc_ife_2_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &cam_cc_titan_top_gdsc.pd,
|
||||
.flags = RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc cam_cc_ipe_0_gdsc = {
|
||||
.gdscr = 0x8004,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0xf,
|
||||
.pd = {
|
||||
.name = "cam_cc_ipe_0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &cam_cc_titan_top_gdsc.pd,
|
||||
.flags = HW_CTRL | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
|
|
@ -2457,7 +2481,7 @@ static int cam_cc_sc7280_probe(struct platform_device *pdev)
|
|||
clk_lucid_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
|
||||
clk_lucid_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &cam_cc_sc7280_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7280_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver cam_cc_sc7280_driver = {
|
||||
|
|
|
|||
|
|
@ -45,11 +45,11 @@ enum {
|
|||
P_SLEEP_CLK,
|
||||
};
|
||||
|
||||
static struct pll_vco lucid_vco[] = {
|
||||
static const struct pll_vco lucid_vco[] = {
|
||||
{ 249600000, 1800000000, 0 },
|
||||
};
|
||||
|
||||
static struct pll_vco zonda_vco[] = {
|
||||
static const struct pll_vco zonda_vco[] = {
|
||||
{ 595200000, 3600000000, 0 },
|
||||
};
|
||||
|
||||
|
|
@ -3034,7 +3034,7 @@ static int camcc_sc8280xp_probe(struct platform_device *pdev)
|
|||
/* Keep some clocks always-on */
|
||||
qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &camcc_sc8280xp_desc, regmap);
|
||||
ret = qcom_cc_really_probe(&pdev->dev, &camcc_sc8280xp_desc, regmap);
|
||||
if (ret)
|
||||
goto err_disable;
|
||||
|
||||
|
|
|
|||
|
|
@ -1735,7 +1735,7 @@ static int cam_cc_sdm845_probe(struct platform_device *pdev)
|
|||
cam_cc_pll_config.l = 0x14;
|
||||
clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &cam_cc_sdm845_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &cam_cc_sdm845_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver cam_cc_sdm845_driver = {
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ enum {
|
|||
P_CAMCC_PLL3_OUT_MAIN,
|
||||
};
|
||||
|
||||
static struct pll_vco fabia_vco[] = {
|
||||
static const struct pll_vco fabia_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
|
|
@ -1879,7 +1879,7 @@ static int camcc_sm6350_probe(struct platform_device *pdev)
|
|||
clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config);
|
||||
clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &camcc_sm6350_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &camcc_sm6350_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver camcc_sm6350_driver = {
|
||||
|
|
|
|||
2061
drivers/clk/qcom/camcc-sm7150.c
Normal file
2061
drivers/clk/qcom/camcc-sm7150.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -32,11 +32,11 @@ enum {
|
|||
P_SLEEP_CLK,
|
||||
};
|
||||
|
||||
static struct pll_vco lucid_vco[] = {
|
||||
static const struct pll_vco lucid_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
static struct pll_vco zonda_vco[] = {
|
||||
static const struct pll_vco zonda_vco[] = {
|
||||
{ 595200000UL, 3600000000UL, 0 },
|
||||
};
|
||||
|
||||
|
|
@ -2433,7 +2433,7 @@ static int cam_cc_sm8250_probe(struct platform_device *pdev)
|
|||
clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
|
||||
clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8250_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver cam_cc_sm8250_driver = {
|
||||
|
|
|
|||
|
|
@ -2839,7 +2839,7 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev)
|
|||
clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
|
||||
clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &cam_cc_sm8450_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver cam_cc_sm8450_driver = {
|
||||
|
|
|
|||
|
|
@ -3540,7 +3540,7 @@ static int cam_cc_sm8550_probe(struct platform_device *pdev)
|
|||
qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */
|
||||
qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap);
|
||||
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8550_desc, regmap);
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
|
|
|
|||
3591
drivers/clk/qcom/camcc-sm8650.c
Normal file
3591
drivers/clk/qcom/camcc-sm8650.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -2466,7 +2466,7 @@ static int cam_cc_x1e80100_probe(struct platform_device *pdev)
|
|||
qcom_branch_set_clk_en(regmap, 0x13a9c); /* CAM_CC_GDSC_CLK */
|
||||
qcom_branch_set_clk_en(regmap, 0x13ab8); /* CAM_CC_SLEEP_CLK */
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &cam_cc_x1e80100_desc, regmap);
|
||||
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_x1e80100_desc, regmap);
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -93,6 +93,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
|
|||
[PLL_OFF_TEST_CTL] = 0x30,
|
||||
[PLL_OFF_TEST_CTL_U] = 0x34,
|
||||
},
|
||||
[CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = {
|
||||
[PLL_OFF_L_VAL] = 0x04,
|
||||
[PLL_OFF_ALPHA_VAL] = 0x08,
|
||||
[PLL_OFF_USER_CTL] = 0x0c,
|
||||
[PLL_OFF_CONFIG_CTL] = 0x10,
|
||||
[PLL_OFF_CONFIG_CTL_U] = 0x14,
|
||||
[PLL_OFF_CONFIG_CTL_U1] = 0x18,
|
||||
[PLL_OFF_TEST_CTL] = 0x1c,
|
||||
[PLL_OFF_TEST_CTL_U] = 0x20,
|
||||
[PLL_OFF_TEST_CTL_U1] = 0x24,
|
||||
[PLL_OFF_OPMODE] = 0x28,
|
||||
[PLL_OFF_STATUS] = 0x38,
|
||||
},
|
||||
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
|
||||
[PLL_OFF_L_VAL] = 0x04,
|
||||
[PLL_OFF_ALPHA_VAL] = 0x08,
|
||||
|
|
@ -788,6 +801,40 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return clamp(rate, min_freq, max_freq);
|
||||
}
|
||||
|
||||
void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
|
||||
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
|
||||
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
|
||||
|
||||
/* Set PLL_BYPASSNL */
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
|
||||
regmap_read(regmap, PLL_MODE(pll), &val);
|
||||
|
||||
/* Wait 5 us between setting BYPASS and deasserting reset */
|
||||
udelay(5);
|
||||
|
||||
/* Take PLL out from reset state */
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
|
||||
regmap_read(regmap, PLL_MODE(pll), &val);
|
||||
|
||||
/* Wait 50us for PLL_LOCK_DET bit to go high */
|
||||
usleep_range(50, 55);
|
||||
|
||||
/* Enable PLL output */
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure);
|
||||
|
||||
static unsigned long
|
||||
alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ enum {
|
|||
CLK_ALPHA_PLL_TYPE_DEFAULT,
|
||||
CLK_ALPHA_PLL_TYPE_HUAYRA,
|
||||
CLK_ALPHA_PLL_TYPE_HUAYRA_APSS,
|
||||
CLK_ALPHA_PLL_TYPE_HUAYRA_2290,
|
||||
CLK_ALPHA_PLL_TYPE_BRAMMO,
|
||||
CLK_ALPHA_PLL_TYPE_FABIA,
|
||||
CLK_ALPHA_PLL_TYPE_TRION,
|
||||
|
|
@ -194,6 +195,8 @@ extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
|
|||
|
||||
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
|
|
|
|||
|
|
@ -191,3 +191,10 @@ const struct clk_ops clk_branch_simple_ops = {
|
|||
.is_enabled = clk_is_enabled_regmap,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_branch_simple_ops);
|
||||
|
||||
const struct clk_ops clk_branch2_prepare_ops = {
|
||||
.prepare = clk_branch2_enable,
|
||||
.unprepare = clk_branch2_disable,
|
||||
.is_prepared = clk_is_enabled_regmap,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_branch2_prepare_ops);
|
||||
|
|
|
|||
|
|
@ -109,6 +109,7 @@ extern const struct clk_ops clk_branch2_ops;
|
|||
extern const struct clk_ops clk_branch_simple_ops;
|
||||
extern const struct clk_ops clk_branch2_aon_ops;
|
||||
extern const struct clk_ops clk_branch2_mem_ops;
|
||||
extern const struct clk_ops clk_branch2_prepare_ops;
|
||||
|
||||
#define to_clk_branch(_hw) \
|
||||
container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
|
||||
|
|
|
|||
|
|
@ -252,11 +252,10 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
|
|||
return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
|
||||
}
|
||||
|
||||
int qcom_cc_really_probe(struct platform_device *pdev,
|
||||
int qcom_cc_really_probe(struct device *dev,
|
||||
const struct qcom_cc_desc *desc, struct regmap *regmap)
|
||||
{
|
||||
int i, ret;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct qcom_reset_controller *reset;
|
||||
struct qcom_cc *cc;
|
||||
struct gdsc_desc *scd;
|
||||
|
|
@ -333,7 +332,7 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
|
|||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
return qcom_cc_really_probe(pdev, desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, desc, regmap);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_cc_probe);
|
||||
|
||||
|
|
@ -351,8 +350,9 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
|
|||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
return qcom_cc_really_probe(pdev, desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, desc, regmap);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("QTI Common Clock module");
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ extern int qcom_cc_register_sleep_clk(struct device *dev);
|
|||
|
||||
extern struct regmap *qcom_cc_map(struct platform_device *pdev,
|
||||
const struct qcom_cc_desc *desc);
|
||||
extern int qcom_cc_really_probe(struct platform_device *pdev,
|
||||
extern int qcom_cc_really_probe(struct device *dev,
|
||||
const struct qcom_cc_desc *desc,
|
||||
struct regmap *regmap);
|
||||
extern int qcom_cc_probe(struct platform_device *pdev,
|
||||
|
|
|
|||
|
|
@ -522,7 +522,7 @@ static int disp_cc_qcm2290_probe(struct platform_device *pdev)
|
|||
/* Keep some clocks always-on */
|
||||
qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap);
|
||||
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_qcm2290_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -713,7 +713,7 @@ static int disp_cc_sc7180_probe(struct platform_device *pdev)
|
|||
|
||||
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7180_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_sc7180_driver = {
|
||||
|
|
|
|||
|
|
@ -881,7 +881,7 @@ static int disp_cc_sc7280_probe(struct platform_device *pdev)
|
|||
/* Keep some clocks always-on */
|
||||
qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */
|
||||
|
||||
return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7280_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_sc7280_driver = {
|
||||
|
|
|
|||
|
|
@ -3172,7 +3172,7 @@ static int disp_cc_sc8280xp_probe(struct platform_device *pdev)
|
|||
clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL1]), regmap, &disp_cc_pll1_config);
|
||||
clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config);
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, desc, regmap);
|
||||
ret = qcom_cc_really_probe(&pdev->dev, desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register display clock controller\n");
|
||||
goto out_pm_runtime_put;
|
||||
|
|
|
|||
|
|
@ -863,7 +863,7 @@ static int disp_cc_sdm845_probe(struct platform_device *pdev)
|
|||
/* Enable hardware clock gating for DSI and MDP clocks */
|
||||
regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &disp_cc_sdm845_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_sdm845_driver = {
|
||||
|
|
|
|||
|
|
@ -586,7 +586,7 @@ static int disp_cc_sm6115_probe(struct platform_device *pdev)
|
|||
/* Keep some clocks always-on */
|
||||
qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap);
|
||||
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6115_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ enum {
|
|||
P_GPLL0_OUT_MAIN,
|
||||
};
|
||||
|
||||
static struct pll_vco disp_cc_pll_vco[] = {
|
||||
static const struct pll_vco disp_cc_pll_vco[] = {
|
||||
{ 500000000, 1000000000, 2 },
|
||||
};
|
||||
|
||||
|
|
@ -682,7 +682,7 @@ static int disp_cc_sm6125_probe(struct platform_device *pdev)
|
|||
|
||||
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &disp_cc_sm6125_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6125_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_sm6125_driver = {
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ enum {
|
|||
P_GCC_DISP_GPLL0_CLK,
|
||||
};
|
||||
|
||||
static struct pll_vco fabia_vco[] = {
|
||||
static const struct pll_vco fabia_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
|
|
@ -761,7 +761,7 @@ static int disp_cc_sm6350_probe(struct platform_device *pdev)
|
|||
|
||||
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &disp_cc_sm6350_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6350_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_sm6350_driver = {
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ enum {
|
|||
P_GCC_DISP_GPLL0_CLK,
|
||||
};
|
||||
|
||||
static struct pll_vco lucid_vco[] = {
|
||||
static const struct pll_vco lucid_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
|
|
@ -583,7 +583,7 @@ static int disp_cc_sm6375_probe(struct platform_device *pdev)
|
|||
|
||||
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &disp_cc_sm6375_desc, regmap);
|
||||
return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6375_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver disp_cc_sm6375_driver = {
|
||||
|
|
|
|||
1006
drivers/clk/qcom/dispcc-sm7150.c
Normal file
1006
drivers/clk/qcom/dispcc-sm7150.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -1366,7 +1366,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
|
|||
/* Keep some clocks always-on */
|
||||
qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap);
|
||||
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8250_desc, regmap);
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user