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net: pcs: xpcs-plat: fix clock lifecycle for !CONFIG_PM builds

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With CONFIG_PM disabled, pm_runtime_enable() and the runtime resume path
are compiled out, so the CSR clock is never prepared/enabled. On
platforms that provide a real "csr" clock this makes register access
fail.

Handle this by preparing/enabling the CSR clock manually in the !PM case
and disabling it in the devm cleanup action. The CONFIG_PM path is left
unchanged and still relies on runtime PM to gate the clock.

Use RUNTIME_PM_OPS() and pm_ptr() for the PM ops as well, so that in
!CONFIG_PM builds the runtime callbacks are still referenced and .pm is
NULL rather than pointing at an empty ops structure. This also drops the
__maybe_unused annotations from the callbacks, which were only needed
because SET_RUNTIME_PM_OPS() expands to nothing when CONFIG_PM is
disabled. Both changes are no-ops when CONFIG_PM is enabled.

The CSR clock is optional (devm_clk_get_optional()), so platforms
without a clock keep working in both cases, and clk_prepare_enable()
on a NULL clock is a no-op. Because the !PM case is handled in the
driver, there is no need to select or depend on PM in Kconfig for all
platforms; keep the current Kconfig as-is to preserve compile coverage.

Signed-off-by: Coia Prant <coiaprant@gmail.com>
Link: https://patch.msgid.link/20261023075214.1793922-4-coiaprant@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Coia Prant 2026-10-23 15:52:13 +08:00 committed by Jakub Kicinski
parent 49d8bbc212
commit eea365ed28
1 changed files with 40 additions and 6 deletions
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46
drivers/net/pcs/pcs-xpcs-plat.c
View File

@ -275,6 +275,7 @@ static int xpcs_plat_init_res(struct dw_xpcs_plat *pxpcs)
return 0;
}
#ifdef CONFIG_PM
static void xpcs_plat_exit_clk(void *data)
{
struct dw_xpcs_plat *pxpcs = data;
@ -304,6 +305,39 @@ static int xpcs_plat_init_clk(struct dw_xpcs_plat *pxpcs)
return 0;
}
#else
static void xpcs_plat_exit_clk(void *data)
{
struct dw_xpcs_plat *pxpcs = data;
clk_disable_unprepare(pxpcs->cclk);
}
static int xpcs_plat_init_clk(struct dw_xpcs_plat *pxpcs)
{
struct device *dev = &pxpcs->pdev->dev;
int ret;
pxpcs->cclk = devm_clk_get_optional(dev, "csr");
if (IS_ERR(pxpcs->cclk))
return dev_err_probe(dev, PTR_ERR(pxpcs->cclk),
"Failed to get CSR clock\n");
ret = clk_prepare_enable(pxpcs->cclk);
if (ret) {
dev_err(dev, "Failed to enable CSR clock: %d\n", ret);
return ret;
}
ret = devm_add_action_or_reset(dev, xpcs_plat_exit_clk, pxpcs);
if (ret) {
dev_err(dev, "Failed to register devm for xpcs_plat_exit_clk: %d\n", ret);
return ret;
}
return 0;
}
#endif
static int xpcs_plat_init_bus(struct dw_xpcs_plat *pxpcs)
{
@ -408,7 +442,7 @@ static int xpcs_plat_probe(struct platform_device *pdev)
return 0;
}
static int __maybe_unused xpcs_plat_pm_runtime_suspend(struct device *dev)
static int xpcs_plat_pm_runtime_suspend(struct device *dev)
{
struct dw_xpcs_plat *pxpcs = dev_get_drvdata(dev);
@ -417,7 +451,7 @@ static int __maybe_unused xpcs_plat_pm_runtime_suspend(struct device *dev)
return 0;
}
static int __maybe_unused xpcs_plat_pm_runtime_resume(struct device *dev)
static int xpcs_plat_pm_runtime_resume(struct device *dev)
{
struct dw_xpcs_plat *pxpcs = dev_get_drvdata(dev);
@ -425,9 +459,9 @@ static int __maybe_unused xpcs_plat_pm_runtime_resume(struct device *dev)
}
static const struct dev_pm_ops xpcs_plat_pm_ops = {
SET_RUNTIME_PM_OPS(xpcs_plat_pm_runtime_suspend,
xpcs_plat_pm_runtime_resume,
NULL)
RUNTIME_PM_OPS(xpcs_plat_pm_runtime_suspend,
xpcs_plat_pm_runtime_resume,
NULL)
};
DW_XPCS_INFO_DECLARE(xpcs_generic, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_ID_NATIVE);
@ -456,7 +490,7 @@ static struct platform_driver xpcs_plat_driver = {
.probe = xpcs_plat_probe,
.driver = {
.name = "dwxpcs",
.pm = &xpcs_plat_pm_ops,
.pm = pm_ptr(&xpcs_plat_pm_ops),
.of_match_table = xpcs_of_ids,
},
};