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Merge branch 'convert-the-micrel-bindings-to-dt-schema'
Stefan Eichenberger says: ==================== Convert the Micrel bindings to DT schema Convert the device tree bindings for the Micrel PHYs and switches to DT schema. ==================== Link: https://patch.msgid.link/20260116130948.79558-1-eichest@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
ee7be82f8c
253
Documentation/devicetree/bindings/net/micrel,gigabit.yaml
Normal file
253
Documentation/devicetree/bindings/net/micrel,gigabit.yaml
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|
@ -0,0 +1,253 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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||||
%YAML 1.2
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---
|
||||
$id: http://devicetree.org/schemas/net/micrel,gigabit.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Micrel series Gigabit Ethernet PHYs
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Stefan Eichenberger <eichest@gmail.com>
|
||||
|
||||
description:
|
||||
Some boards require special skew tuning values, particularly when it comes
|
||||
to clock delays. These values can be specified in the device tree using
|
||||
the properties listed here.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ethernet-phy-id0022.1610 # KSZ9021
|
||||
- ethernet-phy-id0022.1611 # KSZ9021RLRN
|
||||
- ethernet-phy-id0022.1620 # KSZ9031
|
||||
- ethernet-phy-id0022.1631 # KSZ9477
|
||||
- ethernet-phy-id0022.1640 # KSZ9131
|
||||
- ethernet-phy-id0022.1650 # LAN8841
|
||||
- ethernet-phy-id0022.1660 # LAN8814
|
||||
- ethernet-phy-id0022.1670 # LAN8804
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||||
|
||||
micrel,force-master:
|
||||
type: boolean
|
||||
description: |
|
||||
Force phy to master mode. Only set this option if the phy reference
|
||||
clock provided at CLK125_NDO pin is used as MAC reference clock
|
||||
because the clock jitter in slave mode is too high (errata#2).
|
||||
Attention: The link partner must be configurable as slave otherwise
|
||||
no link will be established.
|
||||
|
||||
coma-mode-gpios:
|
||||
maxItems: 1
|
||||
description: |
|
||||
If present the given gpio will be deasserted when the PHY is probed.
|
||||
|
||||
Some PHYs have a COMA mode input pin which puts the PHY into
|
||||
isolate and power-down mode. On some boards this input is connected
|
||||
to a GPIO of the SoC.
|
||||
|
||||
micrel,led-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
LED mode value to set for PHYs with configurable LEDs.
|
||||
|
||||
Configure the LED mode with single value. The list of PHYs and the
|
||||
bits that are currently supported:
|
||||
|
||||
LAN8814: register EP5.0, bit 6
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|
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See the respective PHY datasheet for the mode values.
|
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minimum: 0
|
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maximum: 1
|
||||
|
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patternProperties:
|
||||
'^([rt]xc)-skew-psec$':
|
||||
$ref: /schemas/types.yaml#/definitions/int32
|
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description:
|
||||
Skew control of the pad in picoseconds.
|
||||
minimum: -700
|
||||
maximum: 2400
|
||||
multipleOf: 100
|
||||
default: 0
|
||||
|
||||
'^([rt]xd[0-3]|rxdv|txen)-skew-psec$':
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$ref: /schemas/types.yaml#/definitions/int32
|
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description: |
|
||||
Skew control of the pad in picoseconds.
|
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minimum: -700
|
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maximum: 800
|
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multipleOf: 100
|
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default: 0
|
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|
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allOf:
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- $ref: ethernet-phy.yaml#
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- if:
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||||
properties:
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compatible:
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contains:
|
||||
enum:
|
||||
- ethernet-phy-id0022.1610
|
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- ethernet-phy-id0022.1611
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then:
|
||||
patternProperties:
|
||||
'^([rt]xd[0-3]|[rt]xc|rxdv|txen)-skew-ps$':
|
||||
description: |
|
||||
Skew control of the pad in picoseconds.
|
||||
The actual increment on the chip is 120ps ranging from -840ps to
|
||||
960ps, this mismatch comes from a documentation error before
|
||||
datasheet revision 1.2 (Feb 2014).
|
||||
|
||||
The device tree value to delay mapping looks as follows:
|
||||
Device Tree Value Delay
|
||||
--------------------------
|
||||
0 -840ps
|
||||
200 -720ps
|
||||
400 -600ps
|
||||
600 -480ps
|
||||
800 -360ps
|
||||
1000 -240ps
|
||||
1200 -120ps
|
||||
1400 0ps
|
||||
1600 120ps
|
||||
1800 240ps
|
||||
2000 360ps
|
||||
2200 480ps
|
||||
2400 600ps
|
||||
2600 720ps
|
||||
2800 840ps
|
||||
3000 960ps
|
||||
minimum: 0
|
||||
maximum: 3000
|
||||
multipleOf: 200
|
||||
default: 1400
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ethernet-phy-id0022.1620
|
||||
then:
|
||||
patternProperties:
|
||||
'^([rt]xc)-skew-ps$':
|
||||
description: |
|
||||
Skew control of the pad in picoseconds.
|
||||
|
||||
The device tree value to delay mapping is as follows:
|
||||
Device Tree Value Delay
|
||||
--------------------------
|
||||
0 -900ps
|
||||
60 -840ps
|
||||
120 -780ps
|
||||
180 -720ps
|
||||
240 -660ps
|
||||
300 -600ps
|
||||
360 -540ps
|
||||
420 -480ps
|
||||
480 -420ps
|
||||
540 -360ps
|
||||
600 -300ps
|
||||
660 -240ps
|
||||
720 -180ps
|
||||
780 -120ps
|
||||
840 -60ps
|
||||
900 0ps
|
||||
960 60ps
|
||||
1020 120ps
|
||||
1080 180ps
|
||||
1140 240ps
|
||||
1200 300ps
|
||||
1260 360ps
|
||||
1320 420ps
|
||||
1380 480ps
|
||||
1440 540ps
|
||||
1500 600ps
|
||||
1560 660ps
|
||||
1620 720ps
|
||||
1680 780ps
|
||||
1740 840ps
|
||||
1800 900ps
|
||||
1860 960ps
|
||||
minimum: 0
|
||||
maximum: 1860
|
||||
multipleOf: 60
|
||||
default: 900
|
||||
'^([rt]xd[0-3]|rxdv|txen)-skew-ps$':
|
||||
description: |
|
||||
Skew control of the pad in picoseconds.
|
||||
|
||||
The device tree value to delay mapping is as follows:
|
||||
Device Tree Value Delay
|
||||
--------------------------
|
||||
0 -420ps
|
||||
60 -360ps
|
||||
120 -300ps
|
||||
180 -240ps
|
||||
240 -180ps
|
||||
300 -120ps
|
||||
360 -60ps
|
||||
420 0ps
|
||||
480 60ps
|
||||
540 120ps
|
||||
600 180ps
|
||||
660 240ps
|
||||
720 300ps
|
||||
780 360ps
|
||||
840 420ps
|
||||
900 480ps
|
||||
minimum: 0
|
||||
maximum: 900
|
||||
multipleOf: 60
|
||||
default: 420
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- ethernet-phy-id0022.1640
|
||||
- ethernet-phy-id0022.1650
|
||||
then:
|
||||
patternProperties:
|
||||
'^([rt]xd[0-3]|[rt]xc|rxdv|txen)-skew-psec$': false
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ethernet-phy-id0022.1620
|
||||
then:
|
||||
properties:
|
||||
micrel,force-master: false
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ethernet-phy-id0022.1660
|
||||
then:
|
||||
properties:
|
||||
coma-mode-gpios: false
|
||||
micrel,led-mode: false
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethernet-phy@7 {
|
||||
compatible = "ethernet-phy-id0022.1610";
|
||||
reg = <7>;
|
||||
rxc-skew-ps = <3000>;
|
||||
rxdv-skew-ps = <0>;
|
||||
txc-skew-ps = <3000>;
|
||||
txen-skew-ps = <0>;
|
||||
};
|
||||
|
||||
ethernet-phy@9 {
|
||||
compatible = "ethernet-phy-id0022.1640";
|
||||
reg = <9>;
|
||||
rxc-skew-psec = <(-100)>;
|
||||
txc-skew-psec = <(-100)>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,228 +0,0 @@
|
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Micrel KSZ9021/KSZ9031/KSZ9131 Gigabit Ethernet PHY
|
||||
|
||||
Some boards require special tuning values, particularly when it comes
|
||||
to clock delays. You can specify clock delay values in the PHY OF
|
||||
device node. Deprecated, but still supported, these properties can
|
||||
also be added to an Ethernet OF device node.
|
||||
|
||||
Note that these settings are applied after any phy-specific fixup from
|
||||
phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c),
|
||||
and therefore may overwrite them.
|
||||
|
||||
KSZ9021:
|
||||
|
||||
All skew control options are specified in picoseconds. The minimum
|
||||
value is 0, the maximum value is 3000, and it can be specified in 200ps
|
||||
steps, *but* these values are in no way what you get because this chip's
|
||||
skew values actually increase in 120ps steps, starting from -840ps. The
|
||||
incorrect values came from an error in the original KSZ9021 datasheet
|
||||
before it was corrected in revision 1.2 (Feb 2014), but it is too late to
|
||||
change the driver now because of the many existing device trees that have
|
||||
been created using values that go up in increments of 200.
|
||||
|
||||
The following table shows the actual skew delay you will get for each of the
|
||||
possible devicetree values, and the number that will be programmed into the
|
||||
corresponding pad skew register:
|
||||
|
||||
Device Tree Value Delay Pad Skew Register Value
|
||||
-----------------------------------------------------
|
||||
0 -840ps 0000
|
||||
200 -720ps 0001
|
||||
400 -600ps 0010
|
||||
600 -480ps 0011
|
||||
800 -360ps 0100
|
||||
1000 -240ps 0101
|
||||
1200 -120ps 0110
|
||||
1400 0ps 0111
|
||||
1600 120ps 1000
|
||||
1800 240ps 1001
|
||||
2000 360ps 1010
|
||||
2200 480ps 1011
|
||||
2400 600ps 1100
|
||||
2600 720ps 1101
|
||||
2800 840ps 1110
|
||||
3000 960ps 1111
|
||||
|
||||
Optional properties:
|
||||
|
||||
- rxc-skew-ps : Skew control of RXC pad
|
||||
- rxdv-skew-ps : Skew control of RX CTL pad
|
||||
- txc-skew-ps : Skew control of TXC pad
|
||||
- txen-skew-ps : Skew control of TX CTL pad
|
||||
- rxd0-skew-ps : Skew control of RX data 0 pad
|
||||
- rxd1-skew-ps : Skew control of RX data 1 pad
|
||||
- rxd2-skew-ps : Skew control of RX data 2 pad
|
||||
- rxd3-skew-ps : Skew control of RX data 3 pad
|
||||
- txd0-skew-ps : Skew control of TX data 0 pad
|
||||
- txd1-skew-ps : Skew control of TX data 1 pad
|
||||
- txd2-skew-ps : Skew control of TX data 2 pad
|
||||
- txd3-skew-ps : Skew control of TX data 3 pad
|
||||
|
||||
KSZ9031:
|
||||
|
||||
All skew control options are specified in picoseconds. The minimum
|
||||
value is 0, and the maximum is property-dependent. The increment
|
||||
step is 60ps. The default value is the neutral setting, so setting
|
||||
rxc-skew-ps=<0> actually results in -900 picoseconds adjustment.
|
||||
|
||||
The KSZ9031 hardware supports a range of skew values from negative to
|
||||
positive, where the specific range is property dependent. All values
|
||||
specified in the devicetree are offset by the minimum value so they
|
||||
can be represented as positive integers in the devicetree since it's
|
||||
difficult to represent a negative number in the devictree.
|
||||
|
||||
The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps.
|
||||
|
||||
Pad Skew Value Delay (ps) Devicetree Value
|
||||
------------------------------------------------------
|
||||
0_0000 -900ps 0
|
||||
0_0001 -840ps 60
|
||||
0_0010 -780ps 120
|
||||
0_0011 -720ps 180
|
||||
0_0100 -660ps 240
|
||||
0_0101 -600ps 300
|
||||
0_0110 -540ps 360
|
||||
0_0111 -480ps 420
|
||||
0_1000 -420ps 480
|
||||
0_1001 -360ps 540
|
||||
0_1010 -300ps 600
|
||||
0_1011 -240ps 660
|
||||
0_1100 -180ps 720
|
||||
0_1101 -120ps 780
|
||||
0_1110 -60ps 840
|
||||
0_1111 0ps 900
|
||||
1_0000 60ps 960
|
||||
1_0001 120ps 1020
|
||||
1_0010 180ps 1080
|
||||
1_0011 240ps 1140
|
||||
1_0100 300ps 1200
|
||||
1_0101 360ps 1260
|
||||
1_0110 420ps 1320
|
||||
1_0111 480ps 1380
|
||||
1_1000 540ps 1440
|
||||
1_1001 600ps 1500
|
||||
1_1010 660ps 1560
|
||||
1_1011 720ps 1620
|
||||
1_1100 780ps 1680
|
||||
1_1101 840ps 1740
|
||||
1_1110 900ps 1800
|
||||
1_1111 960ps 1860
|
||||
|
||||
The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps
|
||||
data pads, and the rxdv-skew-ps, txen-skew-ps control pads.
|
||||
|
||||
Pad Skew Value Delay (ps) Devicetree Value
|
||||
------------------------------------------------------
|
||||
0000 -420ps 0
|
||||
0001 -360ps 60
|
||||
0010 -300ps 120
|
||||
0011 -240ps 180
|
||||
0100 -180ps 240
|
||||
0101 -120ps 300
|
||||
0110 -60ps 360
|
||||
0111 0ps 420
|
||||
1000 60ps 480
|
||||
1001 120ps 540
|
||||
1010 180ps 600
|
||||
1011 240ps 660
|
||||
1100 300ps 720
|
||||
1101 360ps 780
|
||||
1110 420ps 840
|
||||
1111 480ps 900
|
||||
|
||||
Optional properties:
|
||||
|
||||
Maximum value of 1860, default value 900:
|
||||
|
||||
- rxc-skew-ps : Skew control of RX clock pad
|
||||
- txc-skew-ps : Skew control of TX clock pad
|
||||
|
||||
Maximum value of 900, default value 420:
|
||||
|
||||
- rxdv-skew-ps : Skew control of RX CTL pad
|
||||
- txen-skew-ps : Skew control of TX CTL pad
|
||||
- rxd0-skew-ps : Skew control of RX data 0 pad
|
||||
- rxd1-skew-ps : Skew control of RX data 1 pad
|
||||
- rxd2-skew-ps : Skew control of RX data 2 pad
|
||||
- rxd3-skew-ps : Skew control of RX data 3 pad
|
||||
- txd0-skew-ps : Skew control of TX data 0 pad
|
||||
- txd1-skew-ps : Skew control of TX data 1 pad
|
||||
- txd2-skew-ps : Skew control of TX data 2 pad
|
||||
- txd3-skew-ps : Skew control of TX data 3 pad
|
||||
|
||||
- micrel,force-master:
|
||||
Boolean, force phy to master mode. Only set this option if the phy
|
||||
reference clock provided at CLK125_NDO pin is used as MAC reference
|
||||
clock because the clock jitter in slave mode is too high (errata#2).
|
||||
Attention: The link partner must be configurable as slave otherwise
|
||||
no link will be established.
|
||||
|
||||
KSZ9131:
|
||||
LAN8841:
|
||||
|
||||
All skew control options are specified in picoseconds. The increment
|
||||
step is 100ps. Unlike KSZ9031, the values represent picoseccond delays.
|
||||
A negative value can be assigned as rxc-skew-psec = <(-100)>;.
|
||||
|
||||
Optional properties:
|
||||
|
||||
Range of the value -700 to 2400, default value 0:
|
||||
|
||||
- rxc-skew-psec : Skew control of RX clock pad
|
||||
- txc-skew-psec : Skew control of TX clock pad
|
||||
|
||||
Range of the value -700 to 800, default value 0:
|
||||
|
||||
- rxdv-skew-psec : Skew control of RX CTL pad
|
||||
- txen-skew-psec : Skew control of TX CTL pad
|
||||
- rxd0-skew-psec : Skew control of RX data 0 pad
|
||||
- rxd1-skew-psec : Skew control of RX data 1 pad
|
||||
- rxd2-skew-psec : Skew control of RX data 2 pad
|
||||
- rxd3-skew-psec : Skew control of RX data 3 pad
|
||||
- txd0-skew-psec : Skew control of TX data 0 pad
|
||||
- txd1-skew-psec : Skew control of TX data 1 pad
|
||||
- txd2-skew-psec : Skew control of TX data 2 pad
|
||||
- txd3-skew-psec : Skew control of TX data 3 pad
|
||||
|
||||
Examples:
|
||||
|
||||
/* Attach to an Ethernet device with autodetected PHY */
|
||||
&enet {
|
||||
rxc-skew-ps = <1800>;
|
||||
rxdv-skew-ps = <0>;
|
||||
txc-skew-ps = <1800>;
|
||||
txen-skew-ps = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Attach to an explicitly-specified PHY */
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1800>;
|
||||
rxdv-skew-ps = <0>;
|
||||
txc-skew-ps = <1800>;
|
||||
txen-skew-ps = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
ethernet@70000 {
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
References
|
||||
|
||||
Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014.
|
||||
http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf
|
||||
|
||||
Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014.
|
||||
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf
|
||||
|
||||
Notes:
|
||||
|
||||
Note that a previous version of the Micrel ksz9021rl/rn Data Sheet
|
||||
was missing extended register 106 (transmit data pad skews), and
|
||||
incorrectly specified the ps per step as 200ps/step instead of
|
||||
120ps/step. The latest update to this document reflects the latest
|
||||
revision of the Micrel specification even though usage in the kernel
|
||||
still reflects that incorrect document.
|
||||
|
|
@ -1,57 +0,0 @@
|
|||
Micrel PHY properties.
|
||||
|
||||
These properties cover the base properties Micrel PHYs.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
|
||||
|
||||
Configure the LED mode with single value. The list of PHYs and the
|
||||
bits that are currently supported:
|
||||
|
||||
KSZ8001: register 0x1e, bits 15..14
|
||||
KSZ8041: register 0x1e, bits 15..14
|
||||
KSZ8021: register 0x1f, bits 5..4
|
||||
KSZ8031: register 0x1f, bits 5..4
|
||||
KSZ8051: register 0x1f, bits 5..4
|
||||
KSZ8081: register 0x1f, bits 5..4
|
||||
KSZ8091: register 0x1f, bits 5..4
|
||||
LAN8814: register EP5.0, bit 6
|
||||
|
||||
See the respective PHY datasheet for the mode values.
|
||||
|
||||
- micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
|
||||
bit selects 25 MHz mode
|
||||
|
||||
Setting the RMII Reference Clock Select bit enables 25 MHz rather
|
||||
than 50 MHz clock mode.
|
||||
|
||||
Note that this option is only needed for certain PHY revisions with a
|
||||
non-standard, inverted function of this configuration bit.
|
||||
Specifically, a clock reference ("rmii-ref" below) is always needed to
|
||||
actually select a mode.
|
||||
|
||||
- clocks, clock-names: contains clocks according to the common clock bindings.
|
||||
|
||||
supported clocks:
|
||||
- KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
|
||||
input clock. Used to determine the XI input clock.
|
||||
|
||||
- micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
|
||||
|
||||
Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled
|
||||
by the FXEN boot strapping pin. It can't be determined from the PHY
|
||||
registers whether the PHY is in fiber mode, so this boolean device tree
|
||||
property can be used to describe it.
|
||||
|
||||
In fiber mode, auto-negotiation is disabled and the PHY can only work in
|
||||
100base-fx (full and half duplex) modes.
|
||||
|
||||
- coma-mode-gpios: If present the given gpio will be deasserted when the
|
||||
PHY is probed.
|
||||
|
||||
Some PHYs have a COMA mode input pin which puts the PHY into
|
||||
isolate and power-down mode. On some boards this input is connected
|
||||
to a GPIO of the SoC.
|
||||
|
||||
Supported on the LAN8814.
|
||||
131
Documentation/devicetree/bindings/net/micrel.yaml
Normal file
131
Documentation/devicetree/bindings/net/micrel.yaml
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/micrel.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Micrel KSZ series PHYs and switches
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Stefan Eichenberger <eichest@gmail.com>
|
||||
|
||||
description:
|
||||
The Micrel KSZ series contains different network phys and switches.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ethernet-phy-id000e.7237 # KSZ8873MLL
|
||||
- ethernet-phy-id0022.1430 # KSZ886X
|
||||
- ethernet-phy-id0022.1435 # KSZ8863
|
||||
- ethernet-phy-id0022.1510 # KSZ8041
|
||||
- ethernet-phy-id0022.1537 # KSZ8041RNLI
|
||||
- ethernet-phy-id0022.1550 # KSZ8051
|
||||
- ethernet-phy-id0022.1555 # KSZ8021
|
||||
- ethernet-phy-id0022.1556 # KSZ8031
|
||||
- ethernet-phy-id0022.1560 # KSZ8081, KSZ8091
|
||||
- ethernet-phy-id0022.1570 # KSZ8061
|
||||
- ethernet-phy-id0022.161a # KSZ8001
|
||||
- ethernet-phy-id0022.1720 # KS8737
|
||||
|
||||
micrel,fiber-mode:
|
||||
type: boolean
|
||||
description: |
|
||||
If present the PHY is configured to operate in fiber mode.
|
||||
|
||||
The KSZ8041FTL variant supports fiber mode, enabled by the FXEN
|
||||
boot strapping pin. It can't be determined from the PHY registers
|
||||
whether the PHY is in fiber mode, so this boolean device tree
|
||||
property can be used to describe it.
|
||||
|
||||
In fiber mode, auto-negotiation is disabled and the PHY can only
|
||||
work in 100base-fx (full and half duplex) modes.
|
||||
|
||||
micrel,led-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
LED mode value to set for PHYs with configurable LEDs.
|
||||
|
||||
Configure the LED mode with single value. The list of PHYs and the
|
||||
bits that are currently supported:
|
||||
|
||||
KSZ8001: register 0x1e, bits 15..14
|
||||
KSZ8041: register 0x1e, bits 15..14
|
||||
KSZ8021: register 0x1f, bits 5..4
|
||||
KSZ8031: register 0x1f, bits 5..4
|
||||
KSZ8051: register 0x1f, bits 5..4
|
||||
KSZ8081: register 0x1f, bits 5..4
|
||||
KSZ8091: register 0x1f, bits 5..4
|
||||
|
||||
See the respective PHY datasheet for the mode values.
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
allOf:
|
||||
- $ref: ethernet-phy.yaml#
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ethernet-phy-id0022.1510
|
||||
then:
|
||||
properties:
|
||||
micrel,fiber-mode: false
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- ethernet-phy-id0022.1510
|
||||
- ethernet-phy-id0022.1555
|
||||
- ethernet-phy-id0022.1556
|
||||
- ethernet-phy-id0022.1550
|
||||
- ethernet-phy-id0022.1560
|
||||
- ethernet-phy-id0022.161a
|
||||
then:
|
||||
properties:
|
||||
micrel,led-mode: false
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- ethernet-phy-id0022.1555
|
||||
- ethernet-phy-id0022.1556
|
||||
- ethernet-phy-id0022.1560
|
||||
then:
|
||||
properties:
|
||||
clock-names:
|
||||
const: rmii-ref
|
||||
description:
|
||||
The RMII reference input clock. Used to determine the XI input
|
||||
clock.
|
||||
micrel,rmii-reference-clock-select-25-mhz:
|
||||
type: boolean
|
||||
description: |
|
||||
RMII Reference Clock Select bit selects 25 MHz mode
|
||||
|
||||
Setting the RMII Reference Clock Select bit enables 25 MHz rather
|
||||
than 50 MHz clock mode.
|
||||
|
||||
dependentRequired:
|
||||
micrel,rmii-reference-clock-select-25-mhz: [ clock-names ]
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethernet-phy@5 {
|
||||
compatible = "ethernet-phy-id0022.1510";
|
||||
reg = <5>;
|
||||
micrel,led-mode = <2>;
|
||||
micrel,fiber-mode;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user