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phy: qcom: qmp-pcie: Add IPQ9650 PCIe PHY support
Add support for the IPQ9650 platform, which includes three Gen3 x2 PCIe controllers and two Gen3 x1 PCIe controllers. The PHY instances require the on-chip refgen supply. Add the IPQ9650 Gen3 x1 and x2 QMP PCIe PHY configurations along with the refgen regulator supply. Note that an on-chip LDO, driven by the SoC CX, supplies the PHY voltages without requiring software control. Note that IPQ9650 does not support CX power collapse or rail scaling. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://patch.msgid.link/20260710-ipq9650_pcie_phy-v3-2-ef6018818d33@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Kathiravan Thirumoorthy
Vinod Koul
parent
7218d17e76
commit
ee6aa0f01d
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@ -956,6 +956,152 @@ static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
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};
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static const struct qmp_phy_init_tbl ipq9650_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_RESETSM_CNTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_TIMER1, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_TIMER2, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x68),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xaa),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xd4),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0b),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x53),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x29),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xaa),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x7d),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xa2),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x13),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb5),
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};
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static const struct qmp_phy_init_tbl ipq9650_pcie_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xb5),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x00),
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};
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static const struct qmp_phy_init_tbl ipq9650_pcie_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x11),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_VGA_GAIN2_LSB, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_VGA_GAIN2_MSB, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_POST_THRESH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x67),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
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};
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static const struct qmp_phy_init_tbl ipq9650_pcie_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x25),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x03),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
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};
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static const struct qmp_phy_init_tbl ipq9650_pcie_pcs_misc_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x1c),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST, 0x34),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST, 0x40),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
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};
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static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x10),
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@ -3864,6 +4010,10 @@ static const char * const qmp_phy_vreg_l[] = {
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"vdda-phy", "vdda-pll",
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};
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static const char * const ipq9650_qmp_phy_vreg_l[] = {
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"refgen",
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};
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static const char * const sm8550_qmp_phy_vreg_l[] = {
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"vdda-phy", "vdda-pll", "vdda-qref",
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};
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@ -3907,6 +4057,14 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
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.rx = 0x0400,
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};
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static const struct qmp_pcie_offsets qmp_pcie_offsets_9650_v4x1 = {
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.serdes = 0,
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.pcs = 0x0600,
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.pcs_misc = 0x0a00,
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.tx = 0x0200,
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.rx = 0x0400,
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};
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static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
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.serdes = 0,
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.pcs = 0x0a00,
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@ -4243,6 +4401,62 @@ static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = {
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.pipe_clock_rate = 250000000,
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};
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static const struct qmp_phy_cfg ipq9650_gen3x1_pciephy_cfg = {
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.lanes = 1,
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.offsets = &qmp_pcie_offsets_9650_v4x1,
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.tbls = {
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.serdes = ipq9650_pcie_serdes_tbl,
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.serdes_num = ARRAY_SIZE(ipq9650_pcie_serdes_tbl),
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.tx = ipq9650_pcie_tx_tbl,
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.tx_num = ARRAY_SIZE(ipq9650_pcie_tx_tbl),
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.rx = ipq9650_pcie_rx_tbl,
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.rx_num = ARRAY_SIZE(ipq9650_pcie_rx_tbl),
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.pcs = ipq9650_pcie_pcs_tbl,
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.pcs_num = ARRAY_SIZE(ipq9650_pcie_pcs_tbl),
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.pcs_misc = ipq9650_pcie_pcs_misc_tbl,
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.pcs_misc_num = ARRAY_SIZE(ipq9650_pcie_pcs_misc_tbl),
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},
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.reset_list = ipq8074_pciephy_reset_l,
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.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
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.vreg_list = ipq9650_qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(ipq9650_qmp_phy_vreg_l),
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.regs = pciephy_v4_regs_layout,
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.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
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.phy_status = PHYSTATUS,
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.pipe_clock_rate = 250000000,
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};
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static const struct qmp_phy_cfg ipq9650_gen3x2_pciephy_cfg = {
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.lanes = 2,
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.offsets = &qmp_pcie_offsets_v4x2,
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.tbls = {
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.serdes = ipq9650_pcie_serdes_tbl,
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.serdes_num = ARRAY_SIZE(ipq9650_pcie_serdes_tbl),
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.tx = ipq9650_pcie_tx_tbl,
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.tx_num = ARRAY_SIZE(ipq9650_pcie_tx_tbl),
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.rx = ipq9650_pcie_rx_tbl,
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.rx_num = ARRAY_SIZE(ipq9650_pcie_rx_tbl),
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.pcs = ipq9650_pcie_pcs_tbl,
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.pcs_num = ARRAY_SIZE(ipq9650_pcie_pcs_tbl),
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.pcs_misc = ipq9650_pcie_pcs_misc_tbl,
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.pcs_misc_num = ARRAY_SIZE(ipq9650_pcie_pcs_misc_tbl),
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},
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.reset_list = ipq8074_pciephy_reset_l,
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.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
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.vreg_list = ipq9650_qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(ipq9650_qmp_phy_vreg_l),
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.regs = pciephy_v4_regs_layout,
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.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
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.phy_status = PHYSTATUS,
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.pipe_clock_rate = 250000000,
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};
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static const struct qmp_phy_cfg qcs615_pciephy_cfg = {
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.lanes = 1,
|
||||
|
||||
|
|
@ -6073,6 +6287,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
|
|||
}, {
|
||||
.compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
|
||||
.data = &ipq9574_gen3x2_pciephy_cfg,
|
||||
}, {
|
||||
.compatible = "qcom,ipq9650-qmp-gen3x1-pcie-phy",
|
||||
.data = &ipq9650_gen3x1_pciephy_cfg,
|
||||
}, {
|
||||
.compatible = "qcom,ipq9650-qmp-gen3x2-pcie-phy",
|
||||
.data = &ipq9650_gen3x2_pciephy_cfg,
|
||||
}, {
|
||||
.compatible = "qcom,kaanapali-qmp-gen3x2-pcie-phy",
|
||||
.data = &qmp_v8_gen3x2_pciephy_cfg,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user